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drm/amd/display: dce60_hw_sequencer: add DCE6 specific functions (v2)
[Why] DCE6 has no bottom_pipe and no Blender HW DCE6 needs 'blank_target' set to false in order to turn on the display DCE6 has a specific dce60_pipe_control_lock() fuction that is a no op [How] Add DCE6 specific functions with needed private dce60_* dependent fuctions Comment DCE6 specific CTRC program visibility implementation Fix a typo in the initial header includes comment 's/DCE8/DCE6/g' Use dce60_apply_ctx_for_surface() in dce60_hw_sequencer_construct Use dce60_pipe_control_lock() in dce60_hw_sequencer_construct v2: add missing return type (Alex) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mauro Rossi
Alex Deucher
parent
102b2f587a
commit
167d74fd7d
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@ -32,22 +32,399 @@
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#include "dce110/dce110_hw_sequencer.h"
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#include "dce100/dce100_hw_sequencer.h"
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/* include DCE8 register header files */
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/* include DCE6 register header files */
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#include "dce/dce_6_0_d.h"
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#include "dce/dce_6_0_sh_mask.h"
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#define DC_LOGGER_INIT()
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/*******************************************************************************
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* Private definitions
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******************************************************************************/
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/***************************PIPE_CONTROL***********************************/
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/*
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* Check if FBC can be enabled
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*/
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static bool dce60_should_enable_fbc(struct dc *dc,
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struct dc_state *context,
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uint32_t *pipe_idx)
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{
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uint32_t i;
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struct pipe_ctx *pipe_ctx = NULL;
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struct resource_context *res_ctx = &context->res_ctx;
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unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
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ASSERT(dc->fbc_compressor);
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/* FBC memory should be allocated */
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if (!dc->ctx->fbc_gpu_addr)
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return false;
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/* Only supports single display */
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if (context->stream_count != 1)
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return false;
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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if (res_ctx->pipe_ctx[i].stream) {
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pipe_ctx = &res_ctx->pipe_ctx[i];
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if (!pipe_ctx)
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continue;
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/* fbc not applicable on underlay pipe */
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if (pipe_ctx->pipe_idx != underlay_idx) {
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*pipe_idx = i;
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break;
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}
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}
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}
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if (i == dc->res_pool->pipe_count)
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return false;
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if (!pipe_ctx->stream->link)
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return false;
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/* Only supports eDP */
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if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
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return false;
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/* PSR should not be enabled */
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if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
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return false;
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/* Nothing to compress */
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if (!pipe_ctx->plane_state)
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return false;
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/* Only for non-linear tiling */
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if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
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return false;
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return true;
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}
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/*
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* Enable FBC
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*/
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static void dce60_enable_fbc(
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struct dc *dc,
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struct dc_state *context)
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{
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uint32_t pipe_idx = 0;
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if (dce60_should_enable_fbc(dc, context, &pipe_idx)) {
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/* Program GRPH COMPRESSED ADDRESS and PITCH */
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struct compr_addr_and_pitch_params params = {0, 0, 0};
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struct compressor *compr = dc->fbc_compressor;
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
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params.source_view_width = pipe_ctx->stream->timing.h_addressable;
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params.source_view_height = pipe_ctx->stream->timing.v_addressable;
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params.inst = pipe_ctx->stream_res.tg->inst;
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compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
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compr->funcs->surface_address_and_pitch(compr, ¶ms);
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compr->funcs->set_fbc_invalidation_triggers(compr, 1);
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compr->funcs->enable_fbc(compr, ¶ms);
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}
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}
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/*******************************************************************************
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* Front End programming
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******************************************************************************/
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static void dce60_set_default_colors(struct pipe_ctx *pipe_ctx)
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{
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struct default_adjustment default_adjust = { 0 };
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default_adjust.force_hw_default = false;
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default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
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default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
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default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
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default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
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/* display color depth */
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default_adjust.color_depth =
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pipe_ctx->stream->timing.display_color_depth;
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/* Lb color depth */
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default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
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pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
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pipe_ctx->plane_res.xfm, &default_adjust);
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}
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/*******************************************************************************
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* In order to turn on surface we will program
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* CRTC
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*
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* DCE6 has no bottom_pipe and no Blender HW
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* We need to set 'blank_target' to false in order to turn on the display
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*
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* |-----------|------------|---------|
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* |curr pipe | set_blank | |
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* |Surface |blank_target| CRCT |
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* |visibility | argument | |
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* |-----------|------------|---------|
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* | off | true | blank |
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* | on | false | unblank |
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* |-----------|------------|---------|
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*
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******************************************************************************/
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static void dce60_program_surface_visibility(const struct dc *dc,
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struct pipe_ctx *pipe_ctx)
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{
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bool blank_target = false;
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/* DCE6 has no bottom_pipe and no Blender HW */
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if (!pipe_ctx->plane_state->visible)
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blank_target = true;
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/* DCE6 skip dce_set_blender_mode() but then proceed to 'unblank' CRTC */
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pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
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}
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static void dce60_get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
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struct tg_color *color)
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{
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uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
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switch (pipe_ctx->plane_res.scl_data.format) {
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case PIXEL_FORMAT_ARGB8888:
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/* set boarder color to red */
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color->color_r_cr = color_value;
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break;
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case PIXEL_FORMAT_ARGB2101010:
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/* set boarder color to blue */
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color->color_b_cb = color_value;
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break;
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case PIXEL_FORMAT_420BPP8:
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/* set boarder color to green */
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color->color_g_y = color_value;
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break;
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case PIXEL_FORMAT_420BPP10:
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/* set boarder color to yellow */
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color->color_g_y = color_value;
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color->color_r_cr = color_value;
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break;
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case PIXEL_FORMAT_FP16:
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/* set boarder color to white */
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color->color_r_cr = color_value;
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color->color_b_cb = color_value;
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color->color_g_y = color_value;
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break;
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default:
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break;
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}
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}
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static void dce60_program_scaler(const struct dc *dc,
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const struct pipe_ctx *pipe_ctx)
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{
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struct tg_color color = {0};
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/* DCE6 skips DCN TOFPGA check for transform_set_pixel_storage_depth == NULL */
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if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
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dce60_get_surface_visual_confirm_color(pipe_ctx, &color);
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else
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color_space_to_black_color(dc,
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pipe_ctx->stream->output_color_space,
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&color);
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pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
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pipe_ctx->plane_res.xfm,
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pipe_ctx->plane_res.scl_data.lb_params.depth,
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&pipe_ctx->stream->bit_depth_params);
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if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
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/*
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* The way 420 is packed, 2 channels carry Y component, 1 channel
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* alternate between Cb and Cr, so both channels need the pixel
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* value for Y
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*/
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if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
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color.color_r_cr = color.color_g_y;
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pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
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pipe_ctx->stream_res.tg,
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&color);
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}
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pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
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&pipe_ctx->plane_res.scl_data);
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}
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static void
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dce60_program_front_end_for_pipe(
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struct dc *dc, struct pipe_ctx *pipe_ctx)
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{
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struct mem_input *mi = pipe_ctx->plane_res.mi;
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struct dc_plane_state *plane_state = pipe_ctx->plane_state;
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struct xfm_grph_csc_adjustment adjust;
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struct out_csc_color_matrix tbl_entry;
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unsigned int i;
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struct dce_hwseq *hws = dc->hwseq;
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DC_LOGGER_INIT();
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memset(&tbl_entry, 0, sizeof(tbl_entry));
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memset(&adjust, 0, sizeof(adjust));
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adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
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dce_enable_fe_clock(dc->hwseq, mi->inst, true);
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dce60_set_default_colors(pipe_ctx);
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if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
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== true) {
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tbl_entry.color_space =
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pipe_ctx->stream->output_color_space;
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for (i = 0; i < 12; i++)
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tbl_entry.regval[i] =
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pipe_ctx->stream->csc_color_matrix.matrix[i];
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pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
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(pipe_ctx->plane_res.xfm, &tbl_entry);
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}
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if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
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adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
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for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
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adjust.temperature_matrix[i] =
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pipe_ctx->stream->gamut_remap_matrix.matrix[i];
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}
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pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
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pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
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dce60_program_scaler(dc, pipe_ctx);
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mi->funcs->mem_input_program_surface_config(
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mi,
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plane_state->format,
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&plane_state->tiling_info,
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&plane_state->plane_size,
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plane_state->rotation,
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NULL,
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false);
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if (mi->funcs->set_blank)
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mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
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if (dc->config.gpu_vm_support)
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mi->funcs->mem_input_program_pte_vm(
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pipe_ctx->plane_res.mi,
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plane_state->format,
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&plane_state->tiling_info,
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plane_state->rotation);
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/* Moved programming gamma from dc to hwss */
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if (pipe_ctx->plane_state->update_flags.bits.full_update ||
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pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
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pipe_ctx->plane_state->update_flags.bits.gamma_change)
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hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
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if (pipe_ctx->plane_state->update_flags.bits.full_update)
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hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
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DC_LOG_SURFACE(
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"Pipe:%d %p: addr hi:0x%x, "
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"addr low:0x%x, "
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"src: %d, %d, %d,"
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" %d; dst: %d, %d, %d, %d;"
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"clip: %d, %d, %d, %d\n",
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pipe_ctx->pipe_idx,
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(void *) pipe_ctx->plane_state,
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pipe_ctx->plane_state->address.grph.addr.high_part,
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pipe_ctx->plane_state->address.grph.addr.low_part,
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pipe_ctx->plane_state->src_rect.x,
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pipe_ctx->plane_state->src_rect.y,
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pipe_ctx->plane_state->src_rect.width,
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pipe_ctx->plane_state->src_rect.height,
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pipe_ctx->plane_state->dst_rect.x,
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pipe_ctx->plane_state->dst_rect.y,
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pipe_ctx->plane_state->dst_rect.width,
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pipe_ctx->plane_state->dst_rect.height,
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pipe_ctx->plane_state->clip_rect.x,
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pipe_ctx->plane_state->clip_rect.y,
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pipe_ctx->plane_state->clip_rect.width,
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pipe_ctx->plane_state->clip_rect.height);
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DC_LOG_SURFACE(
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"Pipe %d: width, height, x, y\n"
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"viewport:%d, %d, %d, %d\n"
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"recout: %d, %d, %d, %d\n",
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pipe_ctx->pipe_idx,
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pipe_ctx->plane_res.scl_data.viewport.width,
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pipe_ctx->plane_res.scl_data.viewport.height,
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pipe_ctx->plane_res.scl_data.viewport.x,
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pipe_ctx->plane_res.scl_data.viewport.y,
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pipe_ctx->plane_res.scl_data.recout.width,
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pipe_ctx->plane_res.scl_data.recout.height,
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pipe_ctx->plane_res.scl_data.recout.x,
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pipe_ctx->plane_res.scl_data.recout.y);
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}
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static void dce60_apply_ctx_for_surface(
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struct dc *dc,
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const struct dc_stream_state *stream,
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int num_planes,
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struct dc_state *context)
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{
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int i;
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if (num_planes == 0)
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return;
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if (dc->fbc_compressor)
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dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
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for (i = 0; i < dc->res_pool->pipe_count; i++) {
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struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
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if (pipe_ctx->stream != stream)
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continue;
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/* Need to allocate mem before program front end for Fiji */
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pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
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pipe_ctx->plane_res.mi,
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pipe_ctx->stream->timing.h_total,
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pipe_ctx->stream->timing.v_total,
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pipe_ctx->stream->timing.pix_clk_100hz / 10,
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context->stream_count);
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dce60_program_front_end_for_pipe(dc, pipe_ctx);
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dc->hwss.update_plane_addr(dc, pipe_ctx);
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dce60_program_surface_visibility(dc, pipe_ctx);
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}
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if (dc->fbc_compressor)
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dce60_enable_fbc(dc, context);
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}
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void dce60_hw_sequencer_construct(struct dc *dc)
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{
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dce110_hw_sequencer_construct(dc);
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dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
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dc->hwss.pipe_control_lock = dce_pipe_control_lock;
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dc->hwss.apply_ctx_for_surface = dce60_apply_ctx_for_surface;
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dc->hwss.pipe_control_lock = dce60_pipe_control_lock;
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dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
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dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
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}
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