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staging: wilc1000: define macros for different register address for SDIO
Instead of using hardcoded value for SDIO register address added the macro for them. Signed-off-by: Ajay Singh <ajay.kathat@microchip.com> Link: https://lore.kernel.org/r/20200214172250.13026-7-ajay.kathat@microchip.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -183,8 +183,8 @@ static int wilc_sdio_reset(struct wilc *wilc)
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cmd.read_write = 1;
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cmd.function = 0;
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cmd.raw = 0;
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cmd.address = 0x6;
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cmd.data = 0x8;
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cmd.address = SDIO_CCCR_ABORT;
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cmd.data = WILC_SDIO_CCCR_ABORT_RESET;
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev, "Fail cmd 52, reset cmd ...\n");
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@ -266,27 +266,30 @@ static int wilc_sdio_set_func0_csa_address(struct wilc *wilc, u32 adr)
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cmd.read_write = 1;
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cmd.function = 0;
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cmd.raw = 0;
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cmd.address = 0x10c;
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cmd.address = WILC_SDIO_FBR_CSA_REG;
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cmd.data = (u8)adr;
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev, "Failed cmd52, set 0x10c data...\n");
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dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
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cmd.address);
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return ret;
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}
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cmd.address = 0x10d;
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cmd.address = WILC_SDIO_FBR_CSA_REG + 1;
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cmd.data = (u8)(adr >> 8);
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev, "Failed cmd52, set 0x10d data...\n");
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dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
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cmd.address);
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return ret;
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}
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cmd.address = 0x10e;
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cmd.address = WILC_SDIO_FBR_CSA_REG + 2;
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cmd.data = (u8)(adr >> 16);
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev, "Failed cmd52, set 0x10e data...\n");
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dev_err(&func->dev, "Failed cmd52, set %04x data...\n",
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cmd.address);
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return ret;
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}
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@ -337,7 +340,7 @@ static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data)
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cpu_to_le32s(&data);
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if (addr >= 0xf0 && addr <= 0xff) {
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if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
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struct sdio_cmd52 cmd;
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cmd.read_write = 1;
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@ -361,7 +364,7 @@ static int wilc_sdio_write_reg(struct wilc *wilc, u32 addr, u32 data)
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cmd.read_write = 1;
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cmd.function = 0;
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cmd.address = 0x10f;
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cmd.address = WILC_SDIO_FBR_DATA_REG;
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cmd.block_mode = 0;
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cmd.increment = 1;
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cmd.count = 4;
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@ -390,13 +393,13 @@ static int wilc_sdio_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
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* func 0 access
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**/
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cmd.function = 0;
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cmd.address = 0x10f;
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cmd.address = WILC_SDIO_FBR_DATA_REG;
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} else {
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/**
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* func 1 access
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**/
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cmd.function = 1;
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cmd.address = 0;
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cmd.address = WILC_SDIO_F1_DATA_REG;
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}
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size = ALIGN(size, 4);
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@ -455,7 +458,7 @@ static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data)
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struct wilc_sdio *sdio_priv = wilc->bus_data;
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int ret;
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if (addr >= 0xf0 && addr <= 0xff) {
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if (addr >= 0xf0 && addr <= 0xff) { /* only vendor specific registers */
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struct sdio_cmd52 cmd;
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cmd.read_write = 0;
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@ -478,7 +481,7 @@ static int wilc_sdio_read_reg(struct wilc *wilc, u32 addr, u32 *data)
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cmd.read_write = 0;
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cmd.function = 0;
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cmd.address = 0x10f;
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cmd.address = WILC_SDIO_FBR_DATA_REG;
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cmd.block_mode = 0;
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cmd.increment = 1;
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cmd.count = 4;
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@ -511,13 +514,13 @@ static int wilc_sdio_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
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* func 0 access
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**/
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cmd.function = 0;
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cmd.address = 0x10f;
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cmd.address = WILC_SDIO_FBR_DATA_REG;
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} else {
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/**
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* func 1 access
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**/
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cmd.function = 1;
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cmd.address = 0;
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cmd.address = WILC_SDIO_F1_DATA_REG;
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}
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size = ALIGN(size, 4);
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@ -598,8 +601,8 @@ static int wilc_sdio_init(struct wilc *wilc, bool resume)
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cmd.read_write = 1;
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cmd.function = 0;
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cmd.raw = 1;
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cmd.address = 0x100;
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cmd.data = 0x80;
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cmd.address = SDIO_FBR_BASE(func->num);
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cmd.data = SDIO_FBR_ENABLE_CSA;
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev, "Fail cmd 52, enable csa...\n");
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@ -622,8 +625,8 @@ static int wilc_sdio_init(struct wilc *wilc, bool resume)
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cmd.read_write = 1;
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cmd.function = 0;
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cmd.raw = 1;
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cmd.address = 0x2;
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cmd.data = 0x2;
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cmd.address = SDIO_CCCR_IOEx;
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cmd.data = WILC_SDIO_CCCR_IO_EN_FUNC1;
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev,
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@ -637,7 +640,7 @@ static int wilc_sdio_init(struct wilc *wilc, bool resume)
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cmd.read_write = 0;
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cmd.function = 0;
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cmd.raw = 0;
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cmd.address = 0x3;
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cmd.address = SDIO_CCCR_IORx;
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loop = 3;
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do {
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cmd.data = 0;
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@ -647,7 +650,7 @@ static int wilc_sdio_init(struct wilc *wilc, bool resume)
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"Fail cmd 52, get IOR register...\n");
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return ret;
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}
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if (cmd.data == 0x2)
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if (cmd.data == WILC_SDIO_CCCR_IO_EN_FUNC1)
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break;
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} while (loop--);
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@ -671,8 +674,8 @@ static int wilc_sdio_init(struct wilc *wilc, bool resume)
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cmd.read_write = 1;
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cmd.function = 0;
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cmd.raw = 1;
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cmd.address = 0x4;
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cmd.data = 0x3;
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cmd.address = SDIO_CCCR_IENx;
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cmd.data = WILC_SDIO_CCCR_IEN_MASTER | WILC_SDIO_CCCR_IEN_FUNC1;
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev, "Fail cmd 52, set IEN register...\n");
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@ -711,12 +714,12 @@ static int wilc_sdio_read_size(struct wilc *wilc, u32 *size)
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cmd.read_write = 0;
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cmd.function = 0;
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cmd.raw = 0;
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cmd.address = 0xf2;
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cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG;
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cmd.data = 0;
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wilc_sdio_cmd52(wilc, &cmd);
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tmp = cmd.data;
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cmd.address = 0xf3;
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cmd.address = WILC_SDIO_INTERRUPT_DATA_SZ_REG + 1;
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cmd.data = 0;
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wilc_sdio_cmd52(wilc, &cmd);
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tmp |= (cmd.data << 8);
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@ -740,10 +743,10 @@ static int wilc_sdio_read_int(struct wilc *wilc, u32 *int_status)
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**/
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if (!sdio_priv->irq_gpio) {
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cmd.function = 1;
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cmd.address = 0x04;
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cmd.address = WILC_SDIO_EXT_IRQ_FLAG_REG;
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} else {
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cmd.function = 0;
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cmd.address = 0xf7;
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cmd.address = WILC_SDIO_IRQ_FLAG_REG;
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}
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cmd.raw = 0;
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cmd.read_write = 0;
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@ -789,14 +792,14 @@ static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val)
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cmd.read_write = 1;
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cmd.function = 0;
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cmd.raw = 0;
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cmd.address = 0xf8;
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cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
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cmd.data = reg;
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev,
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"Failed cmd52, set 0xf8 data (%d) ...\n",
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__LINE__);
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"Failed cmd52, set (%02x) data (%d) ...\n",
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cmd.address, __LINE__);
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return ret;
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}
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}
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@ -819,14 +822,14 @@ static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val)
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cmd.read_write = 1;
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cmd.function = 0;
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cmd.raw = 0;
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cmd.address = 0xf8;
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cmd.address = WILC_SDIO_IRQ_CLEAR_FLAG_REG;
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cmd.data = BIT(i);
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev,
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"Failed cmd52, set 0xf8 data (%d) ...\n",
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__LINE__);
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"Failed cmd52, set (%02x) data (%d) ...\n",
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cmd.address, __LINE__);
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return ret;
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}
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flags &= ~BIT(i);
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@ -860,13 +863,13 @@ static int wilc_sdio_clear_int_ext(struct wilc *wilc, u32 val)
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cmd.read_write = 1;
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cmd.function = 0;
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cmd.raw = 0;
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cmd.address = 0xf6;
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cmd.address = WILC_SDIO_VMM_TBL_CTRL_REG;
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cmd.data = vmm_ctl;
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ret = wilc_sdio_cmd52(wilc, &cmd);
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if (ret) {
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dev_err(&func->dev,
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"Failed cmd52, set 0xf6 data (%d) ...\n",
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__LINE__);
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"Failed cmd52, set (%02x) data (%d) ...\n",
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cmd.address, __LINE__);
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return ret;
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}
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}
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@ -93,6 +93,42 @@
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#define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \
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WILC_SPI_REG_BASE)
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/* Functions IO enables bits */
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#define WILC_SDIO_CCCR_IO_EN_FUNC1 BIT(1)
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/* Function/Interrupt enables bits */
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#define WILC_SDIO_CCCR_IEN_MASTER BIT(0)
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#define WILC_SDIO_CCCR_IEN_FUNC1 BIT(1)
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/* Abort CCCR register bits */
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#define WILC_SDIO_CCCR_ABORT_RESET BIT(3)
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/* Vendor specific CCCR registers */
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#define WILC_SDIO_WAKEUP_REG 0xf0
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#define WILC_SDIO_WAKEUP_BIT BIT(0)
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#define WILC_SDIO_CLK_STATUS_REG 0xf1
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#define WILC_SDIO_CLK_STATUS_BIT BIT(0)
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#define WILC_SDIO_INTERRUPT_DATA_SZ_REG 0xf2 /* Read size (2 bytes) */
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#define WILC_SDIO_VMM_TBL_CTRL_REG 0xf6
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#define WILC_SDIO_IRQ_FLAG_REG 0xf7
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#define WILC_SDIO_IRQ_CLEAR_FLAG_REG 0xf8
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#define WILC_SDIO_HOST_TO_FW_REG 0xfa
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#define WILC_SDIO_HOST_TO_FW_BIT BIT(0)
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#define WILC_SDIO_FW_TO_HOST_REG 0xfc
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#define WILC_SDIO_FW_TO_HOST_BIT BIT(0)
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/* Function 1 specific FBR register */
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#define WILC_SDIO_FBR_CSA_REG 0x10C /* CSA pointer (3 bytes) */
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#define WILC_SDIO_FBR_DATA_REG 0x10F
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#define WILC_SDIO_F1_DATA_REG 0x0
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#define WILC_SDIO_EXT_IRQ_FLAG_REG 0x4
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#define WILC_AHB_DATA_MEM_BASE 0x30000
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#define WILC_AHB_SHARE_MEM_BASE 0xd0000
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