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drm/amdgpu: add support for GC IP version 11.7.1

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Initialize GC IP 11_7_1

Signed-off-by: Granthali Vinodkumar Dhandar <granthali.vinodkumardhandar@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit a928d8d81ec5cdb5a8944d08136720811efad0f6)
This commit is contained in:
Granthali Vinodkumar Dhandar 2026-06-17 18:04:28 +05:30 committed by Alex Deucher
parent ff8cb5cee0
commit 166e1100c1
10 changed files with 59 additions and 1 deletions
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6
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
View File

@ -2120,6 +2120,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
break;
case IP_VERSION(12, 0, 0):
@ -2182,6 +2183,7 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
break;
case IP_VERSION(12, 0, 0):
@ -2509,6 +2511,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
break;
case IP_VERSION(12, 0, 0):
@ -2723,6 +2726,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
adev->enable_mes = true;
adev->enable_mes_kiq = true;
@ -3132,6 +3136,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
adev->family = AMDGPU_FAMILY_GC_11_5_0;
break;
case IP_VERSION(12, 0, 0):
@ -3162,6 +3167,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
adev->flags |= AMD_IS_APU;
break;
default:

1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
View File

@ -978,6 +978,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
/* Don't enable it by default yet.
*/
if (amdgpu_tmz < 1) {

12
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View File

@ -137,6 +137,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_7_0_pfp.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_0_me.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_0_mec.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_0_rlc.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_1_pfp.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_1_me.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_1_mec.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_1_rlc.bin");
static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = {
SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
@ -1133,6 +1137,7 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@ -1618,6 +1623,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 2;
@ -3092,7 +3098,8 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3) ||
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4) ||
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 6) ||
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 7, 0))
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 7, 0) ||
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 7, 1))
bootload_status = RREG32_SOC15(GC, 0,
regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
else
@ -5766,6 +5773,7 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
break;
default:
@ -5807,6 +5815,7 @@ static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
if (!enable)
amdgpu_gfx_off_ctrl(adev, false);
@ -5844,6 +5853,7 @@ static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
gfx_v11_0_update_gfx_clock_gating(adev,
state == AMD_CG_STATE_GATE);
break;

2
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
View File

@ -607,6 +607,7 @@ static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs;
break;
default:
@ -783,6 +784,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
/*

1
drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
View File

@ -44,6 +44,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_3_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_4_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_6_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_0_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_1_imu.bin");
static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
{

2
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
View File

@ -62,6 +62,8 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes_2.bin");
MODULE_FIRMWARE("amdgpu/gc_11_5_6_mes1.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes_2.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_0_mes1.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes_2.bin");
MODULE_FIRMWARE("amdgpu/gc_11_7_1_mes1.bin");
static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block);
static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block);

2
drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
View File

@ -33,6 +33,8 @@
MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_15_0_0_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_15_0_9_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_15_0_9_ta.bin");
static int psp_v15_0_0_init_microcode(struct psp_context *psp)
{

28
drivers/gpu/drm/amd/amdgpu/soc21.c
View File

@ -866,6 +866,34 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block)
AMD_PG_SUPPORT_GFX_PG;
adev->external_rev_id = adev->rev_id + 0xF;
break;
case IP_VERSION(11, 7, 1):
adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_FGCG |
AMD_CG_SUPPORT_REPEATER_FGCG |
AMD_CG_SUPPORT_GFX_PERF_CLK |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS |
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_HDP_DS |
AMD_CG_SUPPORT_HDP_SD |
AMD_CG_SUPPORT_ATHUB_MGCG |
AMD_CG_SUPPORT_ATHUB_LS |
AMD_CG_SUPPORT_IH_CG |
AMD_CG_SUPPORT_BIF_MGCG |
AMD_CG_SUPPORT_BIF_LS;
adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_JPEG_DPG |
AMD_PG_SUPPORT_JPEG |
AMD_PG_SUPPORT_GFX_PG;
adev->external_rev_id = adev->rev_id + 0x40;
break;
default:
/* FIXME: not supported yet */
return -EINVAL;

1
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
View File

@ -1716,6 +1716,7 @@ int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pc
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
/* Cacheline size not available in IP discovery for gc11.
* kfd_fill_gpu_cache_info_from_gfx_config to hard code it
*/

5
drivers/gpu/drm/amd/amdkfd/kfd_device.c
View File

@ -170,6 +170,7 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
case IP_VERSION(11, 5, 4):
case IP_VERSION(11, 5, 6):
case IP_VERSION(11, 7, 0):
case IP_VERSION(11, 7, 1):
kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
break;
case IP_VERSION(12, 0, 0):
@ -456,6 +457,10 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
gfx_target_version = 110700;
f2g = &gfx_v11_kfd2kgd;
break;
case IP_VERSION(11, 7, 1):
gfx_target_version = 110701;
f2g = &gfx_v11_kfd2kgd;
break;
case IP_VERSION(12, 0, 0):
gfx_target_version = 120000;
f2g = &gfx_v12_kfd2kgd;