From 16440d6e4bf1175cda83438d9f9a8ae84bfcf0ee Mon Sep 17 00:00:00 2001 From: Koichiro Den Date: Fri, 9 Oct 2026 13:54:50 +0900 Subject: [PATCH] cxl/port: Convert PCIe link latency to nanoseconds Commit 51293c565cf4 ("cxl: Fix incorrect region perf data calculation") converted CDAT latencies to nanoseconds and removed the conversion in cxl_region_perf_data_calculate(), but left PCIe link latencies in picoseconds. This inflates the FlitLatency contribution to region and node latencies by a factor of 1000, exposing incorrect values in sysfs. The resulting abstract distances can incorrectly reverse the memory tier ordering of nodes. Convert the FlitLatency contribution to nanoseconds before adding it to the access coordinates, rounding up as cdat_normalize() does. Fixes: 51293c565cf4 ("cxl: Fix incorrect region perf data calculation") Cc: stable@vger.kernel.org Signed-off-by: Koichiro Den Reviewed-by: Alison Schofield Reviewed-by: Dave Jiang Link: https://patch.msgid.link/20261009045452.1107921-2-den@valinux.co.jp Signed-off-by: Dave Jiang --- drivers/cxl/core/port.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index a7bfe320c802..376d1d720709 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2392,6 +2392,9 @@ EXPORT_SYMBOL_NS_GPL(schedule_cxl_memdev_detach, "CXL"); static void add_latency(struct access_coordinate *c, long latency) { + /* Convert link latency from picoseconds to nanoseconds. */ + latency = DIV_ROUND_UP(latency, 1000); + for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) { c[i].write_latency += latency; c[i].read_latency += latency;