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ARM: dts: suniv: f1c100s: add I2C DT nodes

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The Allwinner F1C100s series of SoCs contain three I2C controllers
compatible to the ones used in other Allwinner SoCs.

Add the DT nodes describing the resources of the controllers.
At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so
include those pins already, to simplify referencing them later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20221107005433.11079-4-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
This commit is contained in:
Andre Przywara 2022-11-07 00:54:26 +00:00 committed by Jernej Skrabec
parent 77eac2b9e1
commit 16245374b6
1 changed files with 42 additions and 0 deletions
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42
arch/arm/boot/dts/suniv-f1c100s.dtsi
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@ -166,6 +166,12 @@ mmc0_pins: mmc0-pins {
drive-strength = <30>;
};
/omit-if-no-ref/
i2c0_pd_pins: i2c0-pd-pins {
pins = "PD0", "PD12";
function = "i2c0";
};
spi0_pc_pins: spi0-pc-pins {
pins = "PC0", "PC1", "PC2", "PC3";
function = "spi0";
@ -177,6 +183,42 @@ uart0_pe_pins: uart0-pe-pins {
};
};
i2c0: i2c@1c27000 {
compatible = "allwinner,suniv-f1c100s-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x01c27000 0x400>;
interrupts = <7>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@1c27400 {
compatible = "allwinner,suniv-f1c100s-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x01c27400 0x400>;
interrupts = <8>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@1c27800 {
compatible = "allwinner,suniv-f1c100s-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x01c27800 0x400>;
interrupts = <9>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
timer@1c20c00 {
compatible = "allwinner,suniv-f1c100s-timer";
reg = <0x01c20c00 0x90>;