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drm/amdgpu: Add ioctl infra for exporting/importing UALink handles

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Add the ioctl infrastructure to support exporting and importing BOs
to facilitate NPA based memory sharing across GPUs in a rack scale
setup.

Proposed userspace:
35959f8e12/projects/rocr-runtime/libhsakmt/src/memory.c (L971)
35959f8e12/projects/rocr-runtime/libhsakmt/src/memory.c (L1036)

v2: Move the ioctl wire-up to the end of the series.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Horatio Zhang <hongkun.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mukul Joshi 2026-08-20 22:40:53 +08:00 committed by Alex Deucher
parent b67d2d039f
commit 15d1c306d8
4 changed files with 78 additions and 0 deletions
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2
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -54,6 +54,7 @@
#include "amdgpu_userq.h"
#include "amdgpu_userq_fence.h"
#include "../amdxcp/amdgpu_xcp_drv.h"
#include "amdgpu_ualink.h"
/*
* KMS wrapper.
@ -3120,6 +3121,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_PROC_OPTIONS, amdgpu_proc_options_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(AMDGPU_UALINK_HANDLE, amdgpu_gem_ualink_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
};
static const struct drm_driver amdgpu_kms_driver = {

44
drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c
View File

@ -4008,6 +4008,50 @@ int amdgpu_ualink_export_handle(struct drm_device *dev, struct drm_file *filp,
return r;
}
int amdgpu_gem_ualink_handle_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
union drm_amdgpu_ualink_handle *args = data;
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_ualink_handle handle = {};
u32 gem_handle;
int r, fd = -1;
if (adev->ualink.info->accel_state !=
AMDGPU_UALINK_ACCEL_STATE_ACTIVE) {
dev_err(adev->dev,
"ualink device is not in active state in vpod\n");
return -EOPNOTSUPP;
}
/* The input and output members of the ioctl argument alias each other.
* Latch every input field before invoking the handlers, and only write
* the output fields afterwards.
*/
switch (args->in.op) {
case DRM_AMDGPU_UALINK_HANDLE_OP_EXPORT:
gem_handle = args->in.gem_handle;
r = amdgpu_ualink_export_handle(dev, filp, gem_handle, &handle);
if (!r) {
args->out.export_ualink_handle[0] = handle.handle_lo;
args->out.export_ualink_handle[1] = handle.handle_hi;
}
break;
case DRM_AMDGPU_UALINK_HANDLE_OP_IMPORT:
handle.handle_lo = args->in.import_ualink_handle[0];
handle.handle_hi = args->in.import_ualink_handle[1];
r = amdgpu_ualink_import_handle(dev, &handle, &fd);
if (!r)
args->out.import_dmabuf_handle = fd;
break;
default:
r = -EINVAL;
break;
}
return r;
}
int amdgpu_ualink_manager_start(struct amdgpu_device *adev)
{
int i, r;

2
drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h
View File

@ -413,6 +413,8 @@ int amdgpu_ualink_export_handle(struct drm_device *dev, struct drm_file *filp,
int amdgpu_ualink_import_handle(struct drm_device *dev,
const struct amdgpu_ualink_handle *ualink_handle,
int *fd_out);
int amdgpu_gem_ualink_handle_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
void amdgpu_ualink_revoke_exported_memory(struct amdgpu_bo *bo);
int ualink_ip_hw_init(struct amdgpu_ip_block *ip_block);

30
include/uapi/drm/amdgpu_drm.h
View File

@ -59,6 +59,7 @@ extern "C" {
#define DRM_AMDGPU_USERQ_WAIT 0x18
#define DRM_AMDGPU_GEM_LIST_HANDLES 0x19
#define DRM_AMDGPU_PROC_OPTIONS 0x1A
#define DRM_AMDGPU_UALINK_HANDLE 0x1B
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@ -81,6 +82,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
#define DRM_IOCTL_AMDGPU_PROC_OPTIONS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options)
#define DRM_IOCTL_AMDGPU_UALINK_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_UALINK_HANDLE, union drm_amdgpu_ualink_handle)
/**
* DOC: memory domains
@ -1705,6 +1707,34 @@ struct drm_amdgpu_proc_options {
} kfd_sigbus_delay;
};
#define DRM_AMDGPU_UALINK_HANDLE_OP_EXPORT 0
#define DRM_AMDGPU_UALINK_HANDLE_OP_IMPORT 1
struct drm_amdgpu_ualink_handle_in {
/* Export or import */
__u32 op;
/* For future use, no flags defined so far */
__u32 flags;
union {
/* GEM handle of the BO to export */
__u32 gem_handle;
/* UALink handle to import */
__u64 import_ualink_handle[2];
};
};
union drm_amdgpu_ualink_handle_out {
/* Exported UALink handle */
__u64 export_ualink_handle[2];
/** DMABuf representing the imported UALink handle */
__u32 import_dmabuf_handle;
};
union drm_amdgpu_ualink_handle {
struct drm_amdgpu_ualink_handle_in in;
union drm_amdgpu_ualink_handle_out out;
};
#if defined(__cplusplus)
}
#endif