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Merge branch 'pci/controller/xilinx-cpm'
- Add DT and driver support for optional PERST# for use in warm reset scenarios (Sai Krishna Musham) * pci/controller/xilinx-cpm: PCI: xilinx-cpm: Add support for PCIe RP PERST# signal dt-bindings: PCI: xilinx-versal-cpm: Add PERST# and reset support
This commit is contained in:
Bjorn Helgaas
commit
15b0d8e9db
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@ -41,6 +41,10 @@ properties:
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description:
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Maps a Requester ID to an MSI controller and associated MSI sideband data.
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resets:
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description: Reset for the PCIe controller.
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maxItems: 1
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ranges:
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maxItems: 2
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@ -61,6 +65,17 @@ properties:
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interrupt-controller: true
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patternProperties:
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'^pcie@[0-2],0$':
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type: object
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$ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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reg:
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maxItems: 1
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unevaluatedProperties: false
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required:
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- reg
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- reg-names
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@ -76,6 +91,9 @@ unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/xlnx-versal-resets.h>
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versal {
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#address-cells = <2>;
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#size-cells = <2>;
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@ -99,6 +117,16 @@ examples:
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reg = <0x0 0xfca10000 0x0 0x1000>,
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<0x6 0x00000000 0x0 0x10000000>;
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reg-names = "cpm_slcr", "cfg";
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resets = <&versal_reset VERSAL_RST_PCIE_CORE0>;
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pcie@0,0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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pcie_intc_0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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@ -127,6 +155,16 @@ examples:
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<0x06 0x00000000 0x00 0x1000000>,
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<0x00 0xfce20000 0x00 0x1000000>;
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reg-names = "cpm_slcr", "cfg", "cpm_csr";
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resets = <&versal_reset VERSAL_RST_PCIE_CORE0>;
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pcie@0,0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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pcie_intc_1: interrupt-controller {
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#address-cells = <0>;
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@ -6,6 +6,8 @@
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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@ -16,6 +18,7 @@
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/reset.h>
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#include "../pci.h"
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#include "pcie-xilinx-common.h"
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@ -113,6 +116,8 @@ struct xilinx_cpm_variant {
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* @irq: Error interrupt number
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* @lock: lock protecting shared register access
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* @variant: CPM version check pointer
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* @perst_gpio: GPIO descriptor for PERST# signal handling
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* @rstc: Pointer to the PCIe controller reset
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*/
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struct xilinx_cpm_pcie {
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struct device *dev;
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@ -125,6 +130,8 @@ struct xilinx_cpm_pcie {
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int irq;
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raw_spinlock_t lock;
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const struct xilinx_cpm_variant *variant;
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struct gpio_desc *perst_gpio;
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struct reset_control *rstc;
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};
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static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
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@ -389,7 +396,7 @@ static int xilinx_cpm_pcie_init_irq_domain(struct xilinx_cpm_pcie *port)
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struct device_node *pcie_intc_node;
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/* Setup INTx */
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pcie_intc_node = of_get_next_child(node, NULL);
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pcie_intc_node = of_get_child_by_name(node, "interrupt-controller");
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if (!pcie_intc_node) {
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dev_err(dev, "No PCIe Intc node found\n");
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return -EINVAL;
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@ -469,6 +476,22 @@ static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port)
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return 0;
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}
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/**
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* xilinx_cpm_pcie_reset - Reset the PCIe controller and deassert PERST#
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* @port: PCIe port information
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*
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* Reset the PCIe controller and then release the PERST# signal so that the
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* link can train once the bridge is enabled.
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*/
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static void xilinx_cpm_pcie_reset(struct xilinx_cpm_pcie *port)
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{
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reset_control_assert(port->rstc);
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udelay(PCIE_T_PERST_US);
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reset_control_deassert(port->rstc);
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gpiod_set_value_cansleep(port->perst_gpio, 0);
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msleep(PCIE_RESET_CONFIG_WAIT_MS);
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}
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/**
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* xilinx_cpm_pcie_init_port - Initialize hardware
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* @port: PCIe port information
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@ -480,6 +503,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
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if (variant->version == CPM5NC_HOST)
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return;
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if (port->perst_gpio || port->rstc)
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xilinx_cpm_pcie_reset(port);
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if (cpm_pcie_link_up(port))
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dev_info(port->dev, "PCIe Link is UP\n");
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else
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@ -512,6 +538,42 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
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XILINX_CPM_PCIE_REG_RPSC);
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}
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/**
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* xilinx_cpm_pcie_parse_port - Parse the PCIe Root Port child node
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* @port: PCIe port information
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*
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* Read the PERST# GPIO from the Root Port child node.
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*
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* Return: '0' on success and error value on failure
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*/
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static int xilinx_cpm_pcie_parse_port(struct xilinx_cpm_pcie *port)
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{
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struct device *dev = port->dev;
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/*
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* This platform currently supports only one Root Port, so the loop
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* will execute only once.
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* TODO: Enhance the driver to handle multiple Root Ports in the future.
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*/
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for_each_child_of_node_with_prefix(dev->of_node, pcie_port_node, "pcie") {
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port->perst_gpio = devm_fwnode_gpiod_get(dev,
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of_fwnode_handle(pcie_port_node),
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"reset", GPIOD_OUT_HIGH,
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NULL);
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if (IS_ERR(port->perst_gpio)) {
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if (PTR_ERR(port->perst_gpio) == -ENOENT) {
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port->perst_gpio = NULL;
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return 0;
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}
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return dev_err_probe(dev, PTR_ERR(port->perst_gpio),
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"Failed to request reset GPIO\n");
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}
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return 0;
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}
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return 0;
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}
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/**
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* xilinx_cpm_pcie_parse_dt - Parse Device tree
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* @port: PCIe port information
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@ -525,6 +587,19 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
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struct device *dev = port->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *res;
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int ret;
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/* CPM5NC does not support PERST# handling yet */
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if (port->variant->version != CPM5NC_HOST) {
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port->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
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if (IS_ERR(port->rstc))
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return dev_err_probe(dev, PTR_ERR(port->rstc),
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"Failed to request reset\n");
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ret = xilinx_cpm_pcie_parse_port(port);
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if (ret)
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return ret;
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}
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port->cpm_base = devm_platform_ioremap_resource_byname(pdev,
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"cpm_slcr");
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@ -40,6 +40,15 @@ struct pcie_tlp_log;
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*/
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#define PCIE_T_PERST_CLK_US 100
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/*
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* PERST# active time.
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*
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* See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
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* Card Electromechanical Specification, Revision 6.0, Section 2.11.2, Symbol
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* "T_PERST".
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*/
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#define PCIE_T_PERST_US 100
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/*
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* PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
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* Recommends 1ms to 10ms timeout to check L2 ready.
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