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drm/amd/display: rework macros for DWB register access

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[Why]
A hack was used to access DWB register due to difference in the register
naming convention which was not compatible with existing SR/SRI* macros.
The additional macro needed were added to dwb ip specific header file
(dcnxx_dwb.h) instead of soc resource file (dcnxx_resource.c). Due to
this pattern, BASE macro had to be redefined in dcnxx_dwb.h, which in
turn needed us to undefine them in the resource file.

[How]
Add a separate macro for DWB access to the resource files that need it
instead of defining them in DWB ip header file. This will enable us to
reuse the BASE macro defined in the resource file.

Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai 2022-05-06 11:04:15 -04:00 committed by Alex Deucher
parent bcdc915863
commit 158858bf1a
17 changed files with 207 additions and 250 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

363
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
View File

@ -27,204 +27,177 @@
#define TO_DCN20_DWBC(dwbc_base) \
container_of(dwbc_base, struct dcn20_dwbc, base)
/* DCN */
#define BASE_INNER(seg) \
DCE_BASE__INST0_SEG ## seg
#define BASE(seg) \
BASE_INNER(seg)
#define SR(reg_name)\
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
#define SRI(reg_name, block, id)\
.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name
#define SRI2(reg_name, block, id)\
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
#define SRII(reg_name, block, id)\
.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name
#define SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define DWBC_COMMON_REG_LIST_DCN2_0(inst) \
SRI2(WB_ENABLE, CNV, inst),\
SRI2(WB_EC_CONFIG, CNV, inst),\
SRI2(CNV_MODE, CNV, inst),\
SRI2(CNV_WINDOW_START, CNV, inst),\
SRI2(CNV_WINDOW_SIZE, CNV, inst),\
SRI2(CNV_UPDATE, CNV, inst),\
SRI2(CNV_SOURCE_SIZE, CNV, inst),\
SRI2(CNV_TEST_CNTL, CNV, inst),\
SRI2(CNV_TEST_CRC_RED, CNV, inst),\
SRI2(CNV_TEST_CRC_GREEN, CNV, inst),\
SRI2(CNV_TEST_CRC_BLUE, CNV, inst),\
SRI2(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\
SRI2(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\
SRI2(WBSCL_MODE, WBSCL, inst),\
SRI2(WBSCL_TAP_CONTROL, WBSCL, inst),\
SRI2(WBSCL_DEST_SIZE, WBSCL, inst),\
SRI2(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\
SRI2(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\
SRI2(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\
SRI2(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\
SRI2(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\
SRI2(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\
SRI2(WBSCL_ROUND_OFFSET, WBSCL, inst),\
SRI2(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\
SRI2(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\
SRI2(WBSCL_TEST_CNTL, WBSCL, inst),\
SRI2(WBSCL_TEST_CRC_RED, WBSCL, inst),\
SRI2(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\
SRI2(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\
SRI2(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\
SRI2(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\
SRI2(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\
SRI2(WBSCL_CLAMP_CBCR, WBSCL, inst),\
SRI2(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\
SRI2(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\
SRI2(WBSCL_DEBUG, WBSCL, inst),\
SRI2(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\
SRI2(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\
SRI2(WB_DEBUG_CTRL, CNV, inst),\
SRI2(WB_DBG_MODE, CNV, inst),\
SRI2(WB_HW_DEBUG, CNV, inst),\
SRI2(CNV_TEST_DEBUG_INDEX, CNV, inst),\
SRI2(CNV_TEST_DEBUG_DATA, CNV, inst),\
SRI2(WB_SOFT_RESET, CNV, inst),\
SRI2(WB_WARM_UP_MODE_CTL1, CNV, inst),\
SRI2(WB_WARM_UP_MODE_CTL2, CNV, inst)
SRI2_DWB(WB_ENABLE, CNV, inst),\
SRI2_DWB(WB_EC_CONFIG, CNV, inst),\
SRI2_DWB(CNV_MODE, CNV, inst),\
SRI2_DWB(CNV_WINDOW_START, CNV, inst),\
SRI2_DWB(CNV_WINDOW_SIZE, CNV, inst),\
SRI2_DWB(CNV_UPDATE, CNV, inst),\
SRI2_DWB(CNV_SOURCE_SIZE, CNV, inst),\
SRI2_DWB(CNV_TEST_CNTL, CNV, inst),\
SRI2_DWB(CNV_TEST_CRC_RED, CNV, inst),\
SRI2_DWB(CNV_TEST_CRC_GREEN, CNV, inst),\
SRI2_DWB(CNV_TEST_CRC_BLUE, CNV, inst),\
SRI2_DWB(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\
SRI2_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\
SRI2_DWB(WBSCL_MODE, WBSCL, inst),\
SRI2_DWB(WBSCL_TAP_CONTROL, WBSCL, inst),\
SRI2_DWB(WBSCL_DEST_SIZE, WBSCL, inst),\
SRI2_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\
SRI2_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\
SRI2_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\
SRI2_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\
SRI2_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\
SRI2_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\
SRI2_DWB(WBSCL_ROUND_OFFSET, WBSCL, inst),\
SRI2_DWB(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\
SRI2_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\
SRI2_DWB(WBSCL_TEST_CNTL, WBSCL, inst),\
SRI2_DWB(WBSCL_TEST_CRC_RED, WBSCL, inst),\
SRI2_DWB(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\
SRI2_DWB(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\
SRI2_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\
SRI2_DWB(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\
SRI2_DWB(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\
SRI2_DWB(WBSCL_CLAMP_CBCR, WBSCL, inst),\
SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\
SRI2_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\
SRI2_DWB(WBSCL_DEBUG, WBSCL, inst),\
SRI2_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\
SRI2_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\
SRI2_DWB(WB_DEBUG_CTRL, CNV, inst),\
SRI2_DWB(WB_DBG_MODE, CNV, inst),\
SRI2_DWB(WB_HW_DEBUG, CNV, inst),\
SRI2_DWB(CNV_TEST_DEBUG_INDEX, CNV, inst),\
SRI2_DWB(CNV_TEST_DEBUG_DATA, CNV, inst),\
SRI2_DWB(WB_SOFT_RESET, CNV, inst),\
SRI2_DWB(WB_WARM_UP_MODE_CTL1, CNV, inst),\
SRI2_DWB(WB_WARM_UP_MODE_CTL2, CNV, inst)
#define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
SF(WB_ENABLE, WB_ENABLE, mask_sh),\
SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\
SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\
SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\
SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\
SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\
SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\
SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\
SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\
SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\
SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\
SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\
SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\
SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\
SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\
SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\
SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\
SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\
SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\
SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\
SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\
SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\
SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\
SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\
SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\
SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\
SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\
SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\
SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\
SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\
SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\
SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\
SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\
SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\
SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\
SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\
SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\
SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\
SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\
SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\
SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\
SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\
SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\
SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\
SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\
SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\
SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\
SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\
SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\
SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\
SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\
SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\
SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\
SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\
SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\
SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\
SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\
SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\
SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\
SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\
SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\
SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\
SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\
SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\
SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\
SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\
SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\
SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\
SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\
SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\
SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\
SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\
SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\
SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\
SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\
SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\
SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\
SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\
SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\
SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\
SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\
SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\
SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\
SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\
SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\
SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\
SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\
SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\
SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\
SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\
SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\
SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\
SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\
SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\
SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\
SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh)
SF_DWB(WB_ENABLE, WB_ENABLE, mask_sh),\
SF_DWB(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
SF_DWB(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
SF_DWB(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
SF_DWB(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
SF_DWB(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
SF_DWB(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
SF_DWB(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\
SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\
SF_DWB(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\
SF_DWB(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\
SF_DWB(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\
SF_DWB(CNV_MODE, CNV_OUT_BPC, mask_sh),\
SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\
SF_DWB(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
SF_DWB(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
SF_DWB(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
SF_DWB(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
SF_DWB(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
SF_DWB(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
SF_DWB(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
SF_DWB(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\
SF_DWB(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
SF_DWB(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\
SF_DWB(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\
SF_DWB(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\
SF_DWB(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\
SF_DWB(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\
SF_DWB(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\
SF_DWB(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\
SF_DWB(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\
SF_DWB(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\
SF_DWB(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\
SF_DWB(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\
SF_DWB(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\
SF_DWB(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\
SF_DWB(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\
SF_DWB(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\
SF_DWB(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\
SF_DWB(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\
SF_DWB(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\
SF_DWB(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\
SF_DWB(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\
SF_DWB(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\
SF_DWB(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\
SF_DWB(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
SF_DWB(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\
SF_DWB(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\
SF_DWB(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
SF_DWB(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
SF_DWB(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\
SF_DWB(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\
SF_DWB(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
SF_DWB(WBSCL_MODE, WBSCL_MODE, mask_sh),\
SF_DWB(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\
SF_DWB(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\
SF_DWB(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\
SF_DWB(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\
SF_DWB(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\
SF_DWB(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\
SF_DWB(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\
SF_DWB(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\
SF_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\
SF_DWB(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\
SF_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\
SF_DWB(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\
SF_DWB(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\
SF_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\
SF_DWB(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\
SF_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\
SF_DWB(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\
SF_DWB(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\
SF_DWB(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\
SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\
SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\
SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\
SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\
SF_DWB(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\
SF_DWB(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\
SF_DWB(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\
SF_DWB(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\
SF_DWB(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\
SF_DWB(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\
SF_DWB(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\
SF_DWB(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\
SF_DWB(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\
SF_DWB(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\
SF_DWB(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\
SF_DWB(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\
SF_DWB(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\
SF_DWB(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\
SF_DWB(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\
SF_DWB(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\
SF_DWB(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\
SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\
SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\
SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\
SF_DWB(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\
SF_DWB(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\
SF_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\
SF_DWB(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\
SF_DWB(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\
SF_DWB(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\
SF_DWB(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\
SF_DWB(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\
SF_DWB(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\
SF_DWB(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\
SF_DWB(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh)
#define DWBC_REG_FIELD_LIST_DCN2_0(type) \
type WB_ENABLE;\

7
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h
View File

@ -29,13 +29,6 @@
#define TO_DCN20_MMHUBBUB(mcif_wb_base) \
container_of(mcif_wb_base, struct dcn20_mmhubbub, base)
/* DCN */
#define BASE_INNER(seg) \
DCE_BASE__INST0_SEG ## seg
#define BASE(seg) \
BASE_INNER(seg)
#define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \
SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\

11
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
View File

@ -124,8 +124,6 @@ enum dcn20_clk_src_array_id {
* macros to expend register list macro defined in HW object header file */
/* DCN */
/* TODO awful hack. fixup dcn20_dwb.h */
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
@ -138,6 +136,15 @@ enum dcn20_clk_src_array_id {
.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name
#define SRI2_DWB(reg_name, block, id)\
.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
mm ## reg_name
#define SF_DWB(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define SRIR(var_name, reg_name, block, id)\
.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name

6
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
View File

@ -28,12 +28,6 @@
#include "vmid.h"
#define BASE_INNER(seg) \
DCE_BASE__INST0_SEG ## seg
#define BASE(seg) \
BASE_INNER(seg)
#define DCN20_VMID_REG_LIST(id)\
SRI(CNTL, DCN_VM_CONTEXT, id),\
SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\

2
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
View File

@ -94,8 +94,6 @@
* macros to expend register list macro defined in HW object header file */
/* DCN */
/* TODO awful hack. fixup dcn20_dwb.h */
#undef BASE_INNER
#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)

15
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h
View File

@ -27,21 +27,6 @@
#define TO_DCN30_DWBC(dwbc_base) \
container_of(dwbc_base, struct dcn30_dwbc, base)
/* DCN */
#define BASE_INNER(seg) \
DCE_BASE__INST0_SEG ## seg
#define BASE(seg) \
BASE_INNER(seg)
#define SF_DWB(reg_name, block, id, field_name, post_fix)\
.field_name = block ## id ## _ ## reg_name ## __ ## field_name ## post_fix
/* set field name */
#define SF_DWB2(reg_name, block, id, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define DWBC_COMMON_REG_LIST_DCN30(inst) \
SR(DWB_ENABLE_CLK_CTRL),\
SR(DWB_MEM_PWR_CTRL),\

7
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.h
View File

@ -31,13 +31,6 @@
#define TO_DCN30_MMHUBBUB(mcif_wb_base) \
container_of(mcif_wb_base, struct dcn30_mmhubbub, base)
/* DCN */
#define BASE_INNER(seg) \
DCE_BASE__INST0_SEG ## seg
#define BASE(seg) \
BASE_INNER(seg)
#define MCIF_WB_COMMON_REG_LIST_DCN3_0(inst) \
SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\

5
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
View File

@ -108,8 +108,6 @@ enum dcn30_clk_src_array_id {
*/
/* DCN */
/* TODO awful hack. fixup dcn20_dwb.h */
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
@ -142,6 +140,9 @@ enum dcn30_clk_src_array_id {
.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## temp_name
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define DCCG_SRII(reg_name, block, id)\
.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name

5
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
View File

@ -107,8 +107,6 @@ enum dcn301_clk_src_array_id {
*/
/* DCN */
/* TODO awful hack. fixup dcn20_dwb.h */
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
@ -146,6 +144,9 @@ enum dcn301_clk_src_array_id {
.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## temp_name
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define DCCG_SRII(reg_name, block, id)\
.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name

4
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
View File

@ -183,7 +183,6 @@ static const struct dc_plane_cap plane_cap = {
mm ## reg_name
/* DCN */
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
@ -216,6 +215,9 @@ static const struct dc_plane_cap plane_cap = {
.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## temp_name
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define SRII_MPC_RMU(reg_name, block, id)\
.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name

4
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
View File

@ -162,7 +162,6 @@ static const struct dc_plane_cap plane_cap = {
mm ## reg_name
/* DCN */
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
@ -195,6 +194,9 @@ static const struct dc_plane_cap plane_cap = {
.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## temp_name
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define SRII_MPC_RMU(reg_name, block, id)\
.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
mm ## block ## id ## _ ## reg_name

5
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
View File

@ -119,8 +119,6 @@ enum dcn31_clk_src_array_id {
*/
/* DCN */
/* TODO awful hack. fixup dcn20_dwb.h */
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
@ -153,6 +151,9 @@ enum dcn31_clk_src_array_id {
.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## temp_name
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define DCCG_SRII(reg_name, block, id)\
.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name

3
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
View File

@ -184,6 +184,9 @@ enum dcn31_clk_src_array_id {
.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## temp_name
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define DCCG_SRII(reg_name, block, id)\
.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name

5
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
View File

@ -151,8 +151,6 @@ enum dcn31_clk_src_array_id {
*/
/* DCN */
/* TODO awful hack. fixup dcn20_dwb.h */
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
@ -185,6 +183,9 @@ enum dcn31_clk_src_array_id {
.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## temp_name
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define DCCG_SRII(reg_name, block, id)\
.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name

5
drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
View File

@ -142,8 +142,6 @@ enum dcn31_clk_src_array_id {
*/
/* DCN */
/* TODO awful hack. fixup dcn20_dwb.h */
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
@ -176,6 +174,9 @@ enum dcn31_clk_src_array_id {
.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## temp_name
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define DCCG_SRII(reg_name, block, id)\
.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name

5
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
View File

@ -106,8 +106,6 @@ enum dcn32_clk_src_array_id {
*/
/* DCN */
/* TODO awful hack. fixup dcn20_dwb.h */
#undef BASE_INNER
#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
#define BASE(seg) BASE_INNER(seg)
@ -167,6 +165,9 @@ enum dcn32_clk_src_array_id {
REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## temp_name
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define DCCG_SRII(reg_name, block, id)\
REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name

5
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
View File

@ -109,8 +109,6 @@ enum dcn321_clk_src_array_id {
*/
/* DCN */
/* TODO awful hack. fixup dcn20_dwb.h */
#undef BASE_INNER
#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
#define BASE(seg) BASE_INNER(seg)
@ -174,6 +172,9 @@ enum dcn321_clk_src_array_id {
REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name
#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
.field_name = reg_name ## __ ## field_name ## post_fix
#define VUPDATE_SRII(reg_name, block, id)\
REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
reg ## reg_name ## _ ## block ## id