mirror of
https://github.com/torvalds/linux.git
synced 2026-09-24 06:24:02 +02:00
Merge branch 'pci/controller/dwc-qcom'
- Add DT binding and driver support for Hawi SoC (Matthew Leung) - Skip PERST# GPIOs provided by downstream PCIe devices, which should be handled by drivers of those devices (Manivannan Sadhasivam) - Stop advertising Attention Button Present (no Qcom SoCs support Attention Buttons) so pciehp can use Presence Detect Changed events (Qiang Yu) * pci/controller/dwc-qcom: PCI: qcom: Clear Attention Button Present in Slot Capabilities PCI: qcom: Rename qcom_pcie_set_slot_nccs() to qcom_pcie_set_slot_cap() PCI: qcom: Skip PERST# GPIOs provided by downstream PCIe devices PCI: qcom: Add support for Hawi dt-bindings: PCI: qcom: Document Hawi and Maili PCIe Controllers
This commit is contained in:
Bjorn Helgaas
commit
1579362594
201
Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
Normal file
201
Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
Normal file
|
|
@ -0,0 +1,201 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Hawi PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
description:
|
||||
Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on
|
||||
the Synopsys DesignWare PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,hawi-pcie
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,maili-pcie
|
||||
- const: qcom,hawi-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Qualcomm specific registers
|
||||
- description: DesignWare PCIe registers
|
||||
- description: External local bus interface registers
|
||||
- description: ATU address space
|
||||
- description: PCIe configuration space
|
||||
- description: MHI registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: parf
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: atu
|
||||
- const: config
|
||||
- const: mhi
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: PCIe Auxiliary clock
|
||||
- description: PCIe Configuration clock
|
||||
- description: PCIe Master AXI clock
|
||||
- description: PCIe Slave AXI clock
|
||||
- description: PCIe Slave Q2A AXI clock
|
||||
- description: PCIe Aggre NoC AXI clock
|
||||
- description: PCIe Config NoC AXI clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux
|
||||
- const: cfg
|
||||
- const: bus_master
|
||||
- const: bus_slave
|
||||
- const: slave_q2a
|
||||
- const: noc_aggr
|
||||
- const: cnoc_sf_axi
|
||||
|
||||
interrupts:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: PCIe core reset
|
||||
- description: PCIe link down reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
- const: link_down
|
||||
|
||||
required:
|
||||
- power-domains
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c00000 {
|
||||
compatible = "qcom,hawi-pcie";
|
||||
reg = <0 0x01c00000 0 0x3000>,
|
||||
<0 0x40000000 0 0xf1d>,
|
||||
<0 0x40000f20 0 0xa8>,
|
||||
<0 0x40001000 0 0x1000>,
|
||||
<0 0x40100000 0 0x100000>,
|
||||
<0 0x01c03000 0 0x1000>;
|
||||
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
num-lanes = <2>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc_pcie_0_aux_clk>,
|
||||
<&gcc_pcie_0_cfg_ahb_clk>,
|
||||
<&gcc_pcie_0_mstr_axi_clk>,
|
||||
<&gcc_pcie_0_slv_axi_clk>,
|
||||
<&gcc_pcie_0_slv_q2a_axi_clk>,
|
||||
<&gcc_aggre_noc_pcie_axi_clk>,
|
||||
<&gcc_cnoc_pcie_sf_axi_clk>;
|
||||
clock-names = "aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"noc_aggr",
|
||||
"cnoc_sf_axi";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7", "global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
interconnects = <&pcie_anoc_master_pcie_0 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&cnoc_main_slave_pcie_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1000 0x1>,
|
||||
<0x100 &apps_smmu 0x1001 0x1>;
|
||||
|
||||
pinctrl-0 = <&pcie0_default_state>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-domains = <&gcc_pcie_0_phy_gdsc>;
|
||||
|
||||
resets = <&gcc_pcie_0_bcr>,
|
||||
<&gcc_pcie_0_link_down_bcr>;
|
||||
reset-names = "pci", "link_down";
|
||||
|
||||
msi-map = <0x0 &gic_its 0x1000 0x1>,
|
||||
<0x100 &gic_its 0x1001 0x1>;
|
||||
msi-map-mask = <0xff00>;
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -21012,6 +21012,7 @@ M: Manivannan Sadhasivam <mani@kernel.org>
|
|||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pci/qcom,*.yaml
|
||||
F: drivers/pci/controller/dwc/pcie-qcom-common.c
|
||||
F: drivers/pci/controller/dwc/pcie-qcom.c
|
||||
|
||||
|
|
|
|||
|
|
@ -376,7 +376,7 @@ static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci)
|
|||
dw_pcie_dbi_ro_wr_dis(pci);
|
||||
}
|
||||
|
||||
static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci)
|
||||
static void qcom_pcie_set_slot_cap(struct dw_pcie *pci)
|
||||
{
|
||||
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
|
||||
u32 val;
|
||||
|
|
@ -390,6 +390,12 @@ static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci)
|
|||
*/
|
||||
val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP);
|
||||
val |= PCI_EXP_SLTCAP_NCCS;
|
||||
|
||||
/*
|
||||
* Qcom PCIe Root Ports do not support Attention Button, so clear
|
||||
* Attention Button Present in Slot Capabilities.
|
||||
*/
|
||||
val &= ~PCI_EXP_SLTCAP_ABP;
|
||||
writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
|
||||
|
||||
dw_pcie_dbi_ro_wr_dis(pci);
|
||||
|
|
@ -598,7 +604,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
|
|||
writel(CFG_BRIDGE_SB_INIT,
|
||||
pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1);
|
||||
|
||||
qcom_pcie_set_slot_nccs(pcie->pci);
|
||||
qcom_pcie_set_slot_cap(pcie->pci);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -678,7 +684,7 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
|
|||
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
|
||||
}
|
||||
|
||||
qcom_pcie_set_slot_nccs(pcie->pci);
|
||||
qcom_pcie_set_slot_cap(pcie->pci);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -777,7 +783,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
|
|||
val |= EN;
|
||||
writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
|
||||
|
||||
qcom_pcie_set_slot_nccs(pcie->pci);
|
||||
qcom_pcie_set_slot_cap(pcie->pci);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1096,7 +1102,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
|
|||
writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
|
||||
pcie->parf + PARF_NO_SNOOP_OVERRIDE);
|
||||
|
||||
qcom_pcie_set_slot_nccs(pcie->pci);
|
||||
qcom_pcie_set_slot_cap(pcie->pci);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1930,6 +1936,23 @@ static const struct pci_ecam_ops pci_qcom_ecam_ops = {
|
|||
}
|
||||
};
|
||||
|
||||
/* Check if @node is a child of @dev in DT */
|
||||
static bool qcom_pcie_is_child_node(struct device *dev,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct device_node *parent;
|
||||
|
||||
for (parent = of_get_parent(node); parent;
|
||||
parent = of_get_next_parent(parent)) {
|
||||
if (parent == dev->of_node) {
|
||||
of_node_put(parent);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Parse PERST# from all nodes in depth first manner starting from @np */
|
||||
static int qcom_pcie_parse_perst(struct qcom_pcie *pcie,
|
||||
struct qcom_pcie_port *port,
|
||||
|
|
@ -1937,6 +1960,7 @@ static int qcom_pcie_parse_perst(struct qcom_pcie *pcie,
|
|||
{
|
||||
struct device *dev = pcie->pci->dev;
|
||||
struct qcom_pcie_perst *perst;
|
||||
struct device_node *gpio_np;
|
||||
struct gpio_desc *reset;
|
||||
int ret;
|
||||
|
||||
|
|
@ -1950,6 +1974,25 @@ static int qcom_pcie_parse_perst(struct qcom_pcie *pcie,
|
|||
if (!of_find_property(np, "reset-gpios", NULL))
|
||||
goto parse_child_node;
|
||||
|
||||
/*
|
||||
* Skip GPIOs provided by a PCIe device which is a child of the Root
|
||||
* Complex (e.g., a PCIe switch with GPIO controller capability). Such
|
||||
* controllers won't be available at RC probe time and their PERST#
|
||||
* should be controlled by the respective PCI client driver
|
||||
* implementation.
|
||||
*/
|
||||
gpio_np = of_parse_phandle(np, "reset-gpios", 0);
|
||||
if (!gpio_np) {
|
||||
dev_err(dev, "Failed to parse GPIO provider\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (qcom_pcie_is_child_node(dev, gpio_np)) {
|
||||
of_node_put(gpio_np);
|
||||
goto parse_child_node;
|
||||
}
|
||||
of_node_put(gpio_np);
|
||||
|
||||
reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(np), "reset",
|
||||
GPIOD_OUT_HIGH, "PERST#");
|
||||
if (IS_ERR(reset)) {
|
||||
|
|
@ -2420,6 +2463,7 @@ static int qcom_pcie_resume_noirq(struct device *dev)
|
|||
}
|
||||
|
||||
static const struct of_device_id qcom_pcie_match[] = {
|
||||
{ .compatible = "qcom,hawi-pcie", .data = &cfg_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
|
||||
{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
|
||||
{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user