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drm/i915: pass dev_priv explicitly to PRIMCNSTALPHA

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Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PRIMCNSTALPHA register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/783477b86f4d53849775cbf690bb8b9042792a66.1716469091.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2024-05-23 15:59:43 +03:00
parent 491097568a
commit 1572fc3162
2 changed files with 4 additions and 3 deletions
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3
drivers/gpu/drm/i915/display/i9xx_plane.c
View File

@ -478,7 +478,8 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane),
PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
intel_de_write_fw(dev_priv,
PRIMCNSTALPHA(dev_priv, i9xx_plane), 0);
}
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

4
drivers/gpu/drm/i915/display/i9xx_plane_regs.h
View File

@ -101,8 +101,8 @@
#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
#define _PRIMCNSTALPHA_A 0x60a10
#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
#define _PRIMCNSTALPHA_A 0x60a10
#define PRIMCNSTALPHA(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))