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arm64: dts: socfpga: stratix10: add L2 cache info

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This removes cacheinfo warnings at boot, e.g.:
cacheinfo: Unable to detect cache hierarchy for CPU 0

Signed-off-by: Beniamin Sandu <beniaminsandu@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Beniamin Sandu 2024-05-15 19:12:49 +01:00 committed by Dinh Nguyen
parent 32cdf4c75f
commit 1536dc8edc
1 changed files with 10 additions and 0 deletions
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10
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
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@ -34,6 +34,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&l2_shared>;
reg = <0x0>;
};
@ -41,6 +42,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&l2_shared>;
reg = <0x1>;
};
@ -48,6 +50,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&l2_shared>;
reg = <0x2>;
};
@ -55,8 +58,15 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
next-level-cache = <&l2_shared>;
reg = <0x3>;
};
l2_shared: cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
firmware {