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wifi: iwlwifi: Add an helper function for polling bits
Add iwl_poll_bits helper to simplify calls to iwl_poll_bit for the case when the bits and mask arguments are equal. Signed-off-by: Rotem Kerem <rotem.kerem@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250709081300.6bbc4bccc597.Ic7a10a7f8a9a32a9a9feecaf6e3a48fa37479f2d@changeid
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@ -676,10 +676,9 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
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CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM);
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/* See if we got it */
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ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,
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CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,
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IWL_EEPROM_SEM_TIMEOUT);
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ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM,
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IWL_EEPROM_SEM_TIMEOUT);
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if (ret >= 0) {
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IWL_DEBUG_EEPROM(trans->dev,
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"Acquired semaphore after %d tries.\n",
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@ -797,10 +796,9 @@ static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
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iwl_write32(trans, CSR_EEPROM_REG,
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CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
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ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
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CSR_EEPROM_REG_READ_VALID_MSK,
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CSR_EEPROM_REG_READ_VALID_MSK,
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IWL_EEPROM_ACCESS_TIMEOUT);
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ret = iwl_poll_bits(trans, CSR_EEPROM_REG,
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CSR_EEPROM_REG_READ_VALID_MSK,
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IWL_EEPROM_ACCESS_TIMEOUT);
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if (ret < 0) {
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IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
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return ret;
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@ -993,10 +991,9 @@ int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size)
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iwl_write32(trans, CSR_EEPROM_REG,
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CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
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ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
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CSR_EEPROM_REG_READ_VALID_MSK,
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CSR_EEPROM_REG_READ_VALID_MSK,
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IWL_EEPROM_ACCESS_TIMEOUT);
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ret = iwl_poll_bits(trans, CSR_EEPROM_REG,
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CSR_EEPROM_REG_READ_VALID_MSK,
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IWL_EEPROM_ACCESS_TIMEOUT);
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if (ret < 0) {
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IWL_ERR(trans,
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"Time out reading EEPROM[%d]\n", addr);
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@ -47,8 +47,8 @@ IWL_EXPORT_SYMBOL(iwl_read32);
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#define IWL_POLL_INTERVAL 10 /* microseconds */
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int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout)
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int iwl_poll_bits_mask(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout)
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{
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int t = 0;
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@ -61,7 +61,7 @@ int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
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return -ETIMEDOUT;
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}
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IWL_EXPORT_SYMBOL(iwl_poll_bit);
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IWL_EXPORT_SYMBOL(iwl_poll_bits_mask);
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u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
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{
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@ -477,7 +477,7 @@ int iwl_finish_nic_init(struct iwl_trans *trans)
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* device-internal resources is supported, e.g. iwl_write_prph()
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* and accesses to uCode SRAM.
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*/
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err = iwl_poll_bit(trans, CSR_GP_CNTRL, poll_ready, poll_ready, 25000);
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err = iwl_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000);
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if (err < 0) {
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IWL_DEBUG_INFO(trans, "Failed to wake NIC\n");
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@ -23,8 +23,13 @@ static inline void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
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iwl_trans_set_bits_mask(trans, reg, mask, 0);
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}
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int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout);
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int iwl_poll_bits_mask(struct iwl_trans *trans, u32 addr,
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u32 bits, u32 mask, int timeout);
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static inline int iwl_poll_bits(struct iwl_trans *trans, u32 addr, u32 bits,
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int timeout)
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{
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return iwl_poll_bits_mask(trans, addr, bits, bits, timeout);
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}
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int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
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int timeout);
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@ -380,17 +380,15 @@ void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
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iwl_set_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
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CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
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100);
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ret = iwl_poll_bits(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
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100);
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usleep_range(10000, 20000);
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} else {
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iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
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ret = iwl_poll_bit(trans, CSR_RESET,
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CSR_RESET_REG_FLAG_MASTER_DISABLED,
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CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
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ret = iwl_poll_bits(trans, CSR_RESET,
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CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
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}
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if (ret < 0)
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@ -492,10 +490,9 @@ static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
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CSR_HW_IF_CONFIG_REG_PCI_OWN_SET);
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/* See if we got it */
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ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
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CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
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HW_READY_TIMEOUT);
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ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_PCI_OWN_SET,
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HW_READY_TIMEOUT);
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if (ret >= 0)
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iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
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@ -2354,7 +2351,7 @@ bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent)
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* 5000 series and later (including 1000 series) have non-volatile SRAM,
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* and do not save/restore SRAM when power cycling.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000);
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ret = iwl_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000);
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if (unlikely(ret < 0)) {
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u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
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@ -590,7 +590,7 @@ static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
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}
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/* Wait for DMA channels to be idle */
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ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
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ret = iwl_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000);
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if (ret < 0)
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IWL_ERR(trans,
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"Failing on timeout while stopping DMA channel %d [0x%08x]\n",
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