Renesas DTS updates for v6.15 (take two)

- Add GPU support for the RZ/V2H(P) SoC and the RZ/V2H EVK board.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZ8sSMQAKCRCKwlD9ZEnx
 cDdSAQCkYv8LTN4DrlZjOxaUjFabUv4i10e6hA8IKmud9EKwggD/dqAShG/m0b3v
 kKvVfxKDWnd7jTyH6vpCeAiw5HcKuQY=
 =mfSx
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmfUaGsACgkQYKtH/8kJ
 UichTg//RiZCAdT6HWZF4lbw5OH+CaDtG5DGlgvZOmIHQa9UYPJRnk4s0sp6PZ7t
 b15ohnpWssBcSoJVH5dWeplHY2Y7H59shV+8jf+sf8OCOiGsAPfjZmkhpZyb+sci
 jNCfT0QcrDEnEMa6jET9oLfWmj3g8h0lK03SixkH4vCCLVqKIlo2gfbW9IxwPyeY
 SaL/bOoY/ycH3+01klRAPCrINiUqC2JRHhkUnoa9lwKH4AZRYmktvKayZNrn+lTE
 kldcDrEl6RghLPaQBPHpmgVv1TuwYqvlOT18TUsjHZjBdpckbWuiOyItmDFPK+G6
 k57vVDmAqWmY+MmWq90zC74JZryx6Gj65bZOHjvAAsDP7XWPVvmmY00pKZf044nr
 SIUUxw6RdCvE02dGovLEzh8cf1Cel5rYwZaoZ4G754CEzI9M/TtbJODCCWxNl2IX
 5hg7s/qB6qEohdEcBIHyCzel+ZMBMznha1Y5mSzYa17g/5Gxg3iAoGWFgGWJhQcq
 npGf28xb0+crUHb98uCgPpSCc+ba/iMQZ+zIUrXUL4GYjFDsUPWaEKYfYv35bPHS
 p8xrZUw8dOLGwu2h0WIyA822ytzkfh2wigA2r63cDi+mu0+S8HvmxM40ujtZpzTH
 p1Z1oB/OcpRXzz4Xa1cvsvfhx/ht80iXXoyqHFpM1ounWC4gI0w=
 =3lmS
 -----END PGP SIGNATURE-----

Merge tag 'renesas-dts-for-v6.15-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.15 (take two)

  - Add GPU support for the RZ/V2H(P) SoC and the RZ/V2H EVK board.

* tag 'renesas-dts-for-v6.15-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable Mali-G31
  arm64: dts: renesas: r9a09g057: Add Mali-G31 GPU node

Link: https://lore.kernel.org/r/cover.1741362039.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-03-14 18:33:27 +01:00
commit 14833afa5b
2 changed files with 66 additions and 0 deletions

View File

@ -105,6 +105,35 @@ L3_CA55: cache-controller-0 {
};
};
gpu_opp_table: opp-table-1 {
compatible = "operating-points-v2";
opp-630000000 {
opp-hz = /bits/ 64 <630000000>;
opp-microvolt = <800000>;
};
opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-microvolt = <800000>;
};
opp-157500000 {
opp-hz = /bits/ 64 <157500000>;
opp-microvolt = <800000>;
};
opp-78750000 {
opp-hz = /bits/ 64 <78750000>;
opp-microvolt = <800000>;
};
opp-19687500 {
opp-hz = /bits/ 64 <19687500>;
opp-microvolt = <800000>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
@ -581,6 +610,28 @@ i2c8: i2c@11c01000 {
status = "disabled";
};
gpu: gpu@14850000 {
compatible = "renesas,r9a09g057-mali",
"arm,mali-bifrost";
reg = <0x0 0x14850000 0x0 0x10000>;
interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu", "event";
clocks = <&cpg CPG_MOD 0xf0>,
<&cpg CPG_MOD 0xf1>,
<&cpg CPG_MOD 0xf2>;
clock-names = "gpu", "bus", "bus_ace";
power-domains = <&cpg>;
resets = <&cpg 0xdd>,
<&cpg 0xde>,
<&cpg 0xdf>;
reset-names = "rst", "axi_rst", "ace_rst";
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
};
gic: interrupt-controller@14900000 {
compatible = "arm,gic-v3";
reg = <0x0 0x14900000 0 0x20000>,

View File

@ -43,6 +43,16 @@ memory@240000000 {
reg = <0x2 0x40000000 0x2 0x00000000>;
};
reg_0p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-0.8V";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator1 {
compatible = "regulator-fixed";
@ -68,6 +78,11 @@ &audio_extal_clk {
clock-frequency = <22579200>;
};
&gpu {
status = "okay";
mali-supply = <&reg_0p8v>;
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";