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arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES

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[ Upstream commit 5c6d0b55b4 ]

Rename the external refclk inputs to the SERDES from
dummy_cmn_refclk/dummy_cmn_refclk1 to cmn_refclk/cmn_refclk1
respectively. Also move the external refclk DT nodes outside the
cbass_main DT node. Since in j721e common processor board, only the
cmn_refclk1 is connected to 100MHz clock, fix the clock frequency.

Fixes: afd094ebe6 ("arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603143427.28735-2-kishon@ti.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Kishon Vijay Abraham I 2021-06-03 20:04:24 +05:30 committed by Greg Kroah-Hartman
parent 668ca46870
commit 1479998d80
2 changed files with 34 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
View File

@ -560,6 +560,10 @@ &mcasp10 {
status = "okay"; status = "okay";
}; };
&cmn_refclk1 {
clock-frequency = <100000000>;
};
&serdes0 { &serdes0 {
serdes0_pcie_link: link@0 { serdes0_pcie_link: link@0 {
reg = <0>; reg = <0>;

58
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
View File

@ -8,6 +8,20 @@
#include <dt-bindings/mux/mux.h> #include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/mux/ti-serdes.h>
/ {
cmn_refclk: clock-cmnrefclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
cmn_refclk1: clock-cmnrefclk1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
&cbass_main { &cbass_main {
msmc_ram: sram@70000000 { msmc_ram: sram@70000000 {
compatible = "mmio-sram"; compatible = "mmio-sram";
@ -369,24 +383,12 @@ main_pmx0: pinctrl@11c000 {
pinctrl-single,function-mask = <0xffffffff>; pinctrl-single,function-mask = <0xffffffff>;
}; };
dummy_cmn_refclk: dummy-cmn-refclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
dummy_cmn_refclk1: dummy-cmn-refclk1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
serdes_wiz0: wiz@5000000 { serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g"; compatible = "ti,j721e-wiz-16g";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk"; clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
@ -395,21 +397,21 @@ serdes_wiz0: wiz@5000000 {
ranges = <0x5000000 0x0 0x5000000 0x10000>; ranges = <0x5000000 0x0 0x5000000 0x10000>;
wiz0_pll0_refclk: pll0-refclk { wiz0_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; clocks = <&k3_clks 292 11>, <&cmn_refclk>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz0_pll0_refclk>; assigned-clocks = <&wiz0_pll0_refclk>;
assigned-clock-parents = <&k3_clks 292 11>; assigned-clock-parents = <&k3_clks 292 11>;
}; };
wiz0_pll1_refclk: pll1-refclk { wiz0_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz0_pll1_refclk>; assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&k3_clks 292 0>; assigned-clock-parents = <&k3_clks 292 0>;
}; };
wiz0_refclk_dig: refclk-dig { wiz0_refclk_dig: refclk-dig {
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>; assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&k3_clks 292 11>; assigned-clock-parents = <&k3_clks 292 11>;
@ -443,7 +445,7 @@ serdes_wiz1: wiz@5010000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk"; clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
@ -452,21 +454,21 @@ serdes_wiz1: wiz@5010000 {
ranges = <0x5010000 0x0 0x5010000 0x10000>; ranges = <0x5010000 0x0 0x5010000 0x10000>;
wiz1_pll0_refclk: pll0-refclk { wiz1_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; clocks = <&k3_clks 293 13>, <&cmn_refclk>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz1_pll0_refclk>; assigned-clocks = <&wiz1_pll0_refclk>;
assigned-clock-parents = <&k3_clks 293 13>; assigned-clock-parents = <&k3_clks 293 13>;
}; };
wiz1_pll1_refclk: pll1-refclk { wiz1_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz1_pll1_refclk>; assigned-clocks = <&wiz1_pll1_refclk>;
assigned-clock-parents = <&k3_clks 293 0>; assigned-clock-parents = <&k3_clks 293 0>;
}; };
wiz1_refclk_dig: refclk-dig { wiz1_refclk_dig: refclk-dig {
clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz1_refclk_dig>; assigned-clocks = <&wiz1_refclk_dig>;
assigned-clock-parents = <&k3_clks 293 13>; assigned-clock-parents = <&k3_clks 293 13>;
@ -500,7 +502,7 @@ serdes_wiz2: wiz@5020000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk"; clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
@ -509,21 +511,21 @@ serdes_wiz2: wiz@5020000 {
ranges = <0x5020000 0x0 0x5020000 0x10000>; ranges = <0x5020000 0x0 0x5020000 0x10000>;
wiz2_pll0_refclk: pll0-refclk { wiz2_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; clocks = <&k3_clks 294 11>, <&cmn_refclk>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz2_pll0_refclk>; assigned-clocks = <&wiz2_pll0_refclk>;
assigned-clock-parents = <&k3_clks 294 11>; assigned-clock-parents = <&k3_clks 294 11>;
}; };
wiz2_pll1_refclk: pll1-refclk { wiz2_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz2_pll1_refclk>; assigned-clocks = <&wiz2_pll1_refclk>;
assigned-clock-parents = <&k3_clks 294 0>; assigned-clock-parents = <&k3_clks 294 0>;
}; };
wiz2_refclk_dig: refclk-dig { wiz2_refclk_dig: refclk-dig {
clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz2_refclk_dig>; assigned-clocks = <&wiz2_refclk_dig>;
assigned-clock-parents = <&k3_clks 294 11>; assigned-clock-parents = <&k3_clks 294 11>;
@ -557,7 +559,7 @@ serdes_wiz3: wiz@5030000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk"; clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
@ -566,21 +568,21 @@ serdes_wiz3: wiz@5030000 {
ranges = <0x5030000 0x0 0x5030000 0x10000>; ranges = <0x5030000 0x0 0x5030000 0x10000>;
wiz3_pll0_refclk: pll0-refclk { wiz3_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; clocks = <&k3_clks 295 9>, <&cmn_refclk>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz3_pll0_refclk>; assigned-clocks = <&wiz3_pll0_refclk>;
assigned-clock-parents = <&k3_clks 295 9>; assigned-clock-parents = <&k3_clks 295 9>;
}; };
wiz3_pll1_refclk: pll1-refclk { wiz3_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz3_pll1_refclk>; assigned-clocks = <&wiz3_pll1_refclk>;
assigned-clock-parents = <&k3_clks 295 0>; assigned-clock-parents = <&k3_clks 295 0>;
}; };
wiz3_refclk_dig: refclk-dig { wiz3_refclk_dig: refclk-dig {
clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>; #clock-cells = <0>;
assigned-clocks = <&wiz3_refclk_dig>; assigned-clocks = <&wiz3_refclk_dig>;
assigned-clock-parents = <&k3_clks 295 9>; assigned-clock-parents = <&k3_clks 295 9>;