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Merge branch 'pci/dt-bindings'

Browse Source 
- Add rcar-pci-host missing IOMMU properties (Geert Uytterhoeven)

- Add ti,j721e-pci-host J784S4 Device ID (Siddharth Vadapalli)

- Add ti,j721e-pci-host J722S compatible string (Siddharth Vadapalli)

- Add ti,am65 num-viewport, phys, and phy-name properties (Jan Kiszka)

- Drop cdns,cdns-pcie-host redundant msi-parent and pci-bus.yaml (Krzysztof
  Kozlowski)

- Add mediatek,mt7621 missing reg property for child Root Ports (Krzysztof
  Kozlowski)

- Switch bindings from pci-bus.yaml to pci-host-bridge.yaml (Krzysztof
  Kozlowski)

- Convert fsl,layerscape host and endpoint bindings to YAML (Frank Li)

- Add rcar-gen4-pci-host R-Car V4H (R8A779G0) compatible strings for both
  host and endpoint mode (Yoshihiro Shimoda)

- Add rockchip,rk3399-pcie maxItems for ep-gpios (Krzysztof Kozlowski)

* pci/dt-bindings:
  dt-bindings: PCI: rockchip,rk3399-pcie: Add missing maxItems to ep-gpios
  dt-bindings: PCI: rcar-gen4-pci-ep: Add R-Car V4H compatible
  dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car V4H compatible
  dt-bindings: PCI: layerscape-pci: Convert to YAML format
  dt-bindings: PCI: mediatek,mt7621-pcie: Switch from deprecated pci-bus.yaml
  dt-bindings: PCI: host-bridges: Switch from deprecated pci-bus.yaml
  dt-bindings: PCI: mediatek,mt7621: Add missing child node reg
  dt-bindings: PCI: cdns,cdns-pcie-host: Drop redundant msi-parent and pci-bus.yaml
  dt-bindings: PCI: ti,am65: Fix remaining binding warnings
  dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC
  dt-bindings: PCI: rcar-pci-host: Add missing IOMMU properties
  dt-bindings: PCI: ti,j721e-pci-host: Add device-id for TI's J784S4 SoC
This commit is contained in:
Bjorn Helgaas 2024-05-16 18:14:12 -05:00
commit 14680b2527
32 changed files with 333 additions and 110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml
View File

@ -13,7 +13,7 @@ description:
Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- $ref: /schemas/pci/snps,dw-pcie-common.yaml#
# We need a select here so we don't match all nodes with 'snps,dw-pcie'

2
Documentation/devicetree/bindings/pci/apple,pcie.yaml
View File

@ -85,7 +85,7 @@ required:
unevaluatedProperties: false
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
- if:
properties:

2
Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml
View File

@ -11,7 +11,7 @@ maintainers:
- Scott Branden <scott.branden@broadcom.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:

2
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
View File

@ -108,7 +108,7 @@ required:
- msi-controller
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
- if:
properties:

3
Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
View File

@ -10,7 +10,6 @@ maintainers:
- Tom Joseph <tjoseph@cadence.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: cdns-pcie-host.yaml#
properties:
@ -25,8 +24,6 @@ properties:
- const: reg
- const: cfg
msi-parent: true
required:
- reg
- reg-names

2
Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
View File

@ -10,7 +10,7 @@ maintainers:
- Tom Joseph <tjoseph@cadence.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- $ref: cdns-pcie.yaml#
properties:

2
Documentation/devicetree/bindings/pci/faraday,ftpci100.yaml
View File

@ -51,7 +51,7 @@ description: |
<0x6000 0 0 4 &pci_intc 2>;
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:

102
Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml Normal file
View File

@ -0,0 +1,102 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Layerscape PCIe Endpoint(EP) controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.
This controller derives its clocks from the Reset Configuration Word (RCW)
which is used to describe the PLL settings at the time of chip-reset.
Also as per the available Reference Manuals, there is no specific 'version'
register available in the Freescale PCIe controller register set,
which can allow determining the underlying DesignWare PCIe controller version
information.
properties:
compatible:
enum:
- fsl,ls2088a-pcie-ep
- fsl,ls1088a-pcie-ep
- fsl,ls1046a-pcie-ep
- fsl,ls1028a-pcie-ep
- fsl,lx2160ar2-pcie-ep
reg:
maxItems: 2
reg-names:
items:
- const: regs
- const: addr_space
fsl,pcie-scfg:
$ref: /schemas/types.yaml#/definitions/phandle
description: A phandle to the SCFG device node. The second entry is the
physical PCIe controller index starting from '0'. This is used to get
SCFG PEXN registers.
big-endian:
$ref: /schemas/types.yaml#/definitions/flag
description: If the PEX_LUT and PF register block is in big-endian, specify
this property.
dma-coherent: true
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
minItems: 1
maxItems: 2
required:
- compatible
- reg
- reg-names
allOf:
- if:
properties:
compatible:
enum:
- fsl,ls1028a-pcie-ep
- fsl,ls1046a-pcie-ep
- fsl,ls1088a-pcie-ep
then:
properties:
interrupt-names:
items:
- const: pme
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie_ep1: pcie-ep@3400000 {
compatible = "fsl,ls1028a-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000
0x80 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
interrupt-names = "pme";
num-ib-windows = <6>;
num-ob-windows = <8>;
status = "disabled";
};
};
...

167
Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml Normal file
View File

@ -0,0 +1,167 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Layerscape PCIe Root Complex(RC) controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
This controller derives its clocks from the Reset Configuration Word (RCW)
which is used to describe the PLL settings at the time of chip-reset.
Also as per the available Reference Manuals, there is no specific 'version'
register available in the Freescale PCIe controller register set,
which can allow determining the underlying DesignWare PCIe controller version
information.
properties:
compatible:
enum:
- fsl,ls1021a-pcie
- fsl,ls2080a-pcie
- fsl,ls2085a-pcie
- fsl,ls2088a-pcie
- fsl,ls1088a-pcie
- fsl,ls1046a-pcie
- fsl,ls1043a-pcie
- fsl,ls1012a-pcie
- fsl,ls1028a-pcie
- fsl,lx2160a-pcie
reg:
maxItems: 2
reg-names:
items:
- const: regs
- const: config
fsl,pcie-scfg:
$ref: /schemas/types.yaml#/definitions/phandle
description: A phandle to the SCFG device node. The second entry is the
physical PCIe controller index starting from '0'. This is used to get
SCFG PEXN registers.
big-endian:
$ref: /schemas/types.yaml#/definitions/flag
description: If the PEX_LUT and PF register block is in big-endian, specify
this property.
dma-coherent: true
msi-parent: true
iommu-map: true
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
minItems: 1
maxItems: 2
required:
- compatible
- reg
- reg-names
- "#address-cells"
- "#size-cells"
- device_type
- bus-range
- ranges
- interrupts
- interrupt-names
- "#interrupt-cells"
- interrupt-map-mask
- interrupt-map
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- if:
properties:
compatible:
enum:
- fsl,ls1028a-pcie
- fsl,ls1046a-pcie
- fsl,ls1043a-pcie
- fsl,ls1012a-pcie
then:
properties:
interrupts:
maxItems: 2
interrupt-names:
items:
- const: pme
- const: aer
- if:
properties:
compatible:
enum:
- fsl,ls2080a-pcie
- fsl,ls2085a-pcie
- fsl,ls2088a-pcie
then:
properties:
interrupts:
maxItems: 1
interrupt-names:
items:
- const: intr
- if:
properties:
compatible:
enum:
- fsl,ls1088a-pcie
then:
properties:
interrupts:
maxItems: 1
interrupt-names:
items:
- const: aer
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie@3400000 {
compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x20 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
dma-coherent;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
};
};
...

2
Documentation/devicetree/bindings/pci/host-generic-pci.yaml
View File

@ -116,7 +116,7 @@ required:
- ranges
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- if:
properties:
compatible:

2
Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml
View File

@ -12,7 +12,7 @@ maintainers:
description: PCI host controller found in the Intel IXP4xx SoC series.
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:

2
Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml
View File

@ -11,7 +11,7 @@ maintainers:
- Srikanth Thokala <srikanth.thokala@intel.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:

79
Documentation/devicetree/bindings/pci/layerscape-pci.txt
View File

@ -1,79 +0,0 @@
Freescale Layerscape PCIe controller
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
This controller derives its clocks from the Reset Configuration Word (RCW)
which is used to describe the PLL settings at the time of chip-reset.
Also as per the available Reference Manuals, there is no specific 'version'
register available in the Freescale PCIe controller register set,
which can allow determining the underlying DesignWare PCIe controller version
information.
Required properties:
- compatible: should contain the platform identifier such as:
RC mode:
"fsl,ls1021a-pcie"
"fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
"fsl,ls2088a-pcie"
"fsl,ls1088a-pcie"
"fsl,ls1046a-pcie"
"fsl,ls1043a-pcie"
"fsl,ls1012a-pcie"
"fsl,ls1028a-pcie"
EP mode:
"fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"
"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
"fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"
- reg: base addresses and lengths of the PCIe controller register blocks.
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
- interrupt-names: It could include the following entries:
"aer": Used for interrupt line which reports AER events when
non MSI/MSI-X/INTx mode is used
"pme": Used for interrupt line which reports PME events when
non MSI/MSI-X/INTx mode is used
"intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
which has a single interrupt line for miscellaneous controller
events(could include AER and PME events).
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
The second entry is the physical PCIe controller index starting from '0'.
This is used to get SCFG PEXN registers
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
of the data transferred from/to the IP block. This can avoid the software
cache flush/invalid actions, and improve the performance significantly.
Optional properties:
- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
this property.
Example:
pcie@3400000 {
compatible = "fsl,ls1088a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x20 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-viewport = <256>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
};

2
Documentation/devicetree/bindings/pci/loongson.yaml
View File

@ -13,7 +13,7 @@ description: |+
PCI host controller found on Loongson PCHs and SoCs.
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:

7
Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml
View File

@ -14,7 +14,7 @@ description: |+
with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:
@ -33,9 +33,12 @@ properties:
patternProperties:
'^pcie@[0-2],0$':
type: object
$ref: /schemas/pci/pci-bus.yaml#
$ref: /schemas/pci/pci-pci-bridge.yaml#
properties:
reg:
maxItems: 1
resets:
maxItems: 1

2
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
View File

@ -140,7 +140,7 @@ required:
- interrupt-controller
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- if:
properties:
compatible:

2
Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
View File

@ -10,7 +10,7 @@ maintainers:
- Daire McNamara <daire.mcnamara@microchip.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
properties:

2
Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
View File

@ -95,6 +95,6 @@ anyOf:
- msi-map
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
additionalProperties: true

2
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
View File

@ -130,7 +130,7 @@ anyOf:
- msi-map
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- if:
properties:
compatible:

4
Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
View File

@ -16,7 +16,9 @@ allOf:
properties:
compatible:
items:
- const: renesas,r8a779f0-pcie-ep # R-Car S4-8
- enum:
- renesas,r8a779f0-pcie-ep # R-Car S4-8
- renesas,r8a779g0-pcie-ep # R-Car V4H
- const: renesas,rcar-gen4-pcie-ep # R-Car Gen4
reg:

4
Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
View File

@ -16,7 +16,9 @@ allOf:
properties:
compatible:
items:
- const: renesas,r8a779f0-pcie # R-Car S4-8
- enum:
- renesas,r8a779f0-pcie # R-Car S4-8
- renesas,r8a779g0-pcie # R-Car V4H
- const: renesas,rcar-gen4-pcie # R-Car Gen4
reg:

5
Documentation/devicetree/bindings/pci/rcar-pci-host.yaml
View File

@ -12,7 +12,7 @@ maintainers:
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
allOf:
- $ref: pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:
@ -77,6 +77,9 @@ properties:
vpcie12v-supply:
description: The 12v regulator to use for PCIe.
iommu-map: true
iommu-map-mask: true
required:
- compatible
- reg

2
Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
View File

@ -110,7 +110,7 @@ required:
- "#interrupt-cells"
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- if:
properties:

3
Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
View File

@ -10,7 +10,7 @@ maintainers:
- Shawn Lin <shawn.lin@rock-chips.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- $ref: rockchip,rk3399-pcie-common.yaml#
properties:
@ -37,6 +37,7 @@ properties:
description: This property is needed if using 24MHz OSC for RC's PHY.
ep-gpios:
maxItems: 1
description: pre-reset GPIO
vpcie12v-supply:

2
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
View File

@ -23,7 +23,7 @@ select:
- compatible
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- $ref: /schemas/pci/snps,dw-pcie-common.yaml#
- if:
not:

22
Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
View File

@ -11,7 +11,7 @@ maintainers:
- Kishon Vijay Abraham I <kishon@ti.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:
@ -55,6 +55,20 @@ properties:
dma-coherent: true
num-viewport:
$ref: /schemas/types.yaml#/definitions/uint32
phys:
description: per-lane PHYs
minItems: 1
maxItems: 2
phy-names:
minItems: 1
maxItems: 2
items:
pattern: '^pcie-phy[0-1]$'
required:
- compatible
- reg
@ -74,6 +88,7 @@ then:
- dma-coherent
- power-domains
- msi-map
- num-viewport
unevaluatedProperties: false
@ -81,6 +96,7 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
pcie0_rc: pcie@5500000 {
@ -98,9 +114,13 @@ examples:
ti,syscon-pcie-id = <&scm_conf 0x0210>;
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
bus-range = <0x0 0xff>;
num-viewport = <16>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
device_type = "pci";
num-lanes = <1>;
phys = <&serdes0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy0";
};

5
Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
View File

@ -23,6 +23,10 @@ properties:
items:
- const: ti,j7200-pcie-host
- const: ti,j721e-pcie-host
- description: PCIe controller in J722S
items:
- const: ti,j722s-pcie-host
- const: ti,j721e-pcie-host
reg:
maxItems: 4
@ -68,6 +72,7 @@ properties:
- 0xb00d
- 0xb00f
- 0xb010
- 0xb012
- 0xb013
msi-map: true

2
Documentation/devicetree/bindings/pci/versatile.yaml
View File

@ -13,7 +13,7 @@ description: |+
PCI host controller found on the ARM Versatile PB board's FPGA.
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:

2
Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
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@ -10,7 +10,7 @@ maintainers:
- Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:

2
Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml
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@ -10,7 +10,7 @@ maintainers:
- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible:

2
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
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@ -10,7 +10,7 @@ maintainers:
- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
properties:

2
Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml
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@ -10,7 +10,7 @@ maintainers:
- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/pci/pci-host-bridge.yaml#
properties:
compatible: