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arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

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The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
correction has been implemented/enforced by the updates to:
a) Device-Tree binding for CPSW [0]
b) Driver for CPSW [1]
c) Driver for CPSW MAC Port's GMII [2]

To complete the transition from 'RGMII-RXID' to 'RGMII-ID', update the
'phy-mode' property for all CPSW ports by replacing 'rgmii-rxid' with
'rgmii-id'.

[0]: commit 9b357ea525 ("dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example")
[1]: commit ca13b249f2 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
[2]: commit a22d3b0d49 ("phy: ti: gmii-sel: Always write the RGMII ID setting")

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Tested-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> # k3-am642-tqma64xxl-mbax4xxl
Tested-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Toradex Verdin AM62P
Link: https://patch.msgid.link/20251025073802.1790437-1-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Siddharth Vadapalli 2025-10-25 13:07:59 +05:30 committed by Vignesh Raghavendra
parent c9836bf7c3
commit 1446fc4dc0
33 changed files with 40 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
View File

@ -214,7 +214,7 @@ &cpsw3g {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy1>;
bootph-all;
};

2
arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi
View File

@ -74,7 +74,7 @@ &cpsw_port1 {
/* Verdin ETH_2_RGMII */
&cpsw_port2 {
phy-handle = <&cpsw3g_phy1>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
status = "okay";
};

2
arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi
View File

@ -268,7 +268,7 @@ &cpsw_port1 {
/* Verdin ETH_2_RGMII */
&cpsw_port2 {
phy-handle = <&cpsw3g_phy1>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
status = "okay";
};

2
arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
View File

@ -845,7 +845,7 @@ &cpsw3g {
/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
phy-handle = <&cpsw3g_phy0>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
status = "disabled";
};

2
arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
View File

@ -593,7 +593,7 @@ &cpsw3g {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy0>;
};

3
arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
View File

@ -215,8 +215,7 @@ &cpsw3g {
};
&cpsw_port2 {
/* PCB provides an internal delay of 2ns */
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy1>;
};

2
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
View File

@ -192,7 +192,7 @@ &cpsw3g {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy1>;
bootph-all;
};

2
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
View File

@ -731,7 +731,7 @@ &phy_gmii_sel {
&cpsw_port1 {
status = "okay";
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy0>;
bootph-all;
};

2
arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi
View File

@ -78,7 +78,7 @@ &cpsw_port1 {
/* Verdin ETH_2_RGMII */
&cpsw_port2 {
phy-handle = <&carrier_eth_phy>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
status = "okay";
};

2
arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi
View File

@ -275,7 +275,7 @@ &cpsw_port1 {
/* Verdin ETH_2_RGMII */
&cpsw_port2 {
phy-handle = <&carrier_eth_phy>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
status = "okay";
};

2
arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
View File

@ -813,7 +813,7 @@ som_eth_phy: ethernet-phy@0 {
/* Verdin ETH_1 (On-module PHY) */
&cpsw_port1 {
phy-handle = <&som_eth_phy>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
status = "disabled";
};

4
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
View File

@ -541,14 +541,14 @@ &cpsw3g {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
bootph-all;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy1>;
status = "okay";
};

2
arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
View File

@ -291,7 +291,7 @@ &cpsw3g {
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy3>;
};

2
arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
View File

@ -438,7 +438,7 @@ &cpsw3g {
&cpsw_port1 {
bootph-all;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy0>;
};

2
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
View File

@ -178,7 +178,7 @@ cpsw3g_phy1: ethernet-phy@1 {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy1>;
bootph-all;
status = "okay";

4
arch/arm64/boot/dts/ti/k3-am642-evm.dts
View File

@ -579,13 +579,13 @@ &cpsw3g {
&cpsw_port1 {
bootph-all;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy3>;
status = "okay";
};

4
arch/arm64/boot/dts/ti/k3-am642-sk.dts
View File

@ -499,13 +499,13 @@ &cpsw3g {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy1>;
status = "okay";
};

2
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
View File

@ -186,7 +186,7 @@ &cpsw3g {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
};

2
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
View File

@ -586,7 +586,7 @@ phy0: ethernet-phy@0 {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
};

2
arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts
View File

@ -249,7 +249,7 @@ cpsw3g_phy0: ethernet-phy@0 {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
};

2
arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts
View File

@ -281,7 +281,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
};

2
arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi
View File

@ -175,7 +175,7 @@ phy1: ethernet-phy@0 {
&main_cpsw_port1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
status = "okay";
};

2
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
View File

@ -705,7 +705,7 @@ phy0: ethernet-phy@0 {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
bootph-all;
};

2
arch/arm64/boot/dts/ti/k3-am69-sk.dts
View File

@ -771,7 +771,7 @@ mcu_phy0: ethernet-phy@0 {
&mcu_cpsw_port1 {
status = "okay";
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&mcu_phy0>;
bootph-all;
};

2
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
View File

@ -334,7 +334,7 @@ phy0: ethernet-phy@0 {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
};

2
arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
View File

@ -677,7 +677,7 @@ phy0: ethernet-phy@0 {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
};

2
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
View File

@ -780,7 +780,7 @@ phy0: ethernet-phy@0 {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
};

8
arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso
View File

@ -37,7 +37,7 @@ &rgmii3_default_pins
&cpsw0_port1 {
status = "okay";
phy-handle = <&cpsw9g_phy12>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 1>;
};
@ -45,7 +45,7 @@ &cpsw0_port1 {
&cpsw0_port2 {
status = "okay";
phy-handle = <&cpsw9g_phy15>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 2>;
};
@ -53,7 +53,7 @@ &cpsw0_port2 {
&cpsw0_port3 {
status = "okay";
phy-handle = <&cpsw9g_phy0>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 3>;
};
@ -61,7 +61,7 @@ &cpsw0_port3 {
&cpsw0_port4 {
status = "okay";
phy-handle = <&cpsw9g_phy3>;
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 4>;
};

2
arch/arm64/boot/dts/ti/k3-j721e-sk.dts
View File

@ -1045,7 +1045,7 @@ phy0: ethernet-phy@0 {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
};

2
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
View File

@ -469,7 +469,7 @@ phy0: ethernet-phy@0 {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
};

2
arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
View File

@ -80,6 +80,6 @@ main_cpsw_phy0: ethernet-phy@0 {
&main_cpsw_port1 {
status = "okay";
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&main_cpsw_phy0>;
};

2
arch/arm64/boot/dts/ti/k3-j722s-evm.dts
View File

@ -393,7 +393,7 @@ cpsw3g_phy0: ethernet-phy@0 {
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&cpsw3g_phy0>;
status = "okay";
bootph-all;

4
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
View File

@ -920,7 +920,7 @@ mcu_phy0: ethernet-phy@0 {
&mcu_cpsw_port1 {
status = "okay";
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&mcu_phy0>;
};
@ -944,7 +944,7 @@ main_cpsw1_phy0: ethernet-phy@0 {
};
&main_cpsw1_port1 {
phy-mode = "rgmii-rxid";
phy-mode = "rgmii-id";
phy-handle = <&main_cpsw1_phy0>;
status = "okay";
};