From f80c43887ab3bea4f8b1e112dc1dcc044904cf7b Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 19 Jan 2024 11:11:25 +0000 Subject: [PATCH 01/19] dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit Add dt-schema documentation for the Connectivity Peripheral 0 (PERIC0) clock management unit. Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Reviewed-by: Rob Herring Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240119111132.1290455-2-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/google,gs101-clock.yaml | 25 +++++- include/dt-bindings/clock/google,gs101.h | 81 +++++++++++++++++++ 2 files changed, 104 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 3eebc03a309b..b1202a4f6593 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -30,14 +30,15 @@ properties: - google,gs101-cmu-top - google,gs101-cmu-apm - google,gs101-cmu-misc + - google,gs101-cmu-peric0 clocks: minItems: 1 - maxItems: 2 + maxItems: 3 clock-names: minItems: 1 - maxItems: 2 + maxItems: 3 "#clock-cells": const: 1 @@ -88,6 +89,26 @@ allOf: - const: dout_cmu_misc_bus - const: dout_cmu_misc_sss + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-peric0 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: Connectivity Peripheral 0 bus clock (from CMU_TOP) + - description: Connectivity Peripheral 0 IP clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: ip + additionalProperties: false examples: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 21adec22387c..64e6bdc6359c 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -389,4 +389,85 @@ #define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73 #define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74 +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_BUS_USER 1 +#define CLK_MOUT_PERIC0_I3C_USER 2 +#define CLK_MOUT_PERIC0_USI0_UART_USER 3 +#define CLK_MOUT_PERIC0_USI14_USI_USER 4 +#define CLK_MOUT_PERIC0_USI1_USI_USER 5 +#define CLK_MOUT_PERIC0_USI2_USI_USER 6 +#define CLK_MOUT_PERIC0_USI3_USI_USER 7 +#define CLK_MOUT_PERIC0_USI4_USI_USER 8 +#define CLK_MOUT_PERIC0_USI5_USI_USER 9 +#define CLK_MOUT_PERIC0_USI6_USI_USER 10 +#define CLK_MOUT_PERIC0_USI7_USI_USER 11 +#define CLK_MOUT_PERIC0_USI8_USI_USER 12 +#define CLK_DOUT_PERIC0_I3C 13 +#define CLK_DOUT_PERIC0_USI0_UART 14 +#define CLK_DOUT_PERIC0_USI14_USI 15 +#define CLK_DOUT_PERIC0_USI1_USI 16 +#define CLK_DOUT_PERIC0_USI2_USI 17 +#define CLK_DOUT_PERIC0_USI3_USI 18 +#define CLK_DOUT_PERIC0_USI4_USI 19 +#define CLK_DOUT_PERIC0_USI5_USI 20 +#define CLK_DOUT_PERIC0_USI6_USI 21 +#define CLK_DOUT_PERIC0_USI7_USI 22 +#define CLK_DOUT_PERIC0_USI8_USI 23 +#define CLK_GOUT_PERIC0_IP 24 +#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25 +#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26 +#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27 +#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28 +#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29 +#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61 +#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65 +#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66 +#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67 +#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77 +#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78 +#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ From bc8cc7fb55b8da8c6b947603b1bad585e866b90c Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Fri, 19 Jan 2024 19:29:42 -0600 Subject: [PATCH 02/19] dt-bindings: clock: exynos850: Add PDMA clocks Add constants for Peripheral DMA (PDMA) clocks in CMU_CORE controller: - PDMA_ACLK: clock for PDMA0 (regular DMA) - SPDMA_ACLK: clock for PDMA1 (secure DMA) Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20240120012948.8836-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/exynos850.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 3090e09c9a55..bc15108aa3c2 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -320,6 +320,8 @@ #define CLK_GOUT_SSS_PCLK 12 #define CLK_GOUT_GPIO_CORE_PCLK 13 #define CLK_GOUT_SYSREG_CORE_PCLK 14 +#define CLK_GOUT_PDMA_CORE_ACLK 15 +#define CLK_GOUT_SPDMA_CORE_ACLK 16 /* CMU_DPU */ #define CLK_MOUT_DPU_USER 1 From 927b46b543c83a3220b3d931744eab545345faf4 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Fri, 22 Dec 2023 16:53:55 +0000 Subject: [PATCH 03/19] arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node MCT has one global timer and 8 CPU local timers. The global timer can generate 4 interrupts, and each local timer can generate an interrupt making 12 interrupts in total. Signed-off-by: Peter Griffin Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20231222165355.1462740-4-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9747cb3fa03a..4b09e740b58a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -292,6 +292,26 @@ cmu_misc: clock-controller@10010000 { clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss"; }; + timer@10050000 { + compatible = "google,gs101-mct", + "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; + watchdog_cl0: watchdog@10060000 { compatible = "google,gs101-wdt"; reg = <0x10060000 0x100>; From af5c317a93ef168c105bd28afdd675e962244591 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 19 Jan 2024 11:11:28 +0000 Subject: [PATCH 04/19] arm64: dts: exynos: gs101: remove reg-io-width from serial Remove the reg-io-width property in order to comply with the bindings. The entire bus (PERIC) on which the GS101 serial resides only allows 32-bit register accesses. The reg-io-width dt property is disallowed for the "google,gs101-uart" compatible and instead the iotype is inferred from the compatible. Reviewed-by: Peter Griffin Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240119111132.1290455-5-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 4b09e740b58a..d6a2644d0b48 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -386,7 +386,6 @@ usi_uart: usi@10a000c0 { serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - reg-io-width = <4>; interrupts = ; clocks = <&dummy_clk 0>, <&dummy_clk 0>; From e62c706f3aa0cf1c2b4a71542cb07223e68453c6 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 19 Jan 2024 11:11:29 +0000 Subject: [PATCH 05/19] arm64: dts: exynos: gs101: enable cmu-peric0 clock controller Enable the cmu-peric0 clock controller. It feeds USI and I3c. Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240119111132.1290455-6-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index d6a2644d0b48..3b1b6aa1b299 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -359,6 +359,16 @@ ppi_cluster2: interrupt-partition-2 { }; }; + cmu_peric0: clock-controller@10800000 { + compatible = "google,gs101-cmu-peric0"; + reg = <0x10800000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + sysreg_peric0: syscon@10820000 { compatible = "google,gs101-peric0-sysreg", "syscon"; reg = <0x10820000 0x10000>; From d97b6c902a40673debee3cb98d79405193890f34 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 19 Jan 2024 11:11:30 +0000 Subject: [PATCH 06/19] arm64: dts: exynos: gs101: update USI UART to use peric0 clocks Get rid of the dummy clock and start using the cmu_peric0 clocks for the usi_uart and serial_0 nodes. Tested the serial at 115200, 1000000 and 3000000 baudrates, everthing went fine. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240119111132.1290455-7-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 3b1b6aa1b299..dd2d6eededaa 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -180,14 +180,6 @@ HERA_CPU_SLEEP: cpu-hera-sleep { }; }; - /* TODO replace with CCF clock */ - dummy_clk: clock-3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12345>; - clock-output-names = "pclk"; - }; - /* ect node is required to be present by bootloader */ ect { }; @@ -387,7 +379,8 @@ usi_uart: usi@10a000c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&dummy_clk>, <&dummy_clk>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; samsung,mode = ; @@ -398,7 +391,8 @@ serial_0: serial@10a00000 { reg = <0x10a00000 0xc0>; interrupts = ; - clocks = <&dummy_clk 0>, <&dummy_clk 0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; status = "disabled"; From 6d44d1a1fb62e033dde18d73cbbb604663eb84c0 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 19 Jan 2024 11:11:31 +0000 Subject: [PATCH 07/19] arm64: dts: exynos: gs101: define USI8 with I2C configuration USI8 I2C is used to communicate with an eeprom found on the battery connector. Define USI8 in I2C configuration. USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8 doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the selection of the protocol is intentionally left for the board dts file. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240119111132.1290455-8-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index dd2d6eededaa..6ded153cb475 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -372,6 +372,35 @@ pinctrl_peric0: pinctrl@10840000 { interrupts = ; }; + usi8: usi@109700c0 { + compatible = "google,gs101-usi", + "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x101c>; + status = "disabled"; + + hsi2c_8: i2c@10970000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + usi_uart: usi@10a000c0 { compatible = "google,gs101-usi", "samsung,exynos850-usi"; From f6553769131bdc9dc4f8ccb7c7dfabe49028f817 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 19 Jan 2024 11:11:32 +0000 Subject: [PATCH 08/19] arm64: dts: exynos: gs101: enable eeprom on gs101-oriole Enable the eeprom found on the battery connector. The selection of the USI protocol is done in the board dts file because the USI CONFIG register comes with a 0x0 reset value, meaning that USI8 does not have a default protocol (I2C, SPI, UART) at reset. Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240119111132.1290455-9-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 4a71f752200d..cb4d17339b6b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -63,6 +63,15 @@ &ext_200m { clock-frequency = <200000000>; }; +&hsi2c_8 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + &pinctrl_far_alive { key_voldown: key-voldown-pins { samsung,pins = "gpa7-3"; @@ -99,6 +108,11 @@ &usi_uart { status = "okay"; }; +&usi8 { + samsung,mode = ; + status = "okay"; +}; + &watchdog_cl0 { timeout-sec = <30>; status = "okay"; From ca487bc2776e6b2465fcddb0a0fc121c0ff7b118 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Fri, 26 Jan 2024 11:55:17 +0000 Subject: [PATCH 09/19] arm64: dts: exynos: gs101: sysreg_peric0 needs a clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without the clock running, we can not access its registers, and now that we have it, we should add it here so that it gets enabled as and when needed. Update the DTSI accordingly. Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240126115517.1751971-2-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 6ded153cb475..f1c0f6760066 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -364,6 +364,7 @@ cmu_peric0: clock-controller@10800000 { sysreg_peric0: syscon@10820000 { compatible = "google,gs101-peric0-sysreg", "syscon"; reg = <0x10820000 0x10000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; }; pinctrl_peric0: pinctrl@10840000 { From 512b5a875cd8b8352257fefe71513097ee97be77 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 30 Jan 2024 09:36:42 +0000 Subject: [PATCH 10/19] arm64: dts: exynos: gs101: use correct clocks for usi8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wrong pclk clocks have been used in this usi8 instance here. For USI and I2C, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI8_USI_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and i2c drivers. Fixes: 6d44d1a1fb62 ("arm64: dts: exynos: gs101: define USI8 with I2C configuration") Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Tested-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240130093812.1746512-4-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index f1c0f6760066..9022afa97266 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -380,7 +380,7 @@ usi8: usi@109700c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x101c>; @@ -396,7 +396,7 @@ hsi2c_8: i2c@10970000 { pinctrl-names = "default"; pinctrl-0 = <&hsi2c8_bus>; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, - <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names = "hsi2c", "hsi2c_pclk"; status = "disabled"; }; From 21e4e8807bfc7acc0fc9fe3ab69e1dc0662e7ce4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 30 Jan 2024 09:36:43 +0000 Subject: [PATCH 11/19] arm64: dts: exynos: gs101: use correct clocks for usi_uart MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wrong pclk clocks have been used in this usi_uart instance here. For USI and UART, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI0_UART_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and uart drivers. Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Tested-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240130093812.1746512-5-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9022afa97266..1dc6b08be1bf 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -409,7 +409,7 @@ usi_uart: usi@10a000c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; @@ -421,7 +421,7 @@ serial_0: serial@10a00000 { reg = <0x10a00000 0xc0>; interrupts = ; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; From c0fe557853f3d4b61c4e2e729061482f4da901db Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 24 Jan 2024 19:38:57 -0600 Subject: [PATCH 12/19] arm64: dts: exynos: Add PDMA node for Exynos850 Enable PDMA node. It's needed for multiple peripheral modules, like SPI. Use "arm,pl330-broken-no-flushp" quirk, as otherwise SPI transfers in DMA mode often fail with error like this: I/O Error: rx-1 tx-1 rx-f tx-f len-786 dma-1 res-(-5) Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20240125013858.3986-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index da3f4a791e68..e7e1171a3864 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -184,6 +184,16 @@ timer@10040000 { clock-names = "fin_pll", "mct"; }; + pdma0: dma-controller@120c0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x120c0000 0x1000>; + clocks = <&cmu_core CLK_GOUT_PDMA_CORE_ACLK>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + interrupts = ; + arm,pl330-broken-no-flushp; + }; + gic: interrupt-controller@12a01000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From 2ef4cddd31950f563b5642e34d8fa38ad2352ef0 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Thu, 1 Feb 2024 12:30:25 -0600 Subject: [PATCH 13/19] arm64: dts: exynos: Add SPI nodes for Exynos850 Some USI blocks can be configured as SPI controllers. Add corresponding SPI nodes to Exynos850 SoC device tree. Signed-off-by: Sam Protsenko Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240201183025.14566-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index e7e1171a3864..2ba67c3d0681 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -738,6 +738,24 @@ usi_spi_0: usi@139400c0 { <&cmu_peri CLK_GOUT_SPI0_IPCLK>; clock-names = "pclk", "ipclk"; status = "disabled"; + + spi_0: spi@13940000 { + compatible = "samsung,exynos850-spi"; + reg = <0x13940000 0x30>; + clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, + <&cmu_peri CLK_GOUT_SPI0_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 5>, <&pdma0 4>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; usi_cmgp0: usi@11d000c0 { @@ -779,6 +797,24 @@ serial_1: serial@11d00000 { clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; + + spi_1: spi@11d00000 { + compatible = "samsung,exynos850-spi"; + reg = <0x11d00000 0x30>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 12>, <&pdma0 13>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; usi_cmgp1: usi@11d200c0 { @@ -820,6 +856,24 @@ serial_2: serial@11d20000 { clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; + + spi_2: spi@11d20000 { + compatible = "samsung,exynos850-spi"; + reg = <0x11d20000 0x30>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 14>, <&pdma0 15>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; }; From 455061eb32434d5db11836a4de72ea2f4bdf61c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Thu, 1 Feb 2024 16:11:38 +0000 Subject: [PATCH 14/19] dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dt-schema documentation and clock IDs for the Connectivity Peripheral 1 (PERIC1) clock management unit. Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Reviewed-by: Tudor Ambarus Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20240201161258.1013664-3-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/google,gs101-clock.yaml | 9 ++-- include/dt-bindings/clock/google,gs101.h | 48 +++++++++++++++++++ 2 files changed, 54 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index b1202a4f6593..4a74d19cf488 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -31,6 +31,7 @@ properties: - google,gs101-cmu-apm - google,gs101-cmu-misc - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 clocks: minItems: 1 @@ -93,15 +94,17 @@ allOf: properties: compatible: contains: - const: google,gs101-cmu-peric0 + enum: + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 then: properties: clocks: items: - description: External reference clock (24.576 MHz) - - description: Connectivity Peripheral 0 bus clock (from CMU_TOP) - - description: Connectivity Peripheral 0 IP clock (from CMU_TOP) + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP) + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP) clock-names: items: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 64e6bdc6359c..3dac3577788a 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -470,4 +470,52 @@ #define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78 #define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79 +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_I3C_USER 2 +#define CLK_MOUT_PERIC1_USI0_USI_USER 3 +#define CLK_MOUT_PERIC1_USI10_USI_USER 4 +#define CLK_MOUT_PERIC1_USI11_USI_USER 5 +#define CLK_MOUT_PERIC1_USI12_USI_USER 6 +#define CLK_MOUT_PERIC1_USI13_USI_USER 7 +#define CLK_MOUT_PERIC1_USI9_USI_USER 8 +#define CLK_DOUT_PERIC1_I3C 9 +#define CLK_DOUT_PERIC1_USI0_USI 10 +#define CLK_DOUT_PERIC1_USI10_USI 11 +#define CLK_DOUT_PERIC1_USI11_USI 12 +#define CLK_DOUT_PERIC1_USI12_USI 13 +#define CLK_DOUT_PERIC1_USI13_USI 14 +#define CLK_DOUT_PERIC1_USI9_USI 15 +#define CLK_GOUT_PERIC1_IP 16 +#define CLK_GOUT_PERIC1_PCLK 17 +#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18 +#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19 +#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20 +#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21 +#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22 +#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38 +#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45 +#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ From 7d66d98b5bf376a999df13c65bbc0aac3cc9de02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Thu, 1 Feb 2024 16:11:41 +0000 Subject: [PATCH 15/19] arm64: dts: exynos: gs101: enable cmu-peric1 clock controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the cmu-peric1 clock controller. It feeds additional USI, I3C and PWM interfaces / busses. Note that &sysreg_peric1 needs a clock to be able to access its registers and now that Linux knows about this clock, we need to add it in this commit as well so as to keep &sysreg_peric1 working, so that the clock can be enabled as and when needed. Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240201161258.1013664-6-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 1dc6b08be1bf..f89e25777e4a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -429,9 +429,20 @@ serial_0: serial@10a00000 { }; }; + cmu_peric1: clock-controller@10c00000 { + compatible = "google,gs101-cmu-peric1"; + reg = <0x10c00000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + sysreg_peric1: syscon@10c20000 { compatible = "google,gs101-peric1-sysreg", "syscon"; reg = <0x10c20000 0x10000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; }; pinctrl_peric1: pinctrl@10c40000 { From 118261df42496241713cf8190535e9c90e7011f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Thu, 1 Feb 2024 16:11:42 +0000 Subject: [PATCH 16/19] arm64: dts: exynos: gs101: define USI12 with I2C configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On the gs101-oriole board, i2c bus 12 has various USB-related controllers attached to it. Note the selection of the USI protocol is intentionally left for the board dts file. Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240201161258.1013664-7-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index f89e25777e4a..73818285a041 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -451,6 +451,35 @@ pinctrl_peric1: pinctrl@10c40000 { interrupts = ; }; + usi12: usi@10d500c0 { + compatible = "google,gs101-usi", + "samsung,exynos850-usi"; + reg = <0x10d500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1010>; + status = "disabled"; + + hsi2c_12: i2c@10d50000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d50000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; From f9555ac036e253ca99a4d6d55e7e9402b77df77d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Thu, 1 Feb 2024 16:11:43 +0000 Subject: [PATCH 17/19] arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bus has three USB-related devices attached to it: 0x25: Maxim 77759 Type-C port controller 0x35: Maxim 20339EWB Surge protection IC 0x36: Maxim 77759 Fuel gauge 0x57: NXP PCA9468 Battery charger 0x66: Maxim 77759 PMIC 0x69: Maxim 77759 Charger where the Maxim 77759 has multiple i2c slave addresses. These don't have (upstream) Linux drivers yet, but nevertheless we can enable the bus so as to allow working on them (and to make i2cdetect / i2cdump / etc. work). Signed-off-by: André Draszik Reviewed-by: Peter Griffin Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240201161258.1013664-8-andre.draszik@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index cb4d17339b6b..6ccade2c8cb4 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -72,6 +72,11 @@ eeprom: eeprom@50 { }; }; +&hsi2c_12 { + status = "okay"; + /* TODO: add the devices once drivers exist */ +}; + &pinctrl_far_alive { key_voldown: key-voldown-pins { samsung,pins = "gpa7-3"; @@ -113,6 +118,11 @@ &usi8 { status = "okay"; }; +&usi12 { + samsung,mode = ; + status = "okay"; +}; + &watchdog_cl0 { timeout-sec = <30>; status = "okay"; From d5d19683451d0f79a6a953ae92d3836eb752ccb6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Feb 2024 11:52:43 +0100 Subject: [PATCH 18/19] arm64: dts: exynos: gs101: minor whitespace cleanup The DTS code coding style expects exactly one space before '{' and around '=' characters. Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Link: https://lore.kernel.org/r/20240208105243.128875-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/google/gs101-pinctrl.dtsi | 2 +- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi index e6a9776d4d62..a675f822acec 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi @@ -251,7 +251,7 @@ gph1: gph1-gpio-bank { #interrupt-cells = <2>; }; - pcie0_clkreq: pcie0-clkreq-pins{ + pcie0_clkreq: pcie0-clkreq-pins { samsung,pins = "gph0-1"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 73818285a041..7bca92bc1f8d 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -73,7 +73,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0000>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -83,7 +83,7 @@ cpu1: cpu@100 { compatible = "arm,cortex-a55"; reg = <0x0100>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -93,7 +93,7 @@ cpu2: cpu@200 { compatible = "arm,cortex-a55"; reg = <0x0200>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -103,7 +103,7 @@ cpu3: cpu@300 { compatible = "arm,cortex-a55"; reg = <0x0300>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -113,7 +113,7 @@ cpu4: cpu@400 { compatible = "arm,cortex-a76"; reg = <0x0400>; enable-method = "psci"; - cpu-idle-states = <&ENYO_CPU_SLEEP>; + cpu-idle-states = <&ENYO_CPU_SLEEP>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; }; @@ -123,7 +123,7 @@ cpu5: cpu@500 { compatible = "arm,cortex-a76"; reg = <0x0500>; enable-method = "psci"; - cpu-idle-states = <&ENYO_CPU_SLEEP>; + cpu-idle-states = <&ENYO_CPU_SLEEP>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; }; @@ -133,7 +133,7 @@ cpu6: cpu@600 { compatible = "arm,cortex-x1"; reg = <0x0600>; enable-method = "psci"; - cpu-idle-states = <&HERA_CPU_SLEEP>; + cpu-idle-states = <&HERA_CPU_SLEEP>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; }; @@ -143,7 +143,7 @@ cpu7: cpu@700 { compatible = "arm,cortex-x1"; reg = <0x0700>; enable-method = "psci"; - cpu-idle-states = <&HERA_CPU_SLEEP>; + cpu-idle-states = <&HERA_CPU_SLEEP>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; }; From 0791f541ff42f0ba7301f8caa7f3ab257284dc8f Mon Sep 17 00:00:00 2001 From: Tamseel Shams Date: Mon, 5 Feb 2024 13:56:25 +0530 Subject: [PATCH 19/19] arm64: dts: fsd: Add fifosize for UART in Device Tree UART in FSD SoC has fifosize of 64 bytes. Set fifosize as 64 bytes for UART from Device Tree. Signed-off-by: Tamseel Shams Link: https://lore.kernel.org/r/20240205082625.39259-1-m.shams@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/tesla/fsd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index aaffb50b8b60..047a83cee603 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -601,6 +601,7 @@ serial_0: serial@14180000 { clocks = <&clock_peric PERIC_PCLK_UART0>, <&clock_peric PERIC_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; status = "disabled"; }; @@ -613,6 +614,7 @@ serial_1: serial@14190000 { clocks = <&clock_peric PERIC_PCLK_UART1>, <&clock_peric PERIC_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; status = "disabled"; };