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HID: Intel-thc-hid: Intel-thc: Refine code comments
Align capitalization of the first characters for THC structure definition comments in header files. Signed-off-by: Even Xu <even.xu@intel.com> Signed-off-by: Jiri Kosina <jkosina@suse.com>
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@ -52,16 +52,16 @@ enum thc_int_type {
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* struct thc_device - THC private device struct
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* @thc_regmap: MMIO regmap structure for accessing THC registers
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* @mmio_addr: MMIO registers address
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* @thc_bus_lock: mutex locker for THC config
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* @port_type: port type of THC port instance
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* @thc_bus_lock: Mutex locker for THC config
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* @port_type: Port type of THC port instance
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* @pio_int_supported: PIO interrupt supported flag
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* @dma_ctx: DMA specific data
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* @write_complete_wait: signal event for DMA write complete
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* @swdma_complete_wait: signal event for SWDMA sequence complete
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* @write_done: bool value that indicates if DMA write is done
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* @swdma_done: bool value that indicates if SWDMA swquence is done
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* @perf_limit: the delay between read operation and write operation
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* @i2c_subip_regs: the copy of THC I2C sub-system registers for resuming restore
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* @write_complete_wait: Signal event for DMA write complete
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* @swdma_complete_wait: Signal event for SWDMA sequence complete
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* @write_done: Bool value that indicates if DMA write is done
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* @swdma_done: Bool value that indicates if SWDMA sequence is done
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* @perf_limit: The delay between read operation and write operation
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* @i2c_subip_regs: The copy of THC I2C sub-system registers for resuming restore
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*/
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struct thc_device {
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struct device *dev;
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@ -27,7 +27,7 @@
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/**
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* THC DMA channels:
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* @THC_RXDMA1: legacy channel, reserved for raw data reading
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* @THC_RXDMA1: Legacy channel, reserved for raw data reading
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* @THC_RXDMA2: DMA to read HID data from touch device
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* @THC_TXDMA: DMA to write to touch device
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* @THC_SWDMA: SW triggered DMA to write and read from touch device
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@ -42,11 +42,11 @@ enum thc_dma_channel {
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/**
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* THC DMA Physical Memory Descriptor (PRD)
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* @dest_addr: bit[53:0], destination address in system memory
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* @int_on_completion: bit[63], if set, thc will trigger interrupt to driver
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* @len: bit[87:64], length of this entry
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* @end_of_prd: bit[88], if set, this entry is last one of current PRD table
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* @hw_status: bit[90:89], hw status bits
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* @dest_addr: Bit[53:0], destination address in system memory
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* @int_on_completion: Bit[63], if set, thc will trigger interrupt to driver
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* @len: Bit[87:64], length of this entry
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* @end_of_prd: Bit[88], if set, this entry is last one of current PRD table
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* @hw_status: Bit[90:89], hardware status bits
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*/
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struct thc_prd_entry {
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u64 dest_addr : 54;
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@ -88,14 +88,14 @@ struct thc_prd_table {
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* struct thc_dma_configuration - THC DMA configure
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* @dma_channel: DMA channel for current DMA configuration
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* @prd_tbls_dma_handle: DMA buffer handle
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* @dir: direction of DMA for this config
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* @dir: Direction of DMA for this config
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* @prd_tbls: PRD tables for current DMA
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* @sgls: array of pointers to scatter-gather lists
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* @sgls_nent: actual number of entries per sg list
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* @prd_tbl_num: actual number of PRD tables
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* @max_packet_size: size of the buffer needed for 1 DMA message (1 PRD table)
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* @sgls: Array of pointers to scatter-gather lists
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* @sgls_nent: Actual number of entries per scatter-gather list
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* @prd_tbl_num: Actual number of PRD tables
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* @max_packet_size: Size of the buffer needed for 1 DMA message (1 PRD table)
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* @prd_base_addr_high: High 32bits memory address where stores PRD table
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* @prd_base_addr_low: low 32bits memory address where stores PRD table
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* @prd_base_addr_low: Low 32bits memory address where stores PRD table
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* @prd_cntrl: PRD control register value
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* @dma_cntrl: DMA control register value
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*/
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