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pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file

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Define `RZG2L_SINGLE_PIN` at the top of the file to clarify its use for
dedicated pins for improved readability.

While at it update the comment for `RZG2L_SINGLE_PIN_PACK` macro and place
it just above the macro for clarity.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240618174831.415583-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2024-06-18 18:48:30 +01:00 committed by Geert Uytterhoeven
parent f0cdf878a2
commit 13dcd63dc7
1 changed files with 7 additions and 7 deletions
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14
drivers/pinctrl/renesas/pinctrl-rzg2l.c
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@ -64,6 +64,8 @@
#define PIN_CFG_ELC BIT(20)
#define PIN_CFG_IOLH_RZV2H BIT(21)
#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
(PIN_CFG_IOLH_##group | \
PIN_CFG_PUPD | \
@ -105,15 +107,13 @@
*/
#define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
/*
* BIT(63) indicates dedicated pin, p is the register index while
* referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
* (b * 8) and f is the pin configuration capabilities supported.
*/
#define RZG2L_SINGLE_PIN BIT_ULL(63)
#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56)
#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53)
/*
* p is the register index while referencing to SR/IEN/IOLH/FILxx
* registers, b is the register bits (b * 8) and f is the pin
* configuration capabilities supported.
*/
#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \
FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \