mirror of
https://github.com/torvalds/linux.git
synced 2026-09-23 05:04:02 +02:00
arm64: Add override for ID_AA64MMFR4_EL1.NV_frac
In a very unsurprising turn of events, there is a large class of firmware that is totally unable to deal with FEAT_NV3, and doesn't set the required SCR2_EL3.NV3En bit, leading to an UNDEF exception or an unhandled trap to EL3, depending on the implementation. Allow the unfortunate user to override ID_AA64MMFR4_EL1.NV_frac and get a working system. Hopefully firmware will be fixed before actually HW ships, but I have been there before... :-/ Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://patch.msgid.link/20260730071022.296811-30-maz@kernel.org Signed-off-by: Oliver Upton <oupton@kernel.org>
This commit is contained in:
parent
1f4a10ff90
commit
13c164acef
|
|
@ -968,6 +968,7 @@ struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id);
|
|||
extern struct arm64_ftr_override id_aa64mmfr0_override;
|
||||
extern struct arm64_ftr_override id_aa64mmfr1_override;
|
||||
extern struct arm64_ftr_override id_aa64mmfr2_override;
|
||||
extern struct arm64_ftr_override id_aa64mmfr4_override;
|
||||
extern struct arm64_ftr_override id_aa64pfr0_override;
|
||||
extern struct arm64_ftr_override id_aa64pfr1_override;
|
||||
extern struct arm64_ftr_override id_aa64zfr0_override;
|
||||
|
|
|
|||
|
|
@ -785,6 +785,7 @@ static const struct arm64_ftr_bits ftr_raz[] = {
|
|||
struct arm64_ftr_override __read_mostly id_aa64mmfr0_override;
|
||||
struct arm64_ftr_override __read_mostly id_aa64mmfr1_override;
|
||||
struct arm64_ftr_override __read_mostly id_aa64mmfr2_override;
|
||||
struct arm64_ftr_override __read_mostly id_aa64mmfr4_override;
|
||||
struct arm64_ftr_override __read_mostly id_aa64pfr0_override;
|
||||
struct arm64_ftr_override __read_mostly id_aa64pfr1_override;
|
||||
struct arm64_ftr_override __read_mostly id_aa64zfr0_override;
|
||||
|
|
@ -858,7 +859,8 @@ static const struct __ftr_reg_entry {
|
|||
ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2,
|
||||
&id_aa64mmfr2_override),
|
||||
ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),
|
||||
ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4),
|
||||
ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4,
|
||||
&id_aa64mmfr4_override),
|
||||
|
||||
/* Op1 = 0, CRn = 10, CRm = 4 */
|
||||
ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr),
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ PI_EXPORT_SYM(id_aa64isar2_override);
|
|||
PI_EXPORT_SYM(id_aa64mmfr0_override);
|
||||
PI_EXPORT_SYM(id_aa64mmfr1_override);
|
||||
PI_EXPORT_SYM(id_aa64mmfr2_override);
|
||||
PI_EXPORT_SYM(id_aa64mmfr4_override);
|
||||
PI_EXPORT_SYM(id_aa64pfr0_override);
|
||||
PI_EXPORT_SYM(id_aa64pfr1_override);
|
||||
PI_EXPORT_SYM(id_aa64smfr0_override);
|
||||
|
|
|
|||
|
|
@ -106,6 +106,15 @@ static const struct ftr_set_desc mmfr2 __prel64_initconst = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct ftr_set_desc mmfr4 __prel64_initconst = {
|
||||
.name = "id_aa64mmfr4",
|
||||
.override = &id_aa64mmfr4_override,
|
||||
.fields = {
|
||||
FIELD("nv_frac", ID_AA64MMFR4_EL1_NV_frac_SHIFT, NULL),
|
||||
{}
|
||||
},
|
||||
};
|
||||
|
||||
static bool __init pfr0_sve_filter(u64 val)
|
||||
{
|
||||
/*
|
||||
|
|
@ -220,6 +229,7 @@ PREL64(const struct ftr_set_desc, reg) regs[] __prel64_initconst = {
|
|||
{ &mmfr0 },
|
||||
{ &mmfr1 },
|
||||
{ &mmfr2 },
|
||||
{ &mmfr4 },
|
||||
{ &pfr0 },
|
||||
{ &pfr1 },
|
||||
{ &isar1 },
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user