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arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file

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As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to
RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory
range. This shows that I/O memory has never been used/working on the
old SoCs despite the region being advertised. As PCIe I/O ranges will
not be supported in newer SoCs using CP11x co-processors, let's
simply drop them. It is not harmful in any case as PCIe device drivers
can do it all with the regular mapped memory anyway.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Miquel Raynal 2019-10-04 16:27:30 +02:00 committed by Gregory CLEMENT
parent 47cf40af64
commit 1399672e48
4 changed files with 4 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/marvell/armada-70x0.dtsi
View File

@ -19,7 +19,6 @@ aliases {
*/
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
#define CP11X_PCIE_IO_BASE 0xf9000000
#define CP11X_PCIE_MEM_BASE 0xf6000000
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
@ -29,7 +28,6 @@ aliases {
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIE_IO_BASE
#undef CP11X_PCIE_MEM_BASE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE

3
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
View File

@ -179,8 +179,7 @@ &cp0_pcie0 {
num-lanes = <4>;
num-viewport = <8>;
reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
<&cp0_comphy2 0>, <&cp0_comphy3 0>;
phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",

4
arch/arm64/boot/dts/marvell/armada-80x0.dtsi
View File

@ -21,7 +21,6 @@ aliases {
*/
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
#define CP11X_PCIE_IO_BASE 0xf9000000
#define CP11X_PCIE_MEM_BASE 0xf6000000
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
@ -31,7 +30,6 @@ aliases {
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIE_IO_BASE
#undef CP11X_PCIE_MEM_BASE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
@ -42,7 +40,6 @@ aliases {
*/
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
#define CP11X_PCIE_IO_BASE 0xfd000000
#define CP11X_PCIE_MEM_BASE 0xfa000000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
@ -52,7 +49,6 @@ aliases {
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIE_IO_BASE
#undef CP11X_PCIE_MEM_BASE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE

16
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
View File

@ -10,7 +10,6 @@
#include "armada-common.dtsi"
#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface * 0x10000))
#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
@ -507,11 +506,8 @@ CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0) 0 0x10000
/* non-prefetchable memory */
0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
@ -534,11 +530,8 @@ CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1) 0 0x10000
/* non-prefetchable memory */
0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
@ -562,11 +555,8 @@ CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2) 0 0x10000
/* non-prefetchable memory */
0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;