From 134f3c7022b5d3f129a62c3df5d126967227075e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= Date: Tue, 27 Jan 2026 14:41:10 +0200 Subject: [PATCH] drm/i915/psr: Add TRANS_PUSH register bit definition for PSR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add TRANS_PUSH register bit LNL_TRANS_PUSH_PSR_PR_EN definition for PSR usage. v2: add bspec reference Bspec: 69984 Signed-off-by: Jouni Högander Reviewed-by: Ankit Nautiyal Link: https://patch.msgid.link/20260127124120.1069026-2-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_vrr_regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h index 427ada0d3973..9d4d6573a149 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -165,6 +165,7 @@ #define TRANS_PUSH(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_PUSH_A) #define TRANS_PUSH_EN REG_BIT(31) #define TRANS_PUSH_SEND REG_BIT(30) +#define LNL_TRANS_PUSH_PSR_PR_EN REG_BIT(16) #define _TRANS_VRR_VSYNC_A 0x60078 #define TRANS_VRR_VSYNC(display, trans) _MMIO_TRANS2((display), (trans), _TRANS_VRR_VSYNC_A)