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rtw-next patches for v6.10
Some fixes and changes of capabilities detailed in following:
rtl8xxxu:
* enable MFP support
rtlwifi:
* some cleanups
rtw88:
* disable unsupported interface type of mesh point for all chips, and only
support station mode for SDIO chips.
rtw89:
* fixes of 8852b, 8852c and 8922a
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Merge tag 'rtw-next-2024-04-04' of https://github.com/pkshih/rtw
rtw-next patches for v6.10
Some fixes and changes of capabilities detailed in following:
rtl8xxxu:
* enable MFP support
rtlwifi:
* some cleanups
rtw88:
* disable unsupported interface type of mesh point for all chips, and only
support station mode for SDIO chips.
rtw89:
* fixes of 8852b, 8852c and 8922a
This commit is contained in:
Kalle Valo
commit
132c2a1cf7
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@ -6473,7 +6473,9 @@ int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
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rx_status->mactime = rx_desc->tsfl;
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rx_status->flag |= RX_FLAG_MACTIME_START;
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if (!rx_desc->swdec)
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if (!rx_desc->swdec &&
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!(_ieee80211_is_robust_mgmt_frame(hdr) &&
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ieee80211_has_protected(hdr->frame_control)))
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rx_status->flag |= RX_FLAG_DECRYPTED;
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if (rx_desc->crc32)
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rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
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@ -6578,7 +6580,9 @@ int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
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rx_status->mactime = rx_desc->tsfl;
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rx_status->flag |= RX_FLAG_MACTIME_START;
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if (!rx_desc->swdec)
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if (!rx_desc->swdec &&
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!(_ieee80211_is_robust_mgmt_frame(hdr) &&
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ieee80211_has_protected(hdr->frame_control)))
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rx_status->flag |= RX_FLAG_DECRYPTED;
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if (rx_desc->crc32)
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rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
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@ -7998,6 +8002,7 @@ static int rtl8xxxu_probe(struct usb_interface *interface,
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ieee80211_hw_set(hw, HAS_RATE_CONTROL);
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ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
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ieee80211_hw_set(hw, AMPDU_AGGREGATION);
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ieee80211_hw_set(hw, MFP_CAPABLE);
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wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
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@ -489,7 +489,6 @@ static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
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}
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static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
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bool wmm_enable,
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u8 out_ep_num,
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u8 queue_sel)
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{
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@ -505,66 +504,39 @@ static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
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u8 value8;
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u32 txqpagenum, txqpageunit, txqremaininpage;
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if (!wmm_enable) {
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numpubq = (ischipn) ? CHIP_B_PAGE_NUM_PUBQ :
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CHIP_A_PAGE_NUM_PUBQ;
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txqpagenum = TX_TOTAL_PAGE_NUMBER - numpubq;
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numpubq = (ischipn) ? CHIP_B_PAGE_NUM_PUBQ :
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CHIP_A_PAGE_NUM_PUBQ;
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txqpagenum = TX_TOTAL_PAGE_NUMBER - numpubq;
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txqpageunit = txqpagenum / outepnum;
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txqremaininpage = txqpagenum % outepnum;
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if (queue_sel & TX_SELE_HQ)
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numhq = txqpageunit;
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if (queue_sel & TX_SELE_LQ)
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numlq = txqpageunit;
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/* HIGH priority queue always present in the configuration of
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* 2 out-ep. Remainder pages have assigned to High queue */
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if (outepnum > 1 && txqremaininpage)
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numhq += txqremaininpage;
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/* NOTE: This step done before writing REG_RQPN. */
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if (ischipn) {
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if (queue_sel & TX_SELE_NQ)
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numnq = txqpageunit;
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value8 = (u8)_NPQ(numnq);
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rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
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}
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} else {
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/* for WMM ,number of out-ep must more than or equal to 2! */
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numpubq = ischipn ? WMM_CHIP_B_PAGE_NUM_PUBQ :
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WMM_CHIP_A_PAGE_NUM_PUBQ;
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if (queue_sel & TX_SELE_HQ) {
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numhq = ischipn ? WMM_CHIP_B_PAGE_NUM_HPQ :
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WMM_CHIP_A_PAGE_NUM_HPQ;
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}
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if (queue_sel & TX_SELE_LQ) {
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numlq = ischipn ? WMM_CHIP_B_PAGE_NUM_LPQ :
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WMM_CHIP_A_PAGE_NUM_LPQ;
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}
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/* NOTE: This step done before writing REG_RQPN. */
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if (ischipn) {
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if (queue_sel & TX_SELE_NQ)
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numnq = WMM_CHIP_B_PAGE_NUM_NPQ;
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value8 = (u8)_NPQ(numnq);
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rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
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}
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txqpageunit = txqpagenum / outepnum;
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txqremaininpage = txqpagenum % outepnum;
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if (queue_sel & TX_SELE_HQ)
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numhq = txqpageunit;
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if (queue_sel & TX_SELE_LQ)
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numlq = txqpageunit;
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/* HIGH priority queue always present in the configuration of
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* 2 out-ep. Remainder pages have assigned to High queue.
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*/
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if (outepnum > 1 && txqremaininpage)
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numhq += txqremaininpage;
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/* NOTE: This step done before writing REG_RQPN. */
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if (ischipn) {
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if (queue_sel & TX_SELE_NQ)
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numnq = txqpageunit;
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value8 = (u8)_NPQ(numnq);
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rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
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}
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/* TX DMA */
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value32 = _HPQ(numhq) | _LPQ(numlq) | _PUBQ(numpubq) | LD_RQPN;
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rtl_write_dword(rtlpriv, REG_RQPN, value32);
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}
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static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
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static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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u8 txpktbuf_bndy;
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u8 txpktbuf_bndy = TX_PAGE_BOUNDARY;
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u8 value8;
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if (!wmm_enable)
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txpktbuf_bndy = TX_PAGE_BOUNDARY;
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else /* for WMM */
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txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
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? WMM_CHIP_B_TX_PAGE_BOUNDARY
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: WMM_CHIP_A_TX_PAGE_BOUNDARY;
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rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
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rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
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rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
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@ -589,7 +561,6 @@ static void _rtl92c_init_chipn_reg_priority(struct ieee80211_hw *hw, u16 beq,
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}
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static void _rtl92cu_init_chipn_one_out_ep_priority(struct ieee80211_hw *hw,
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bool wmm_enable,
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u8 queue_sel)
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{
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u16 value;
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@ -614,7 +585,6 @@ static void _rtl92cu_init_chipn_one_out_ep_priority(struct ieee80211_hw *hw,
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}
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static void _rtl92cu_init_chipn_two_out_ep_priority(struct ieee80211_hw *hw,
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bool wmm_enable,
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u8 queue_sel)
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{
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u16 beq, bkq, viq, voq, mgtq, hiq;
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@ -638,67 +608,47 @@ static void _rtl92cu_init_chipn_two_out_ep_priority(struct ieee80211_hw *hw,
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valuelow = QUEUE_NORMAL;
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break;
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}
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if (!wmm_enable) {
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beq = valuelow;
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bkq = valuelow;
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viq = valuehi;
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voq = valuehi;
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mgtq = valuehi;
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hiq = valuehi;
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} else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
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beq = valuehi;
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bkq = valuelow;
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viq = valuelow;
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voq = valuehi;
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mgtq = valuehi;
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hiq = valuehi;
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}
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beq = valuelow;
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bkq = valuelow;
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viq = valuehi;
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voq = valuehi;
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mgtq = valuehi;
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hiq = valuehi;
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_rtl92c_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq);
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pr_info("Tx queue select: 0x%02x\n", queue_sel);
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}
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static void _rtl92cu_init_chipn_three_out_ep_priority(struct ieee80211_hw *hw,
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bool wmm_enable,
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u8 queue_sel)
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{
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u16 beq, bkq, viq, voq, mgtq, hiq;
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if (!wmm_enable) { /* typical setting */
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beq = QUEUE_LOW;
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bkq = QUEUE_LOW;
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viq = QUEUE_NORMAL;
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voq = QUEUE_HIGH;
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mgtq = QUEUE_HIGH;
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hiq = QUEUE_HIGH;
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} else { /* for WMM */
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beq = QUEUE_LOW;
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bkq = QUEUE_NORMAL;
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viq = QUEUE_NORMAL;
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voq = QUEUE_HIGH;
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mgtq = QUEUE_HIGH;
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hiq = QUEUE_HIGH;
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}
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beq = QUEUE_LOW;
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bkq = QUEUE_LOW;
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viq = QUEUE_NORMAL;
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voq = QUEUE_HIGH;
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mgtq = QUEUE_HIGH;
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hiq = QUEUE_HIGH;
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_rtl92c_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq);
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pr_info("Tx queue select :0x%02x..\n", queue_sel);
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}
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static void _rtl92cu_init_chipn_queue_priority(struct ieee80211_hw *hw,
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bool wmm_enable,
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u8 out_ep_num,
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u8 queue_sel)
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{
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switch (out_ep_num) {
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case 1:
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_rtl92cu_init_chipn_one_out_ep_priority(hw, wmm_enable,
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queue_sel);
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_rtl92cu_init_chipn_one_out_ep_priority(hw, queue_sel);
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break;
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case 2:
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_rtl92cu_init_chipn_two_out_ep_priority(hw, wmm_enable,
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queue_sel);
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_rtl92cu_init_chipn_two_out_ep_priority(hw, queue_sel);
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break;
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case 3:
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_rtl92cu_init_chipn_three_out_ep_priority(hw, wmm_enable,
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queue_sel);
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_rtl92cu_init_chipn_three_out_ep_priority(hw, queue_sel);
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break;
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default:
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WARN_ON(1); /* Shall not reach here! */
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@ -707,7 +657,6 @@ static void _rtl92cu_init_chipn_queue_priority(struct ieee80211_hw *hw,
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}
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static void _rtl92cu_init_chipt_queue_priority(struct ieee80211_hw *hw,
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bool wmm_enable,
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u8 out_ep_num,
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u8 queue_sel)
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{
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@ -716,12 +665,7 @@ static void _rtl92cu_init_chipt_queue_priority(struct ieee80211_hw *hw,
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switch (out_ep_num) {
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case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
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if (!wmm_enable) /* typical setting */
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hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
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HQSEL_HIQ;
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else /* for WMM */
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hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
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HQSEL_HIQ;
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hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ | HQSEL_HIQ;
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break;
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case 1:
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if (TX_SELE_LQ == queue_sel) {
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|
|
@ -742,18 +686,15 @@ static void _rtl92cu_init_chipt_queue_priority(struct ieee80211_hw *hw,
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}
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static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
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bool wmm_enable,
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u8 out_ep_num,
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u8 queue_sel)
|
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{
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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|
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if (IS_NORMAL_CHIP(rtlhal->version))
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_rtl92cu_init_chipn_queue_priority(hw, wmm_enable, out_ep_num,
|
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queue_sel);
|
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_rtl92cu_init_chipn_queue_priority(hw, out_ep_num, queue_sel);
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else
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_rtl92cu_init_chipt_queue_priority(hw, wmm_enable, out_ep_num,
|
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queue_sel);
|
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_rtl92cu_init_chipt_queue_priority(hw, out_ep_num, queue_sel);
|
||||
}
|
||||
|
||||
static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
|
||||
|
|
@ -810,8 +751,7 @@ static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
|
|||
struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
|
||||
struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
|
||||
int err = 0;
|
||||
u32 boundary = 0;
|
||||
u8 wmm_enable = false; /* TODO */
|
||||
u32 boundary = TX_PAGE_BOUNDARY;
|
||||
u8 out_ep_nums = rtlusb->out_ep_nums;
|
||||
u8 queue_sel = rtlusb->out_queue_sel;
|
||||
|
||||
|
|
@ -821,22 +761,13 @@ static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
|
|||
pr_err("Failed to init power on!\n");
|
||||
return err;
|
||||
}
|
||||
if (!wmm_enable) {
|
||||
boundary = TX_PAGE_BOUNDARY;
|
||||
} else { /* for WMM */
|
||||
boundary = (IS_NORMAL_CHIP(rtlhal->version))
|
||||
? WMM_CHIP_B_TX_PAGE_BOUNDARY
|
||||
: WMM_CHIP_A_TX_PAGE_BOUNDARY;
|
||||
}
|
||||
if (!rtl92c_init_llt_table(hw, boundary)) {
|
||||
pr_err("Failed to init LLT Table!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
_rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
|
||||
queue_sel);
|
||||
_rtl92c_init_trx_buffer(hw, wmm_enable);
|
||||
_rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
|
||||
queue_sel);
|
||||
_rtl92cu_init_queue_reserved_page(hw, out_ep_nums, queue_sel);
|
||||
_rtl92c_init_trx_buffer(hw);
|
||||
_rtl92cu_init_queue_priority(hw, out_ep_nums, queue_sel);
|
||||
/* Get Rx PHY status in order to report RSSI and others. */
|
||||
rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
|
||||
rtl92c_init_interrupt(hw);
|
||||
|
|
@ -1553,7 +1484,6 @@ void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
|
|||
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
|
||||
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
|
||||
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
|
||||
enum wireless_mode wirelessmode = mac->mode;
|
||||
u8 idx = 0;
|
||||
|
||||
switch (variable) {
|
||||
|
|
@ -1605,36 +1535,15 @@ void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
|
|||
}
|
||||
case HW_VAR_SLOT_TIME:{
|
||||
u8 e_aci;
|
||||
u8 QOS_MODE = 1;
|
||||
|
||||
rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
|
||||
rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
|
||||
"HW_VAR_SLOT_TIME %x\n", val[0]);
|
||||
if (QOS_MODE) {
|
||||
for (e_aci = 0; e_aci < AC_MAX; e_aci++)
|
||||
rtlpriv->cfg->ops->set_hw_reg(hw,
|
||||
HW_VAR_AC_PARAM,
|
||||
&e_aci);
|
||||
} else {
|
||||
u8 sifstime = 0;
|
||||
u8 u1baifs;
|
||||
|
||||
if (IS_WIRELESS_MODE_A(wirelessmode) ||
|
||||
IS_WIRELESS_MODE_N_24G(wirelessmode) ||
|
||||
IS_WIRELESS_MODE_N_5G(wirelessmode))
|
||||
sifstime = 16;
|
||||
else
|
||||
sifstime = 10;
|
||||
u1baifs = sifstime + (2 * val[0]);
|
||||
rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
|
||||
u1baifs);
|
||||
rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
|
||||
u1baifs);
|
||||
rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
|
||||
u1baifs);
|
||||
rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
|
||||
u1baifs);
|
||||
}
|
||||
for (e_aci = 0; e_aci < AC_MAX; e_aci++)
|
||||
rtlpriv->cfg->ops->set_hw_reg(hw,
|
||||
HW_VAR_AC_PARAM,
|
||||
&e_aci);
|
||||
break;
|
||||
}
|
||||
case HW_VAR_ACK_PREAMBLE:{
|
||||
|
|
|
|||
|
|
@ -3937,7 +3937,9 @@ void rtw_coex_display_coex_info(struct rtw_dev *rtwdev, struct seq_file *m)
|
|||
lte_coex = rtw_coex_read_indirect_reg(rtwdev, 0x38);
|
||||
bt_coex = rtw_coex_read_indirect_reg(rtwdev, 0x54);
|
||||
|
||||
if (!coex_stat->bt_disabled && !coex_stat->bt_mailbox_reply) {
|
||||
if (!coex_stat->wl_under_ips &&
|
||||
(!coex_stat->wl_under_lps || coex_stat->wl_force_lps_ctrl) &&
|
||||
!coex_stat->bt_disabled && !coex_stat->bt_mailbox_reply) {
|
||||
rtw_coex_get_bt_supported_version(rtwdev,
|
||||
&coex_stat->bt_supported_version);
|
||||
rtw_coex_get_bt_patch_version(rtwdev, &coex_stat->patch_ver);
|
||||
|
|
|
|||
|
|
@ -783,12 +783,18 @@ void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect,
|
|||
static const u8 rssi_min = 0, rssi_max = 100, rssi_offset = 100;
|
||||
struct rtw_sta_info *si =
|
||||
sta ? (struct rtw_sta_info *)sta->drv_priv : NULL;
|
||||
s32 threshold = bss_conf->cqm_rssi_thold + rssi_offset;
|
||||
s32 thold = RTW_DEFAULT_CQM_THOLD;
|
||||
u32 hyst = RTW_DEFAULT_CQM_HYST;
|
||||
u8 h2c_pkt[H2C_PKT_SIZE] = {0};
|
||||
|
||||
if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_BCN_FILTER))
|
||||
return;
|
||||
|
||||
if (bss_conf->cqm_rssi_thold)
|
||||
thold = bss_conf->cqm_rssi_thold;
|
||||
if (bss_conf->cqm_rssi_hyst)
|
||||
hyst = bss_conf->cqm_rssi_hyst;
|
||||
|
||||
if (!connect) {
|
||||
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_BCN_FILTER_OFFLOAD_P1);
|
||||
SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, connect);
|
||||
|
|
@ -805,15 +811,15 @@ void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect,
|
|||
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
|
||||
|
||||
memset(h2c_pkt, 0, sizeof(h2c_pkt));
|
||||
threshold = clamp_t(s32, threshold, rssi_min, rssi_max);
|
||||
thold = clamp_t(s32, thold + rssi_offset, rssi_min, rssi_max);
|
||||
SET_H2C_CMD_ID_CLASS(h2c_pkt, H2C_CMD_BCN_FILTER_OFFLOAD_P1);
|
||||
SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, connect);
|
||||
SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt,
|
||||
BCN_FILTER_OFFLOAD_MODE_DEFAULT);
|
||||
SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, (u8)threshold);
|
||||
SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, thold);
|
||||
SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, BCN_LOSS_CNT);
|
||||
SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, si->mac_id);
|
||||
SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, bss_conf->cqm_rssi_hyst);
|
||||
SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, hyst);
|
||||
SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, bss_conf->beacon_int);
|
||||
rtw_fw_send_h2c_command(rtwdev, h2c_pkt);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,6 +29,8 @@
|
|||
#define BCN_FILTER_CONNECTION_LOSS 1
|
||||
#define BCN_FILTER_CONNECTED 2
|
||||
#define BCN_FILTER_NOTIFY_BEACON_LOSS 3
|
||||
#define RTW_DEFAULT_CQM_THOLD -70
|
||||
#define RTW_DEFAULT_CQM_HYST 4
|
||||
|
||||
#define SCAN_NOTIFY_TIMEOUT msecs_to_jiffies(10)
|
||||
|
||||
|
|
|
|||
|
|
@ -386,6 +386,8 @@ static void rtw_ops_bss_info_changed(struct ieee80211_hw *hw,
|
|||
rtw_coex_media_status_notify(rtwdev, vif->cfg.assoc);
|
||||
if (rtw_bf_support)
|
||||
rtw_bf_assoc(rtwdev, vif, conf);
|
||||
|
||||
rtw_fw_beacon_filter_config(rtwdev, true, vif);
|
||||
} else {
|
||||
rtw_leave_lps(rtwdev);
|
||||
rtw_bf_disassoc(rtwdev, vif, conf);
|
||||
|
|
|
|||
|
|
@ -227,9 +227,6 @@ static void rtw_watch_dog_work(struct work_struct *work)
|
|||
else
|
||||
clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
|
||||
|
||||
rtw_coex_wl_status_check(rtwdev);
|
||||
rtw_coex_query_bt_hid_list(rtwdev);
|
||||
|
||||
if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
|
||||
rtw_coex_wl_status_change_notify(rtwdev, 0);
|
||||
|
||||
|
|
@ -257,6 +254,8 @@ static void rtw_watch_dog_work(struct work_struct *work)
|
|||
|
||||
/* make sure BB/RF is working for dynamic mech */
|
||||
rtw_leave_lps(rtwdev);
|
||||
rtw_coex_wl_status_check(rtwdev);
|
||||
rtw_coex_query_bt_hid_list(rtwdev);
|
||||
|
||||
rtw_phy_dynamic_mechanism(rtwdev);
|
||||
|
||||
|
|
@ -2204,6 +2203,7 @@ EXPORT_SYMBOL(rtw_core_deinit);
|
|||
|
||||
int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
|
||||
{
|
||||
bool sta_mode_only = rtwdev->hci.type == RTW_HCI_TYPE_SDIO;
|
||||
struct rtw_hal *hal = &rtwdev->hal;
|
||||
int max_tx_headroom = 0;
|
||||
int ret;
|
||||
|
|
@ -2232,10 +2232,12 @@ int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
|
|||
ieee80211_hw_set(hw, TX_AMSDU);
|
||||
ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
|
||||
|
||||
hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
|
||||
BIT(NL80211_IFTYPE_AP) |
|
||||
BIT(NL80211_IFTYPE_ADHOC) |
|
||||
BIT(NL80211_IFTYPE_MESH_POINT);
|
||||
if (sta_mode_only)
|
||||
hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
|
||||
else
|
||||
hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
|
||||
BIT(NL80211_IFTYPE_AP) |
|
||||
BIT(NL80211_IFTYPE_ADHOC);
|
||||
hw->wiphy->available_antennas_tx = hal->antenna_tx;
|
||||
hw->wiphy->available_antennas_rx = hal->antenna_rx;
|
||||
|
||||
|
|
@ -2246,7 +2248,7 @@ int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
|
|||
hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS;
|
||||
hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev);
|
||||
|
||||
if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C) {
|
||||
if (!sta_mode_only && rtwdev->chip->id == RTW_CHIP_TYPE_8822C) {
|
||||
hw->wiphy->iface_combinations = rtw_iface_combs;
|
||||
hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4069,6 +4069,24 @@ void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg eve
|
|||
}
|
||||
}
|
||||
|
||||
void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks)
|
||||
{
|
||||
const struct dmi_system_id *match;
|
||||
enum rtw89_quirks quirk;
|
||||
|
||||
if (!quirks)
|
||||
return;
|
||||
|
||||
for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) {
|
||||
quirk = (uintptr_t)match->driver_data;
|
||||
if (quirk >= NUM_OF_RTW89_QUIRKS)
|
||||
continue;
|
||||
|
||||
set_bit(quirk, rtwdev->quirks);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(rtw89_check_quirks);
|
||||
|
||||
int rtw89_core_start(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
int ret;
|
||||
|
|
@ -4486,7 +4504,11 @@ static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
|
|||
|
||||
hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
|
||||
WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
|
||||
WIPHY_FLAG_AP_UAPSD | WIPHY_FLAG_SPLIT_SCAN_6GHZ;
|
||||
WIPHY_FLAG_AP_UAPSD;
|
||||
|
||||
if (!chip->support_rnr)
|
||||
hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ;
|
||||
|
||||
hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
|
||||
|
||||
hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
|
||||
#include <linux/average.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/dmi.h>
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
|
@ -3981,6 +3982,7 @@ struct rtw89_chip_info {
|
|||
u8 support_bands;
|
||||
u16 support_bandwidths;
|
||||
bool support_unii4;
|
||||
bool support_rnr;
|
||||
bool ul_tb_waveform_ctrl;
|
||||
bool ul_tb_pwr_diff;
|
||||
bool hw_sec_hdr;
|
||||
|
|
@ -4079,6 +4081,7 @@ union rtw89_bus_info {
|
|||
|
||||
struct rtw89_driver_info {
|
||||
const struct rtw89_chip_info *chip;
|
||||
const struct dmi_system_id *quirks;
|
||||
union rtw89_bus_info bus;
|
||||
};
|
||||
|
||||
|
|
@ -4426,6 +4429,12 @@ enum rtw89_flags {
|
|||
NUM_OF_RTW89_FLAGS,
|
||||
};
|
||||
|
||||
enum rtw89_quirks {
|
||||
RTW89_QUIRK_PCI_BER,
|
||||
|
||||
NUM_OF_RTW89_QUIRKS,
|
||||
};
|
||||
|
||||
enum rtw89_pkt_drop_sel {
|
||||
RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
|
||||
RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
|
||||
|
|
@ -5186,6 +5195,7 @@ struct rtw89_dev {
|
|||
DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
|
||||
DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
|
||||
DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
|
||||
DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS);
|
||||
|
||||
struct rtw89_phy_stat phystat;
|
||||
struct rtw89_rfk_wait_info rfk_wait;
|
||||
|
|
@ -6231,6 +6241,7 @@ int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
|
|||
void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
|
||||
struct ieee80211_sta *sta,
|
||||
struct cfg80211_tid_config *tid_config);
|
||||
void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
|
||||
int rtw89_core_init(struct rtw89_dev *rtwdev);
|
||||
void rtw89_core_deinit(struct rtw89_dev *rtwdev);
|
||||
int rtw89_core_register(struct rtw89_dev *rtwdev);
|
||||
|
|
|
|||
|
|
@ -637,6 +637,7 @@ static const struct __fw_feat_cfg fw_feat_tbl[] = {
|
|||
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 30, 0, CRASH_TRIGGER),
|
||||
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 11, 0, MACID_PAUSE_SLEEP),
|
||||
__CFG_FW_FEAT(RTL8922A, ge, 0, 34, 35, 0, SCAN_OFFLOAD),
|
||||
__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 12, 0, BEACON_FILTER),
|
||||
};
|
||||
|
||||
static void rtw89_fw_iterate_feature_cfg(struct rtw89_fw_info *fw,
|
||||
|
|
@ -1349,13 +1350,12 @@ static void rtw89_fw_prog_cnt_dump(struct rtw89_dev *rtwdev)
|
|||
static void rtw89_fw_dl_fail_dump(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
u32 val32;
|
||||
u16 val16;
|
||||
|
||||
val32 = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);
|
||||
rtw89_err(rtwdev, "[ERR]fwdl 0x1E0 = 0x%x\n", val32);
|
||||
|
||||
val16 = rtw89_read16(rtwdev, R_AX_BOOT_DBG + 2);
|
||||
rtw89_err(rtwdev, "[ERR]fwdl 0x83F2 = 0x%x\n", val16);
|
||||
val32 = rtw89_read32(rtwdev, R_AX_BOOT_DBG);
|
||||
rtw89_err(rtwdev, "[ERR]fwdl 0x83F0 = 0x%x\n", val32);
|
||||
|
||||
rtw89_fw_prog_cnt_dump(rtwdev);
|
||||
}
|
||||
|
|
@ -1394,8 +1394,9 @@ static int rtw89_fw_download_suit(struct rtw89_dev *rtwdev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
|
||||
bool include_bb)
|
||||
static
|
||||
int __rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
|
||||
bool include_bb)
|
||||
{
|
||||
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
|
||||
struct rtw89_fw_info *fw_info = &rtwdev->fw;
|
||||
|
|
@ -1433,7 +1434,7 @@ int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
|
|||
ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE);
|
||||
if (ret) {
|
||||
rtw89_warn(rtwdev, "download firmware fail\n");
|
||||
return ret;
|
||||
goto fwdl_err;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -1443,6 +1444,21 @@ int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
|
|||
return ret;
|
||||
}
|
||||
|
||||
int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
|
||||
bool include_bb)
|
||||
{
|
||||
int retry;
|
||||
int ret;
|
||||
|
||||
for (retry = 0; retry < 5; retry++) {
|
||||
ret = __rtw89_fw_download(rtwdev, type, include_bb);
|
||||
if (!ret)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
struct rtw89_fw_info *fw = &rtwdev->fw;
|
||||
|
|
@ -4692,6 +4708,7 @@ int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
|
|||
struct rtw89_h2c_scanofld_be_macc_role *macc_role;
|
||||
struct rtw89_chan *op = &scan_info->op_chan;
|
||||
struct rtw89_h2c_scanofld_be_opch *opch;
|
||||
struct rtw89_pktofld_info *pkt_info;
|
||||
struct rtw89_h2c_scanofld_be *h2c;
|
||||
struct sk_buff *skb;
|
||||
u8 macc_role_size = sizeof(*macc_role) * option->num_macc_role;
|
||||
|
|
@ -4716,6 +4733,16 @@ int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
|
|||
h2c = (struct rtw89_h2c_scanofld_be *)skb->data;
|
||||
ptr = skb->data;
|
||||
|
||||
memset(probe_id, RTW89_SCANOFLD_PKT_NONE, sizeof(probe_id));
|
||||
|
||||
list_for_each_entry(pkt_info, &scan_info->pkt_list[NL80211_BAND_6GHZ], list) {
|
||||
if (pkt_info->wildcard_6ghz) {
|
||||
/* Provide wildcard as template */
|
||||
probe_id[NL80211_BAND_6GHZ] = pkt_info->id;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
h2c->w0 = le32_encode_bits(option->operation, RTW89_H2C_SCANOFLD_BE_W0_OP) |
|
||||
le32_encode_bits(option->scan_mode,
|
||||
RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE) |
|
||||
|
|
@ -5553,6 +5580,7 @@ static bool rtw89_is_6ghz_wildcard_probe_req(struct rtw89_dev *rtwdev,
|
|||
info->ssid_len = req->ssids[ssid_idx].ssid_len;
|
||||
return false;
|
||||
} else {
|
||||
info->wildcard_6ghz = true;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
|
@ -5587,12 +5615,8 @@ static int rtw89_append_probe_req_ie(struct rtw89_dev *rtwdev,
|
|||
goto out;
|
||||
}
|
||||
|
||||
if (rtw89_is_6ghz_wildcard_probe_req(rtwdev, rtwvif, info, band,
|
||||
ssid_idx)) {
|
||||
kfree_skb(new);
|
||||
kfree(info);
|
||||
goto out;
|
||||
}
|
||||
rtw89_is_6ghz_wildcard_probe_req(rtwdev, rtwvif, info, band,
|
||||
ssid_idx);
|
||||
|
||||
ret = rtw89_fw_h2c_add_pkt_offload(rtwdev, &info->id, new);
|
||||
if (ret) {
|
||||
|
|
@ -5750,6 +5774,10 @@ static void rtw89_hw_scan_add_chan(struct rtw89_dev *rtwdev, int chan_type,
|
|||
continue;
|
||||
else if (info->channel_6ghz && probe_count != 0)
|
||||
ch_info->period += RTW89_CHANNEL_TIME_6G;
|
||||
|
||||
if (info->wildcard_6ghz)
|
||||
continue;
|
||||
|
||||
ch_info->pkt_id[probe_count++] = info->id;
|
||||
if (probe_count >= RTW89_SCANOFLD_MAX_SSID)
|
||||
break;
|
||||
|
|
@ -5804,6 +5832,10 @@ static void rtw89_hw_scan_add_chan_be(struct rtw89_dev *rtwdev, int chan_type,
|
|||
if (info->channel_6ghz &&
|
||||
ch_info->pri_ch != info->channel_6ghz)
|
||||
continue;
|
||||
|
||||
if (info->wildcard_6ghz)
|
||||
continue;
|
||||
|
||||
ch_info->pkt_id[probe_count++] = info->id;
|
||||
if (probe_count >= RTW89_SCANOFLD_MAX_SSID)
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -340,8 +340,9 @@ struct rtw89_mac_chinfo_be {
|
|||
struct rtw89_pktofld_info {
|
||||
struct list_head list;
|
||||
u8 id;
|
||||
bool wildcard_6ghz;
|
||||
|
||||
/* Below fields are for 6 GHz RNR use only */
|
||||
/* Below fields are for WiFi 6 chips 6 GHz RNR use only */
|
||||
u8 ssid[IEEE80211_MAX_SSID_LEN];
|
||||
u8 ssid_len;
|
||||
u8 bssid[ETH_ALEN];
|
||||
|
|
@ -2981,6 +2982,7 @@ struct rtw89_h2c_scanofld_be {
|
|||
__le32 w5;
|
||||
__le32 w6;
|
||||
__le32 w7;
|
||||
__le32 w8;
|
||||
struct rtw89_h2c_scanofld_be_macc_role role[];
|
||||
} __packed;
|
||||
|
||||
|
|
|
|||
|
|
@ -19,6 +19,31 @@ MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support");
|
|||
MODULE_PARM_DESC(disable_aspm_l1, "Set Y to disable PCI ASPM L1 support");
|
||||
MODULE_PARM_DESC(disable_aspm_l1ss, "Set Y to disable PCI L1SS support");
|
||||
|
||||
static int rtw89_pci_get_phy_offset_by_link_speed(struct rtw89_dev *rtwdev,
|
||||
u32 *phy_offset)
|
||||
{
|
||||
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
|
||||
struct pci_dev *pdev = rtwpci->pdev;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
ret = pci_read_config_dword(pdev, RTW89_PCIE_L1_STS_V1, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val = u32_get_bits(val, RTW89_BCFG_LINK_SPEED_MASK);
|
||||
if (val == RTW89_PCIE_GEN1_SPEED) {
|
||||
*phy_offset = R_RAC_DIRECT_OFFSET_G1;
|
||||
} else if (val == RTW89_PCIE_GEN2_SPEED) {
|
||||
*phy_offset = R_RAC_DIRECT_OFFSET_G2;
|
||||
} else {
|
||||
rtw89_warn(rtwdev, "Unknown PCI link speed %d\n", val);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtw89_pci_rst_bdram_ax(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
u32 val;
|
||||
|
|
@ -2298,6 +2323,68 @@ static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void rtw89_pci_disable_eq(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
u16 g1_oobs, g2_oobs;
|
||||
u32 backup_aspm;
|
||||
u32 phy_offset;
|
||||
u16 oobs_val;
|
||||
u16 val16;
|
||||
int ret;
|
||||
|
||||
if (rtwdev->chip->chip_id != RTL8852C)
|
||||
return;
|
||||
|
||||
backup_aspm = rtw89_read32(rtwdev, R_AX_PCIE_MIX_CFG_V1);
|
||||
rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_ASPM_CTRL_MASK);
|
||||
|
||||
g1_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_G1 +
|
||||
RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL);
|
||||
g2_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_G2 +
|
||||
RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL);
|
||||
if (g1_oobs && g2_oobs)
|
||||
goto out;
|
||||
|
||||
ret = rtw89_pci_get_phy_offset_by_link_speed(rtwdev, &phy_offset);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT, BAC_RX_TEST_EN);
|
||||
rtw89_write16(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT, ADDR_SEL_PINOUT_DIS_VAL);
|
||||
rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, B_PCIE_BIT_RD_SEL);
|
||||
|
||||
val16 = rtw89_read16_mask(rtwdev, phy_offset + RAC_ANA1F * RAC_MULT,
|
||||
OOBS_LEVEL_MASK);
|
||||
oobs_val = u16_encode_bits(val16, OOBS_SEN_MASK);
|
||||
|
||||
rtw89_write16(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA03 * RAC_MULT, oobs_val);
|
||||
rtw89_write16_set(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA09 * RAC_MULT,
|
||||
BAC_OOBS_SEL);
|
||||
|
||||
rtw89_write16(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA03 * RAC_MULT, oobs_val);
|
||||
rtw89_write16_set(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA09 * RAC_MULT,
|
||||
BAC_OOBS_SEL);
|
||||
|
||||
out:
|
||||
rtw89_write32(rtwdev, R_AX_PCIE_MIX_CFG_V1, backup_aspm);
|
||||
}
|
||||
|
||||
static void rtw89_pci_ber(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
u32 phy_offset;
|
||||
|
||||
if (!test_bit(RTW89_QUIRK_PCI_BER, rtwdev->quirks))
|
||||
return;
|
||||
|
||||
phy_offset = R_RAC_DIRECT_OFFSET_G1;
|
||||
rtw89_write16(rtwdev, phy_offset + RAC_ANA1E * RAC_MULT, RAC_ANA1E_G1_VAL);
|
||||
rtw89_write16(rtwdev, phy_offset + RAC_ANA2E * RAC_MULT, RAC_ANA2E_VAL);
|
||||
|
||||
phy_offset = R_RAC_DIRECT_OFFSET_G2;
|
||||
rtw89_write16(rtwdev, phy_offset + RAC_ANA1E * RAC_MULT, RAC_ANA1E_G2_VAL);
|
||||
rtw89_write16(rtwdev, phy_offset + RAC_ANA2E * RAC_MULT, RAC_ANA2E_VAL);
|
||||
}
|
||||
|
||||
static void rtw89_pci_rxdma_prefth(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
if (rtwdev->chip->chip_id != RTL8852A)
|
||||
|
|
@ -2695,6 +2782,8 @@ static int rtw89_pci_ops_mac_pre_init_ax(struct rtw89_dev *rtwdev)
|
|||
const struct rtw89_pci_info *info = rtwdev->pci_info;
|
||||
int ret;
|
||||
|
||||
rtw89_pci_disable_eq(rtwdev);
|
||||
rtw89_pci_ber(rtwdev);
|
||||
rtw89_pci_rxdma_prefth(rtwdev);
|
||||
rtw89_pci_l1off_pwroff(rtwdev);
|
||||
rtw89_pci_deglitch_setting(rtwdev);
|
||||
|
|
@ -4171,6 +4260,8 @@ int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
rtwdev->hci.rpwm_addr = pci_info->rpwm_addr;
|
||||
rtwdev->hci.cpwm_addr = pci_info->cpwm_addr;
|
||||
|
||||
rtw89_check_quirks(rtwdev, info->quirks);
|
||||
|
||||
SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev);
|
||||
|
||||
ret = rtw89_core_init(rtwdev);
|
||||
|
|
|
|||
|
|
@ -12,11 +12,18 @@
|
|||
#define MDIO_PG0_G2 2
|
||||
#define MDIO_PG1_G2 3
|
||||
#define RAC_CTRL_PPR 0x00
|
||||
#define RAC_ANA03 0x03
|
||||
#define OOBS_SEN_MASK GENMASK(5, 1)
|
||||
#define RAC_ANA09 0x09
|
||||
#define BAC_OOBS_SEL BIT(4)
|
||||
#define RAC_ANA0A 0x0A
|
||||
#define B_BAC_EQ_SEL BIT(5)
|
||||
#define RAC_ANA0C 0x0C
|
||||
#define B_PCIE_BIT_PSAVE BIT(15)
|
||||
#define RAC_ANA0D 0x0D
|
||||
#define BAC_RX_TEST_EN BIT(6)
|
||||
#define RAC_ANA10 0x10
|
||||
#define ADDR_SEL_PINOUT_DIS_VAL 0x3C4
|
||||
#define B_PCIE_BIT_PINOUT_DIS BIT(3)
|
||||
#define RAC_REG_REV2 0x1B
|
||||
#define BAC_CMU_EN_DLY_MASK GENMASK(15, 12)
|
||||
|
|
@ -26,11 +33,17 @@
|
|||
#define RAC_REG_FLD_0 0x1D
|
||||
#define BAC_AUTOK_N_MASK GENMASK(3, 2)
|
||||
#define PCIE_AUTOK_4 0x3
|
||||
#define RAC_ANA1E 0x1E
|
||||
#define RAC_ANA1E_G1_VAL 0x66EA
|
||||
#define RAC_ANA1E_G2_VAL 0x6EEA
|
||||
#define RAC_ANA1F 0x1F
|
||||
#define OOBS_LEVEL_MASK GENMASK(12, 8)
|
||||
#define RAC_ANA24 0x24
|
||||
#define B_AX_DEGLITCH GENMASK(11, 8)
|
||||
#define RAC_ANA26 0x26
|
||||
#define B_AX_RXEN GENMASK(15, 14)
|
||||
#define RAC_ANA2E 0x2E
|
||||
#define RAC_ANA2E_VAL 0xFFFE
|
||||
#define RAC_CTRL_PPR_V1 0x30
|
||||
#define B_AX_CLK_CALIB_EN BIT(12)
|
||||
#define B_AX_CALIB_EN BIT(13)
|
||||
|
|
|
|||
|
|
@ -381,6 +381,23 @@ static void rtw89_phy_bb_wrap_ftm_init(struct rtw89_dev *rtwdev,
|
|||
rtw89_write32_mask(rtwdev, addr, 0x7, 0);
|
||||
}
|
||||
|
||||
static void rtw89_phy_bb_wrap_ul_pwr(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
|
||||
u8 mac_idx;
|
||||
u32 addr;
|
||||
|
||||
if (chip_id != RTL8922A)
|
||||
return;
|
||||
|
||||
for (mac_idx = 0; mac_idx < RTW89_MAC_NUM; mac_idx++) {
|
||||
addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_RSSI_TARGET_LMT, mac_idx);
|
||||
rtw89_write32(rtwdev, addr, 0x0201FE00);
|
||||
addr = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_TH, mac_idx);
|
||||
rtw89_write32(rtwdev, addr, 0x00FFEC7E);
|
||||
}
|
||||
}
|
||||
|
||||
static void rtw89_phy_bb_wrap_init_be(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
enum rtw89_mac_idx mac_idx = RTW89_MAC_0;
|
||||
|
|
@ -391,6 +408,7 @@ static void rtw89_phy_bb_wrap_init_be(struct rtw89_dev *rtwdev)
|
|||
rtw89_phy_bb_wrap_force_cr_init(rtwdev, mac_idx);
|
||||
rtw89_phy_bb_wrap_ftm_init(rtwdev, mac_idx);
|
||||
rtw89_phy_bb_wrap_tpu_set_all(rtwdev, mac_idx);
|
||||
rtw89_phy_bb_wrap_ul_pwr(rtwdev);
|
||||
}
|
||||
|
||||
static void rtw89_phy_ch_info_init_be(struct rtw89_dev *rtwdev)
|
||||
|
|
|
|||
|
|
@ -1891,7 +1891,6 @@
|
|||
B_AX_B0_IMR_ERR_USRCTL_NOINIT | \
|
||||
B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \
|
||||
B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \
|
||||
B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \
|
||||
B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \
|
||||
B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \
|
||||
B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \
|
||||
|
|
@ -7497,6 +7496,9 @@
|
|||
#define B_BE_PWR_BT_VAL GENMASK(8, 0)
|
||||
#define B_BE_PWR_FORCE_COEX_ON GENMASK(29, 27)
|
||||
|
||||
#define R_BE_PWR_TH 0x11A78
|
||||
#define R_BE_PWR_RSSI_TARGET_LMT 0x11A84
|
||||
|
||||
#define R_BE_PWR_OFST_SW 0x11AE8
|
||||
#define B_BE_PWR_OFST_SW_DB GENMASK(27, 24)
|
||||
|
||||
|
|
|
|||
|
|
@ -2447,6 +2447,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
|
|||
.dig_regs = &rtw8851b_dig_regs,
|
||||
.tssi_dbw_table = NULL,
|
||||
.support_chanctx_num = 0,
|
||||
.support_rnr = false,
|
||||
.support_bands = BIT(NL80211_BAND_2GHZ) |
|
||||
BIT(NL80211_BAND_5GHZ),
|
||||
.support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
|
||||
|
|
|
|||
|
|
@ -63,6 +63,7 @@ static const struct rtw89_pci_info rtw8851b_pci_info = {
|
|||
|
||||
static const struct rtw89_driver_info rtw89_8851be_info = {
|
||||
.chip = &rtw8851b_chip_info,
|
||||
.quirks = NULL,
|
||||
.bus = {
|
||||
.pci = &rtw8851b_pci_info,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -2163,6 +2163,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
|
|||
.dig_regs = &rtw8852a_dig_regs,
|
||||
.tssi_dbw_table = NULL,
|
||||
.support_chanctx_num = 1,
|
||||
.support_rnr = false,
|
||||
.support_bands = BIT(NL80211_BAND_2GHZ) |
|
||||
BIT(NL80211_BAND_5GHZ),
|
||||
.support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ static const struct rtw89_pci_info rtw8852a_pci_info = {
|
|||
|
||||
static const struct rtw89_driver_info rtw89_8852ae_info = {
|
||||
.chip = &rtw8852a_chip_info,
|
||||
.quirks = NULL,
|
||||
.bus = {
|
||||
.pci = &rtw8852a_pci_info,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -2597,6 +2597,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
|
|||
.dig_regs = &rtw8852b_dig_regs,
|
||||
.tssi_dbw_table = NULL,
|
||||
.support_chanctx_num = 0,
|
||||
.support_rnr = false,
|
||||
.support_bands = BIT(NL80211_BAND_2GHZ) |
|
||||
BIT(NL80211_BAND_5GHZ),
|
||||
.support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
|
||||
|
|
|
|||
|
|
@ -63,6 +63,7 @@ static const struct rtw89_pci_info rtw8852b_pci_info = {
|
|||
|
||||
static const struct rtw89_driver_info rtw89_8852be_info = {
|
||||
.chip = &rtw8852b_chip_info,
|
||||
.quirks = NULL,
|
||||
.bus = {
|
||||
.pci = &rtw8852b_pci_info,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -2934,6 +2934,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
|
|||
.dig_regs = &rtw8852c_dig_regs,
|
||||
.tssi_dbw_table = &rtw89_8852c_tssi_dbw_table,
|
||||
.support_chanctx_num = 2,
|
||||
.support_rnr = false,
|
||||
.support_bands = BIT(NL80211_BAND_2GHZ) |
|
||||
BIT(NL80211_BAND_5GHZ) |
|
||||
BIT(NL80211_BAND_6GHZ),
|
||||
|
|
|
|||
|
|
@ -34521,7 +34521,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][0][1][0][RTW89_FCC][48] = 72,
|
||||
[0][0][1][0][RTW89_ETSI][48] = 127,
|
||||
[0][0][1][0][RTW89_MKK][48] = 127,
|
||||
[0][0][1][0][RTW89_IC][48] = 127,
|
||||
[0][0][1][0][RTW89_IC][48] = 72,
|
||||
[0][0][1][0][RTW89_KCC][48] = 127,
|
||||
[0][0][1][0][RTW89_ACMA][48] = 127,
|
||||
[0][0][1][0][RTW89_CN][48] = 127,
|
||||
|
|
@ -34534,7 +34534,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][0][1][0][RTW89_FCC][50] = 72,
|
||||
[0][0][1][0][RTW89_ETSI][50] = 127,
|
||||
[0][0][1][0][RTW89_MKK][50] = 127,
|
||||
[0][0][1][0][RTW89_IC][50] = 127,
|
||||
[0][0][1][0][RTW89_IC][50] = 72,
|
||||
[0][0][1][0][RTW89_KCC][50] = 127,
|
||||
[0][0][1][0][RTW89_ACMA][50] = 127,
|
||||
[0][0][1][0][RTW89_CN][50] = 127,
|
||||
|
|
@ -34547,7 +34547,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][0][1][0][RTW89_FCC][52] = 72,
|
||||
[0][0][1][0][RTW89_ETSI][52] = 127,
|
||||
[0][0][1][0][RTW89_MKK][52] = 127,
|
||||
[0][0][1][0][RTW89_IC][52] = 127,
|
||||
[0][0][1][0][RTW89_IC][52] = 72,
|
||||
[0][0][1][0][RTW89_KCC][52] = 127,
|
||||
[0][0][1][0][RTW89_ACMA][52] = 127,
|
||||
[0][0][1][0][RTW89_CN][52] = 127,
|
||||
|
|
@ -34885,7 +34885,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][1][1][0][RTW89_FCC][48] = 48,
|
||||
[0][1][1][0][RTW89_ETSI][48] = 127,
|
||||
[0][1][1][0][RTW89_MKK][48] = 127,
|
||||
[0][1][1][0][RTW89_IC][48] = 127,
|
||||
[0][1][1][0][RTW89_IC][48] = 48,
|
||||
[0][1][1][0][RTW89_KCC][48] = 127,
|
||||
[0][1][1][0][RTW89_ACMA][48] = 127,
|
||||
[0][1][1][0][RTW89_CN][48] = 127,
|
||||
|
|
@ -34898,7 +34898,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][1][1][0][RTW89_FCC][50] = 48,
|
||||
[0][1][1][0][RTW89_ETSI][50] = 127,
|
||||
[0][1][1][0][RTW89_MKK][50] = 127,
|
||||
[0][1][1][0][RTW89_IC][50] = 127,
|
||||
[0][1][1][0][RTW89_IC][50] = 48,
|
||||
[0][1][1][0][RTW89_KCC][50] = 127,
|
||||
[0][1][1][0][RTW89_ACMA][50] = 127,
|
||||
[0][1][1][0][RTW89_CN][50] = 127,
|
||||
|
|
@ -34911,7 +34911,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][1][1][0][RTW89_FCC][52] = 48,
|
||||
[0][1][1][0][RTW89_ETSI][52] = 127,
|
||||
[0][1][1][0][RTW89_MKK][52] = 127,
|
||||
[0][1][1][0][RTW89_IC][52] = 127,
|
||||
[0][1][1][0][RTW89_IC][52] = 48,
|
||||
[0][1][1][0][RTW89_KCC][52] = 127,
|
||||
[0][1][1][0][RTW89_ACMA][52] = 127,
|
||||
[0][1][1][0][RTW89_CN][52] = 127,
|
||||
|
|
@ -35249,7 +35249,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][0][2][0][RTW89_FCC][48] = 72,
|
||||
[0][0][2][0][RTW89_ETSI][48] = 127,
|
||||
[0][0][2][0][RTW89_MKK][48] = 127,
|
||||
[0][0][2][0][RTW89_IC][48] = 127,
|
||||
[0][0][2][0][RTW89_IC][48] = 72,
|
||||
[0][0][2][0][RTW89_KCC][48] = 127,
|
||||
[0][0][2][0][RTW89_ACMA][48] = 127,
|
||||
[0][0][2][0][RTW89_CN][48] = 127,
|
||||
|
|
@ -35262,7 +35262,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][0][2][0][RTW89_FCC][50] = 72,
|
||||
[0][0][2][0][RTW89_ETSI][50] = 127,
|
||||
[0][0][2][0][RTW89_MKK][50] = 127,
|
||||
[0][0][2][0][RTW89_IC][50] = 127,
|
||||
[0][0][2][0][RTW89_IC][50] = 72,
|
||||
[0][0][2][0][RTW89_KCC][50] = 127,
|
||||
[0][0][2][0][RTW89_ACMA][50] = 127,
|
||||
[0][0][2][0][RTW89_CN][50] = 127,
|
||||
|
|
@ -35275,7 +35275,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][0][2][0][RTW89_FCC][52] = 72,
|
||||
[0][0][2][0][RTW89_ETSI][52] = 127,
|
||||
[0][0][2][0][RTW89_MKK][52] = 127,
|
||||
[0][0][2][0][RTW89_IC][52] = 127,
|
||||
[0][0][2][0][RTW89_IC][52] = 72,
|
||||
[0][0][2][0][RTW89_KCC][52] = 127,
|
||||
[0][0][2][0][RTW89_ACMA][52] = 127,
|
||||
[0][0][2][0][RTW89_CN][52] = 127,
|
||||
|
|
@ -35613,7 +35613,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][1][2][0][RTW89_FCC][48] = 48,
|
||||
[0][1][2][0][RTW89_ETSI][48] = 127,
|
||||
[0][1][2][0][RTW89_MKK][48] = 127,
|
||||
[0][1][2][0][RTW89_IC][48] = 127,
|
||||
[0][1][2][0][RTW89_IC][48] = 48,
|
||||
[0][1][2][0][RTW89_KCC][48] = 127,
|
||||
[0][1][2][0][RTW89_ACMA][48] = 127,
|
||||
[0][1][2][0][RTW89_CN][48] = 127,
|
||||
|
|
@ -35626,7 +35626,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][1][2][0][RTW89_FCC][50] = 50,
|
||||
[0][1][2][0][RTW89_ETSI][50] = 127,
|
||||
[0][1][2][0][RTW89_MKK][50] = 127,
|
||||
[0][1][2][0][RTW89_IC][50] = 127,
|
||||
[0][1][2][0][RTW89_IC][50] = 50,
|
||||
[0][1][2][0][RTW89_KCC][50] = 127,
|
||||
[0][1][2][0][RTW89_ACMA][50] = 127,
|
||||
[0][1][2][0][RTW89_CN][50] = 127,
|
||||
|
|
@ -35639,7 +35639,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][1][2][0][RTW89_FCC][52] = 48,
|
||||
[0][1][2][0][RTW89_ETSI][52] = 127,
|
||||
[0][1][2][0][RTW89_MKK][52] = 127,
|
||||
[0][1][2][0][RTW89_IC][52] = 127,
|
||||
[0][1][2][0][RTW89_IC][52] = 48,
|
||||
[0][1][2][0][RTW89_KCC][52] = 127,
|
||||
[0][1][2][0][RTW89_ACMA][52] = 127,
|
||||
[0][1][2][0][RTW89_CN][52] = 127,
|
||||
|
|
@ -35977,7 +35977,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][1][2][1][RTW89_FCC][48] = 48,
|
||||
[0][1][2][1][RTW89_ETSI][48] = 127,
|
||||
[0][1][2][1][RTW89_MKK][48] = 127,
|
||||
[0][1][2][1][RTW89_IC][48] = 127,
|
||||
[0][1][2][1][RTW89_IC][48] = 48,
|
||||
[0][1][2][1][RTW89_KCC][48] = 127,
|
||||
[0][1][2][1][RTW89_ACMA][48] = 127,
|
||||
[0][1][2][1][RTW89_CN][48] = 127,
|
||||
|
|
@ -35990,7 +35990,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][1][2][1][RTW89_FCC][50] = 50,
|
||||
[0][1][2][1][RTW89_ETSI][50] = 127,
|
||||
[0][1][2][1][RTW89_MKK][50] = 127,
|
||||
[0][1][2][1][RTW89_IC][50] = 127,
|
||||
[0][1][2][1][RTW89_IC][50] = 50,
|
||||
[0][1][2][1][RTW89_KCC][50] = 127,
|
||||
[0][1][2][1][RTW89_ACMA][50] = 127,
|
||||
[0][1][2][1][RTW89_CN][50] = 127,
|
||||
|
|
@ -36003,7 +36003,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[0][1][2][1][RTW89_FCC][52] = 48,
|
||||
[0][1][2][1][RTW89_ETSI][52] = 127,
|
||||
[0][1][2][1][RTW89_MKK][52] = 127,
|
||||
[0][1][2][1][RTW89_IC][52] = 127,
|
||||
[0][1][2][1][RTW89_IC][52] = 48,
|
||||
[0][1][2][1][RTW89_KCC][52] = 127,
|
||||
[0][1][2][1][RTW89_ACMA][52] = 127,
|
||||
[0][1][2][1][RTW89_CN][52] = 127,
|
||||
|
|
@ -36172,7 +36172,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[1][0][2][0][RTW89_FCC][47] = 68,
|
||||
[1][0][2][0][RTW89_ETSI][47] = 127,
|
||||
[1][0][2][0][RTW89_MKK][47] = 127,
|
||||
[1][0][2][0][RTW89_IC][47] = 127,
|
||||
[1][0][2][0][RTW89_IC][47] = 68,
|
||||
[1][0][2][0][RTW89_KCC][47] = 127,
|
||||
[1][0][2][0][RTW89_ACMA][47] = 127,
|
||||
[1][0][2][0][RTW89_CN][47] = 127,
|
||||
|
|
@ -36185,7 +36185,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[1][0][2][0][RTW89_FCC][51] = 68,
|
||||
[1][0][2][0][RTW89_ETSI][51] = 127,
|
||||
[1][0][2][0][RTW89_MKK][51] = 127,
|
||||
[1][0][2][0][RTW89_IC][51] = 127,
|
||||
[1][0][2][0][RTW89_IC][51] = 68,
|
||||
[1][0][2][0][RTW89_KCC][51] = 127,
|
||||
[1][0][2][0][RTW89_ACMA][51] = 127,
|
||||
[1][0][2][0][RTW89_CN][51] = 127,
|
||||
|
|
@ -36354,7 +36354,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[1][1][2][0][RTW89_FCC][47] = 62,
|
||||
[1][1][2][0][RTW89_ETSI][47] = 127,
|
||||
[1][1][2][0][RTW89_MKK][47] = 127,
|
||||
[1][1][2][0][RTW89_IC][47] = 127,
|
||||
[1][1][2][0][RTW89_IC][47] = 62,
|
||||
[1][1][2][0][RTW89_KCC][47] = 127,
|
||||
[1][1][2][0][RTW89_ACMA][47] = 127,
|
||||
[1][1][2][0][RTW89_CN][47] = 127,
|
||||
|
|
@ -36367,7 +36367,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[1][1][2][0][RTW89_FCC][51] = 60,
|
||||
[1][1][2][0][RTW89_ETSI][51] = 127,
|
||||
[1][1][2][0][RTW89_MKK][51] = 127,
|
||||
[1][1][2][0][RTW89_IC][51] = 127,
|
||||
[1][1][2][0][RTW89_IC][51] = 60,
|
||||
[1][1][2][0][RTW89_KCC][51] = 127,
|
||||
[1][1][2][0][RTW89_ACMA][51] = 127,
|
||||
[1][1][2][0][RTW89_CN][51] = 127,
|
||||
|
|
@ -36536,7 +36536,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[1][1][2][1][RTW89_FCC][47] = 62,
|
||||
[1][1][2][1][RTW89_ETSI][47] = 127,
|
||||
[1][1][2][1][RTW89_MKK][47] = 127,
|
||||
[1][1][2][1][RTW89_IC][47] = 127,
|
||||
[1][1][2][1][RTW89_IC][47] = 62,
|
||||
[1][1][2][1][RTW89_KCC][47] = 127,
|
||||
[1][1][2][1][RTW89_ACMA][47] = 127,
|
||||
[1][1][2][1][RTW89_CN][47] = 127,
|
||||
|
|
@ -36549,7 +36549,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[1][1][2][1][RTW89_FCC][51] = 60,
|
||||
[1][1][2][1][RTW89_ETSI][51] = 127,
|
||||
[1][1][2][1][RTW89_MKK][51] = 127,
|
||||
[1][1][2][1][RTW89_IC][51] = 127,
|
||||
[1][1][2][1][RTW89_IC][51] = 60,
|
||||
[1][1][2][1][RTW89_KCC][51] = 127,
|
||||
[1][1][2][1][RTW89_ACMA][51] = 127,
|
||||
[1][1][2][1][RTW89_CN][51] = 127,
|
||||
|
|
@ -36640,7 +36640,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[2][0][2][0][RTW89_FCC][49] = 62,
|
||||
[2][0][2][0][RTW89_ETSI][49] = 127,
|
||||
[2][0][2][0][RTW89_MKK][49] = 127,
|
||||
[2][0][2][0][RTW89_IC][49] = 127,
|
||||
[2][0][2][0][RTW89_IC][49] = 62,
|
||||
[2][0][2][0][RTW89_KCC][49] = 127,
|
||||
[2][0][2][0][RTW89_ACMA][49] = 127,
|
||||
[2][0][2][0][RTW89_CN][49] = 127,
|
||||
|
|
@ -36731,7 +36731,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[2][1][2][0][RTW89_FCC][49] = 62,
|
||||
[2][1][2][0][RTW89_ETSI][49] = 127,
|
||||
[2][1][2][0][RTW89_MKK][49] = 127,
|
||||
[2][1][2][0][RTW89_IC][49] = 127,
|
||||
[2][1][2][0][RTW89_IC][49] = 62,
|
||||
[2][1][2][0][RTW89_KCC][49] = 127,
|
||||
[2][1][2][0][RTW89_ACMA][49] = 127,
|
||||
[2][1][2][0][RTW89_CN][49] = 127,
|
||||
|
|
@ -36822,7 +36822,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[2][1][2][1][RTW89_FCC][49] = 62,
|
||||
[2][1][2][1][RTW89_ETSI][49] = 127,
|
||||
[2][1][2][1][RTW89_MKK][49] = 127,
|
||||
[2][1][2][1][RTW89_IC][49] = 127,
|
||||
[2][1][2][1][RTW89_IC][49] = 62,
|
||||
[2][1][2][1][RTW89_KCC][49] = 127,
|
||||
[2][1][2][1][RTW89_ACMA][49] = 127,
|
||||
[2][1][2][1][RTW89_CN][49] = 127,
|
||||
|
|
@ -36861,7 +36861,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[3][0][2][0][RTW89_FCC][45] = 52,
|
||||
[3][0][2][0][RTW89_ETSI][45] = 127,
|
||||
[3][0][2][0][RTW89_MKK][45] = 127,
|
||||
[3][0][2][0][RTW89_IC][45] = 127,
|
||||
[3][0][2][0][RTW89_IC][45] = 52,
|
||||
[3][0][2][0][RTW89_KCC][45] = 127,
|
||||
[3][0][2][0][RTW89_ACMA][45] = 127,
|
||||
[3][0][2][0][RTW89_CN][45] = 127,
|
||||
|
|
@ -36900,7 +36900,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[3][1][2][0][RTW89_FCC][45] = 46,
|
||||
[3][1][2][0][RTW89_ETSI][45] = 127,
|
||||
[3][1][2][0][RTW89_MKK][45] = 127,
|
||||
[3][1][2][0][RTW89_IC][45] = 127,
|
||||
[3][1][2][0][RTW89_IC][45] = 46,
|
||||
[3][1][2][0][RTW89_KCC][45] = 127,
|
||||
[3][1][2][0][RTW89_ACMA][45] = 127,
|
||||
[3][1][2][0][RTW89_CN][45] = 127,
|
||||
|
|
@ -36939,7 +36939,7 @@ const s8 rtw89_8852c_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
|
|||
[3][1][2][1][RTW89_FCC][45] = 46,
|
||||
[3][1][2][1][RTW89_ETSI][45] = 127,
|
||||
[3][1][2][1][RTW89_MKK][45] = 127,
|
||||
[3][1][2][1][RTW89_IC][45] = 127,
|
||||
[3][1][2][1][RTW89_IC][45] = 46,
|
||||
[3][1][2][1][RTW89_KCC][45] = 127,
|
||||
[3][1][2][1][RTW89_ACMA][45] = 127,
|
||||
[3][1][2][1][RTW89_CN][45] = 127,
|
||||
|
|
@ -49374,7 +49374,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[0][0][RTW89_FCC][48] = 46,
|
||||
[0][0][RTW89_ETSI][48] = 127,
|
||||
[0][0][RTW89_MKK][48] = 127,
|
||||
[0][0][RTW89_IC][48] = 127,
|
||||
[0][0][RTW89_IC][48] = 46,
|
||||
[0][0][RTW89_KCC][48] = 127,
|
||||
[0][0][RTW89_ACMA][48] = 127,
|
||||
[0][0][RTW89_CN][48] = 127,
|
||||
|
|
@ -49387,7 +49387,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[0][0][RTW89_FCC][50] = 44,
|
||||
[0][0][RTW89_ETSI][50] = 127,
|
||||
[0][0][RTW89_MKK][50] = 127,
|
||||
[0][0][RTW89_IC][50] = 127,
|
||||
[0][0][RTW89_IC][50] = 44,
|
||||
[0][0][RTW89_KCC][50] = 127,
|
||||
[0][0][RTW89_ACMA][50] = 127,
|
||||
[0][0][RTW89_CN][50] = 127,
|
||||
|
|
@ -49400,7 +49400,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[0][0][RTW89_FCC][52] = 34,
|
||||
[0][0][RTW89_ETSI][52] = 127,
|
||||
[0][0][RTW89_MKK][52] = 127,
|
||||
[0][0][RTW89_IC][52] = 127,
|
||||
[0][0][RTW89_IC][52] = 34,
|
||||
[0][0][RTW89_KCC][52] = 127,
|
||||
[0][0][RTW89_ACMA][52] = 127,
|
||||
[0][0][RTW89_CN][52] = 127,
|
||||
|
|
@ -49738,7 +49738,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[0][1][RTW89_FCC][48] = 20,
|
||||
[0][1][RTW89_ETSI][48] = 127,
|
||||
[0][1][RTW89_MKK][48] = 127,
|
||||
[0][1][RTW89_IC][48] = 127,
|
||||
[0][1][RTW89_IC][48] = 20,
|
||||
[0][1][RTW89_KCC][48] = 127,
|
||||
[0][1][RTW89_ACMA][48] = 127,
|
||||
[0][1][RTW89_CN][48] = 127,
|
||||
|
|
@ -49751,7 +49751,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[0][1][RTW89_FCC][50] = 20,
|
||||
[0][1][RTW89_ETSI][50] = 127,
|
||||
[0][1][RTW89_MKK][50] = 127,
|
||||
[0][1][RTW89_IC][50] = 127,
|
||||
[0][1][RTW89_IC][50] = 20,
|
||||
[0][1][RTW89_KCC][50] = 127,
|
||||
[0][1][RTW89_ACMA][50] = 127,
|
||||
[0][1][RTW89_CN][50] = 127,
|
||||
|
|
@ -49764,7 +49764,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[0][1][RTW89_FCC][52] = 8,
|
||||
[0][1][RTW89_ETSI][52] = 127,
|
||||
[0][1][RTW89_MKK][52] = 127,
|
||||
[0][1][RTW89_IC][52] = 127,
|
||||
[0][1][RTW89_IC][52] = 8,
|
||||
[0][1][RTW89_KCC][52] = 127,
|
||||
[0][1][RTW89_ACMA][52] = 127,
|
||||
[0][1][RTW89_CN][52] = 127,
|
||||
|
|
@ -50102,7 +50102,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[1][0][RTW89_FCC][48] = 56,
|
||||
[1][0][RTW89_ETSI][48] = 127,
|
||||
[1][0][RTW89_MKK][48] = 127,
|
||||
[1][0][RTW89_IC][48] = 127,
|
||||
[1][0][RTW89_IC][48] = 56,
|
||||
[1][0][RTW89_KCC][48] = 127,
|
||||
[1][0][RTW89_ACMA][48] = 127,
|
||||
[1][0][RTW89_CN][48] = 127,
|
||||
|
|
@ -50115,7 +50115,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[1][0][RTW89_FCC][50] = 58,
|
||||
[1][0][RTW89_ETSI][50] = 127,
|
||||
[1][0][RTW89_MKK][50] = 127,
|
||||
[1][0][RTW89_IC][50] = 127,
|
||||
[1][0][RTW89_IC][50] = 58,
|
||||
[1][0][RTW89_KCC][50] = 127,
|
||||
[1][0][RTW89_ACMA][50] = 127,
|
||||
[1][0][RTW89_CN][50] = 127,
|
||||
|
|
@ -50128,7 +50128,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[1][0][RTW89_FCC][52] = 56,
|
||||
[1][0][RTW89_ETSI][52] = 127,
|
||||
[1][0][RTW89_MKK][52] = 127,
|
||||
[1][0][RTW89_IC][52] = 127,
|
||||
[1][0][RTW89_IC][52] = 56,
|
||||
[1][0][RTW89_KCC][52] = 127,
|
||||
[1][0][RTW89_ACMA][52] = 127,
|
||||
[1][0][RTW89_CN][52] = 127,
|
||||
|
|
@ -50466,7 +50466,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[1][1][RTW89_FCC][48] = 34,
|
||||
[1][1][RTW89_ETSI][48] = 127,
|
||||
[1][1][RTW89_MKK][48] = 127,
|
||||
[1][1][RTW89_IC][48] = 127,
|
||||
[1][1][RTW89_IC][48] = 34,
|
||||
[1][1][RTW89_KCC][48] = 127,
|
||||
[1][1][RTW89_ACMA][48] = 127,
|
||||
[1][1][RTW89_CN][48] = 127,
|
||||
|
|
@ -50479,7 +50479,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[1][1][RTW89_FCC][50] = 34,
|
||||
[1][1][RTW89_ETSI][50] = 127,
|
||||
[1][1][RTW89_MKK][50] = 127,
|
||||
[1][1][RTW89_IC][50] = 127,
|
||||
[1][1][RTW89_IC][50] = 34,
|
||||
[1][1][RTW89_KCC][50] = 127,
|
||||
[1][1][RTW89_ACMA][50] = 127,
|
||||
[1][1][RTW89_CN][50] = 127,
|
||||
|
|
@ -50492,7 +50492,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[1][1][RTW89_FCC][52] = 30,
|
||||
[1][1][RTW89_ETSI][52] = 127,
|
||||
[1][1][RTW89_MKK][52] = 127,
|
||||
[1][1][RTW89_IC][52] = 127,
|
||||
[1][1][RTW89_IC][52] = 30,
|
||||
[1][1][RTW89_KCC][52] = 127,
|
||||
[1][1][RTW89_ACMA][52] = 127,
|
||||
[1][1][RTW89_CN][52] = 127,
|
||||
|
|
@ -50830,7 +50830,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[2][0][RTW89_FCC][48] = 64,
|
||||
[2][0][RTW89_ETSI][48] = 127,
|
||||
[2][0][RTW89_MKK][48] = 127,
|
||||
[2][0][RTW89_IC][48] = 127,
|
||||
[2][0][RTW89_IC][48] = 64,
|
||||
[2][0][RTW89_KCC][48] = 127,
|
||||
[2][0][RTW89_ACMA][48] = 127,
|
||||
[2][0][RTW89_CN][48] = 127,
|
||||
|
|
@ -50843,7 +50843,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[2][0][RTW89_FCC][50] = 64,
|
||||
[2][0][RTW89_ETSI][50] = 127,
|
||||
[2][0][RTW89_MKK][50] = 127,
|
||||
[2][0][RTW89_IC][50] = 127,
|
||||
[2][0][RTW89_IC][50] = 64,
|
||||
[2][0][RTW89_KCC][50] = 127,
|
||||
[2][0][RTW89_ACMA][50] = 127,
|
||||
[2][0][RTW89_CN][50] = 127,
|
||||
|
|
@ -50856,7 +50856,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[2][0][RTW89_FCC][52] = 64,
|
||||
[2][0][RTW89_ETSI][52] = 127,
|
||||
[2][0][RTW89_MKK][52] = 127,
|
||||
[2][0][RTW89_IC][52] = 127,
|
||||
[2][0][RTW89_IC][52] = 64,
|
||||
[2][0][RTW89_KCC][52] = 127,
|
||||
[2][0][RTW89_ACMA][52] = 127,
|
||||
[2][0][RTW89_CN][52] = 127,
|
||||
|
|
@ -51194,7 +51194,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[2][1][RTW89_FCC][48] = 40,
|
||||
[2][1][RTW89_ETSI][48] = 127,
|
||||
[2][1][RTW89_MKK][48] = 127,
|
||||
[2][1][RTW89_IC][48] = 127,
|
||||
[2][1][RTW89_IC][48] = 40,
|
||||
[2][1][RTW89_KCC][48] = 127,
|
||||
[2][1][RTW89_ACMA][48] = 127,
|
||||
[2][1][RTW89_CN][48] = 127,
|
||||
|
|
@ -51207,7 +51207,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[2][1][RTW89_FCC][50] = 40,
|
||||
[2][1][RTW89_ETSI][50] = 127,
|
||||
[2][1][RTW89_MKK][50] = 127,
|
||||
[2][1][RTW89_IC][50] = 127,
|
||||
[2][1][RTW89_IC][50] = 40,
|
||||
[2][1][RTW89_KCC][50] = 127,
|
||||
[2][1][RTW89_ACMA][50] = 127,
|
||||
[2][1][RTW89_CN][50] = 127,
|
||||
|
|
@ -51220,7 +51220,7 @@ const s8 rtw89_8852c_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]
|
|||
[2][1][RTW89_FCC][52] = 40,
|
||||
[2][1][RTW89_ETSI][52] = 127,
|
||||
[2][1][RTW89_MKK][52] = 127,
|
||||
[2][1][RTW89_IC][52] = 127,
|
||||
[2][1][RTW89_IC][52] = 40,
|
||||
[2][1][RTW89_KCC][52] = 127,
|
||||
[2][1][RTW89_ACMA][52] = 127,
|
||||
[2][1][RTW89_CN][52] = 127,
|
||||
|
|
|
|||
|
|
@ -68,8 +68,31 @@ static const struct rtw89_pci_info rtw8852c_pci_info = {
|
|||
.recognize_intrs = rtw89_pci_recognize_intrs_v1,
|
||||
};
|
||||
|
||||
static const struct dmi_system_id rtw8852c_pci_quirks[] = {
|
||||
{
|
||||
.ident = "Dell Inc. Vostro 16 5640",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 16 5640"),
|
||||
DMI_MATCH(DMI_PRODUCT_SKU, "0CA0"),
|
||||
},
|
||||
.driver_data = (void *)RTW89_QUIRK_PCI_BER,
|
||||
},
|
||||
{
|
||||
.ident = "Dell Inc. Inspiron 16 5640",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 16 5640"),
|
||||
DMI_MATCH(DMI_PRODUCT_SKU, "0C9F"),
|
||||
},
|
||||
.driver_data = (void *)RTW89_QUIRK_PCI_BER,
|
||||
},
|
||||
{},
|
||||
};
|
||||
|
||||
static const struct rtw89_driver_info rtw89_8852ce_info = {
|
||||
.chip = &rtw8852c_chip_info,
|
||||
.quirks = rtw8852c_pci_quirks,
|
||||
.bus = {
|
||||
.pci = &rtw8852c_pci_info,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -2545,6 +2545,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
|
|||
.dig_regs = &rtw8922a_dig_regs,
|
||||
.tssi_dbw_table = NULL,
|
||||
.support_chanctx_num = 2,
|
||||
.support_rnr = true,
|
||||
.support_bands = BIT(NL80211_BAND_2GHZ) |
|
||||
BIT(NL80211_BAND_5GHZ) |
|
||||
BIT(NL80211_BAND_6GHZ),
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ static const struct rtw89_pci_info rtw8922a_pci_info = {
|
|||
|
||||
static const struct rtw89_driver_info rtw89_8922ae_info = {
|
||||
.chip = &rtw8922a_chip_info,
|
||||
.quirks = NULL,
|
||||
.bus = {
|
||||
.pci = &rtw8922a_pci_info,
|
||||
},
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user