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drm/amd/display: Control BW allocation in FW side

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[Why]
The BW allocation feature should be controlled in FW side.

[How]
Pass the control bit to FW boot option.

Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Cruise Hung 2025-10-08 14:44:29 +08:00 committed by Alex Deucher
parent d021bd48ee
commit 1319fb80b3
5 changed files with 4 additions and 7 deletions
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3
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -850,8 +850,7 @@ union dpia_debug_options {
uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
uint32_t disable_usb4_pm_support:1; /* bit 5 */
uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */
uint32_t enable_bw_allocation_mode:1; /* bit 7 */
uint32_t reserved:24;
uint32_t reserved:25;
} bits;
uint32_t raw;
};

5
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
View File

@ -225,11 +225,6 @@ bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link)
bool ret = false;
uint8_t val;
if (link->dc->debug.dpia_debug.bits.enable_bw_allocation_mode == false) {
DC_LOG_DEBUG("%s: link[%d] DPTX BW allocation mode disabled", __func__, link->link_index);
return false;
}
val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ;
if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) {

1
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
View File

@ -318,6 +318,7 @@ struct dmub_srv_hw_params {
bool enable_non_transparent_setconfig;
bool lower_hbr3_phy_ssc;
bool override_hbr3_pll_vco;
bool disable_dpia_bw_allocation;
};
/**

1
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
View File

@ -380,6 +380,7 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu
boot_options.bits.override_hbr3_pll_vco = params->override_hbr3_pll_vco;
boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0;
boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation;
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
}

1
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
View File

@ -418,6 +418,7 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu
boot_options.bits.disable_sldo_opt = params->disable_sldo_opt;
boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig;
boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc;
boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation;
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
}