From 0cebea3ab053d195f51107fb4c7a2246af602765 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Sun, 22 Dec 2019 12:39:18 +0100 Subject: [PATCH 1/3] ARM: tegra: Let the EMC hardware use the EMC clock The EMC hardware block needs access to the EMC clock in order to scale the external memory frequency. Add the clocks property so that drivers for the EMC can acquire a reference to the EMC clock. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 413bfb981de8..a01092b6d26d 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -625,6 +625,8 @@ mc: memory-controller@70019000 { emc: emc@7001b000 { compatible = "nvidia,tegra124-emc"; reg = <0x0 0x7001b000 0x0 0x1000>; + clocks = <&tegra_car TEGRA124_CLK_EMC>; + clock-names = "emc"; nvidia,memory-controller = <&mc>; }; From ceffd1040ac0e3e661a6604bb018897c438fb340 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Sun, 22 Dec 2019 12:39:20 +0100 Subject: [PATCH 2/3] ARM: tegra: Rename EMC on Tegra124 Rename the EMC node to external-memory-controller according to device tree best practices. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 2 +- arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 2 +- arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 2 +- arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 2 +- arch/arm/boot/dts/tegra124.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index d18eaf4a4a3a..32401457ae71 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -84,7 +84,7 @@ timing-924000000 { }; }; - emc@7001b000 { + external-memory-controller@7001b000 { emc-timings-1 { nvidia,ram-code = <1>; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 784a529e1f19..861d3f22116b 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -79,7 +79,7 @@ timing-924000000 { }; }; - emc@7001b000 { + external-memory-controller@7001b000 { emc-timings-3 { nvidia,ram-code = <3>; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index fb6b3e1a0b1f..c91647d13a50 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -219,7 +219,7 @@ timing-792000000 { }; }; - emc@7001b000 { + external-memory-controller@7001b000 { emc-timings-1 { nvidia,ram-code = <1>; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index c7c31d4c1a2b..d2beea0bd15f 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -68,7 +68,7 @@ timing-792000000 { }; }; - emc@7001b000 { + external-memory-controller@7001b000 { emc-timings-1 { nvidia,ram-code = <1>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a01092b6d26d..7f330b1f150f 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -622,7 +622,7 @@ mc: memory-controller@70019000 { #iommu-cells = <1>; }; - emc: emc@7001b000 { + emc: external-memory-controller@7001b000 { compatible = "nvidia,tegra124-emc"; reg = <0x0 0x7001b000 0x0 0x1000>; clocks = <&tegra_car TEGRA124_CLK_EMC>; From 834f1d6cf3647e804e7a80569e42ee7fbee50eb1 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 18 Dec 2019 21:59:57 +0300 Subject: [PATCH 3/3] ARM: dts: tegra20: paz00: Add memory timings PAZ00 board has two variants of DDR2 SDRAM devices for External Memory: one is Hynix HY5PS1G831CLFP-Y5 and the other is Micron MT47H128M8CF-25:H. The Micron variant doesn't have official timings in the wild, hence only timings for the Hynix are added. The memory frequency-scaling was tested using the Tegra20 devfreq driver. Tested-by: Marc Dietrich Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-paz00.dts | 46 +++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 85fce5bc72d6..be0ab9b84b9a 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -311,6 +311,52 @@ nvec@7000c500 { reset-names = "i2c"; }; + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@hynix { + nvidia,ram-code = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + emc-table@166500 { + reg = <166500>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <166500>; + nvidia,emc-registers = <0x0000000a 0x00000016 + 0x00000008 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x000004df + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000a 0x000000c8 + 0x00000003 0x00000006 0x00000004 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe03b0323 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <333000>; + nvidia,emc-registers = <0x00000018 0x00000033 + 0x00000012 0x00000004 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000bff + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xf0440303 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + i2c@7000d000 { status = "okay"; clock-frequency = <400000>;