From 7017524e39dbf6ba42c34b06ec36c99859ffe361 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 11 Jan 2025 17:54:19 +0100 Subject: [PATCH 001/308] arm64: dts: qcom: x1e80100: Set CPU interconnect paths as ACTIVE_ONLY There is no use wasting power on keeping the links between the CPU and something else online when the CPUs are online. Change the interconnect tag for such paths, so that RPMh is requested to automatically clock-gate those when possible. Keeping these paths online is also a potential power collapse blocker, however this commit alone doesn't magically fix all the remaining TODOs related to suspend. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250111-topic-x1e_fixups-v1-2-77dc39237c12@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 236 ++++++++++++------------- 1 file changed, 118 insertions(+), 118 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 4936fa5b98ff..9d3843676343 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -863,8 +863,8 @@ i2c16: i2c@880000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -899,8 +899,8 @@ spi16: spi@880000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -935,8 +935,8 @@ i2c17: i2c@884000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -971,8 +971,8 @@ spi17: spi@884000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1007,8 +1007,8 @@ i2c18: i2c@888000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1043,8 +1043,8 @@ spi18: spi@888000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1079,8 +1079,8 @@ i2c19: i2c@88c000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1115,8 +1115,8 @@ spi19: spi@88c000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1151,8 +1151,8 @@ i2c20: i2c@890000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1187,8 +1187,8 @@ spi20: spi@890000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1223,8 +1223,8 @@ i2c21: i2c@894000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1259,8 +1259,8 @@ spi21: spi@894000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1295,8 +1295,8 @@ uart21: serial@894000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -1320,8 +1320,8 @@ i2c22: i2c@898000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1356,8 +1356,8 @@ spi22: spi@898000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1392,8 +1392,8 @@ i2c23: i2c@89c000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1428,8 +1428,8 @@ spi23: spi@89c000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1508,8 +1508,8 @@ i2c8: i2c@a80000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1544,8 +1544,8 @@ spi8: spi@a80000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1580,8 +1580,8 @@ i2c9: i2c@a84000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1616,8 +1616,8 @@ spi9: spi@a84000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1652,8 +1652,8 @@ i2c10: i2c@a88000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1688,8 +1688,8 @@ spi10: spi@a88000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1724,8 +1724,8 @@ i2c11: i2c@a8c000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1760,8 +1760,8 @@ spi11: spi@a8c000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1796,8 +1796,8 @@ i2c12: i2c@a90000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1832,8 +1832,8 @@ spi12: spi@a90000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1868,8 +1868,8 @@ i2c13: i2c@a94000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1904,8 +1904,8 @@ spi13: spi@a94000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1940,8 +1940,8 @@ i2c14: i2c@a98000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1976,8 +1976,8 @@ spi14: spi@a98000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2012,8 +2012,8 @@ uart14: serial@a98000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2037,8 +2037,8 @@ i2c15: i2c@a9c000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2073,8 +2073,8 @@ spi15: spi@a9c000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2152,8 +2152,8 @@ i2c0: i2c@b80000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2188,8 +2188,8 @@ spi0: spi@b80000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2224,8 +2224,8 @@ i2c1: i2c@b84000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2260,8 +2260,8 @@ spi1: spi@b84000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2296,8 +2296,8 @@ i2c2: i2c@b88000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2332,8 +2332,8 @@ uart2: serial@b88000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2357,8 +2357,8 @@ spi2: spi@b88000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2393,8 +2393,8 @@ i2c3: i2c@b8c000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2429,8 +2429,8 @@ spi3: spi@b8c000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2465,8 +2465,8 @@ i2c4: i2c@b90000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2501,8 +2501,8 @@ spi4: spi@b90000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2537,8 +2537,8 @@ i2c5: i2c@b94000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2573,8 +2573,8 @@ spi5: spi@b94000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2609,8 +2609,8 @@ i2c6: i2c@b98000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2645,8 +2645,8 @@ spi6: spi@b98000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2681,8 +2681,8 @@ i2c7: i2c@b9c000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2717,8 +2717,8 @@ spi7: spi@b9c000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -3194,8 +3194,8 @@ pcie3: pcie@1bd0000 { interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; @@ -3395,8 +3395,8 @@ pcie6a: pci@1bf8000 { interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; @@ -3522,8 +3522,8 @@ pcie5: pci@1c00000 { interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; @@ -3646,8 +3646,8 @@ pcie4: pci@1c08000 { interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; @@ -4694,8 +4694,8 @@ usb_1_ss2: usb@a0f8800 { interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "usb-ddr", "apps-usb"; @@ -4794,8 +4794,8 @@ usb_2: usb@a2f8800 { interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "usb-ddr", "apps-usb"; @@ -4879,8 +4879,8 @@ usb_mp: usb@a4f8800 { interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "usb-ddr", "apps-usb"; @@ -5053,8 +5053,8 @@ usb_1_ss1: usb@a8f8800 { interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "usb-ddr", "apps-usb"; From 18ecea8e04d8a259625a1f44c41a5d2c4b552d33 Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Sat, 11 Jan 2025 16:32:07 +0800 Subject: [PATCH 002/308] arm64: dts: qcom: sc8280xp-pmics: Fix slave ID in interrupts configuration According to the binding for qcom,spmi-pmic-arb, the cell 1 should be slave id, the slave id of pmc8280_2 is 3. Signed-off-by: Pengyu Luo Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250111083209.262269-1-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index 1e3babf2e40d..c19fb9c39ed9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -212,7 +212,7 @@ pmc8280_2: pmic@3 { pm8280_2_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; - interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + interrupts-extended = <&spmi_bus 0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; io-channels = <&pmk8280_vadc PM8350_ADC7_DIE_TEMP(3)>; io-channel-names = "thermal"; #thermal-sensor-cells = <0>; From 60a2c9cc15825fd0016a622fe7a3b2838abc32f5 Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Sat, 11 Jan 2025 16:32:08 +0800 Subject: [PATCH 003/308] arm64: dts: qcom: sc8280xp-pmics: Add more temp-alarm devices There are 4 Qualcomm PMIC Die Temp Alarm Sensor Devices under windows os, in separate dt files, pm8350c and pmr735a have already support temp alarm, add the rest 2 devices for sc8280xp-pmic. Temperature trip points are from dsdt(Temp. in tenths of degrees Kelvin). example: Name (TPSV, 0x0E60) // 0x0E60 - 2730 = 950 Method (_PSV, 0, NotSerialized) // _PSV: Passive Temperature { Return (\_SB.TZ15.TPSV) } Name (TCRT, 0x0F28) // 0X0F28 - 2730 = 1150 Method (_CRT, 0, NotSerialized) // _CRT: Critical Temperature { Return (\_SB.TZ15.TCRT) } Signed-off-by: Pengyu Luo Link: https://lore.kernel.org/r/20250111083209.262269-2-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index c19fb9c39ed9..307df1d3dcd2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -32,6 +32,26 @@ trip1 { }; }; + pmc8280c_thermal: pmc8280c-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmc8280c_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + pm8280_2_thermal: pm8280-2-thermal { polling-delay-passive = <100>; @@ -51,6 +71,26 @@ trip1 { }; }; }; + + pmr735a_thermal: pmr735a-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmr735a_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; }; }; @@ -181,6 +221,13 @@ pmc8280c: pmic@2 { #address-cells = <1>; #size-cells = <0>; + pmc8280c_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmc8280c_gpios: gpio@8800 { compatible = "qcom,pm8350c-gpio", "qcom,spmi-gpio"; reg = <0x8800>; @@ -235,6 +282,15 @@ pmr735a: pmic@4 { #address-cells = <1>; #size-cells = <0>; + pmr735a_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmk8280_vadc PMR735A_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + pmr735a_gpios: gpio@8800 { compatible = "qcom,pmr735a-gpio", "qcom,spmi-gpio"; reg = <0x8800>; From a9ca8e5c6379f00efbfbccd873ff66b0f0c46873 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Wed, 12 Feb 2025 17:03:42 +0530 Subject: [PATCH 004/308] arm64: dts: qcom: qcs6490-rb3gen2: Add vadc and adc-tm channels Add support for vadc and adc-tm channels which are used for monitoring thermistors present on the platform. - Add the necessary includes for qcom,spmi-adc7-pm7325 and qcom,spmi-adc7-pmk8350. - Add thermal zones for quiet-thermal, sdm-skin-thermal, and xo-thermal, and define their polling delays and thermal sensors. - Configure the pm7325_temp_alarm node to use the pmk8350_vadc channel for thermal monitoring. - Configure the pmk8350_adc_tm node to enable its thermal sensors and define their registers and settings. - Configure the pmk8350_vadc node to define its channels and settings Signed-off-by: Rakesh Kota Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250212113342.873086-1-quic_kotarake@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 108 +++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 7a36c90ad4ec..fe2d14865a75 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -9,6 +9,8 @@ #define PM7250B_SID 8 #define PM7250B_SID1 9 +#include +#include #include #include #include @@ -212,6 +214,44 @@ pmic_glink_sbu_in: endpoint { }; }; + thermal-zones { + sdm-skin-thermal { + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-thermal { + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -745,6 +785,36 @@ kypd_vol_up_n: kypd-vol-up-n-state { }; }; +&pm7325_temp_alarm { + io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pm8350c_pwm { nvmem = <&pmk8350_sdam_21>, <&pmk8350_sdam_22>; @@ -789,6 +859,44 @@ &pmk8350_rtc { status = "okay"; }; +&pmk8350_vadc { + channel@3 { + reg = ; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = ; + label = "xo_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@103 { + reg = ; + label = "pm7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; +}; + &pon_pwrkey { status = "okay"; }; From 97e05bb2253db34fc0971e87f523a0f1d4cf14c2 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 12 Feb 2025 15:31:36 +0200 Subject: [PATCH 005/308] arm64: dts: qcom: x1e80100: Add the watchdog device The X Elite implements Server Base System Architecture (SBSA) specification compliant generic watchdog. Describe it. Signed-off-by: Rajendra Nayak Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20250212-x1e80100-add-watchdog-v2-1-a73897f0dad5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 9d3843676343..766f1f996baa 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -8142,6 +8142,13 @@ frame@1780d000 { }; }; + watchdog@1c840000 { + compatible = "arm,sbsa-gwdt"; + reg = <0 0x1c840000 0 0x1000>, + <0 0x1c850000 0 0x1000>; + interrupts = ; + }; + pmu@24091000 { compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>; From 62a770da5327910233ff0b0e1989e14feb3d766e Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 11 Feb 2025 13:56:37 +0100 Subject: [PATCH 006/308] arm64: dts: qcom: sm8650: add OSM L3 node Add the OSC L3 Cache controller node. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-1-a0c950540e68@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 86684cb9a932..bc09e879c144 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5506,6 +5506,16 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; + epss_l3: interconnect@17d90000 { + compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3"; + reg = <0 0x17d90000 0 0x1000>; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x17d91000 0 0x1000>, From c9658c3963b8a5ebe488acfa2609fc641a126b60 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 11 Feb 2025 13:56:38 +0100 Subject: [PATCH 007/308] arm64: dts: qcom: sm8650: add cpu interconnect nodes Add the interconnect entry for each cpu, with 3 different paths: - CPU to Last Level Cache Controller (LLCC) - Last Level Cache Controller (LLCC) to DDR - L3 Cache from CPU to DDR interface Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-2-a0c950540e68@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 57 ++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index bc09e879c144..e194a95cdcc0 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -85,6 +86,13 @@ cpu0: cpu@0 { qcom,freq-domain = <&cpufreq_hw 0>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_0: l2-cache { @@ -118,6 +126,13 @@ cpu1: cpu@100 { qcom,freq-domain = <&cpufreq_hw 0>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; }; @@ -138,6 +153,13 @@ cpu2: cpu@200 { qcom,freq-domain = <&cpufreq_hw 3>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_200: l2-cache { @@ -165,6 +187,13 @@ cpu3: cpu@300 { qcom,freq-domain = <&cpufreq_hw 3>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; }; @@ -185,6 +214,13 @@ cpu4: cpu@400 { qcom,freq-domain = <&cpufreq_hw 3>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_400: l2-cache { @@ -212,6 +248,13 @@ cpu5: cpu@500 { qcom,freq-domain = <&cpufreq_hw 1>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_500: l2-cache { @@ -239,6 +282,13 @@ cpu6: cpu@600 { qcom,freq-domain = <&cpufreq_hw 1>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_600: l2-cache { @@ -266,6 +316,13 @@ cpu7: cpu@700 { qcom,freq-domain = <&cpufreq_hw 2>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; l2_700: l2-cache { From c24db2c178578ab069dba8be81ef278854bad74f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 11 Feb 2025 13:56:39 +0100 Subject: [PATCH 008/308] arm64: dts: qcom: sm8650: add cpu OPP table with DDR, LLCC & L3 bandwidths Add the OPP tables for each CPU clusters (cpu0-1, cpu2-3-4, cpu5-6 & cpu7) to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache frequency by aggregating bandwidth requests of all CPU core with referenc to the current OPP they are configured in by the LMH/EPSS hardware. The effect is a proper caches & DDR frequency scaling when CPU cores changes frequency. The OPP tables were built using the downstream memlat ddr, llcc & l3 tables for each cluster types with the actual EPSS cpufreq LUT tables from running HDK and QRD devices. The cpu2 and cpu5 tables are similar but must be kept separate to take in account that they define OPP for shared CPUs of two different clusters that can scale separately, thus vote different bandwidths. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-3-a0c950540e68@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 876 +++++++++++++++++++++++++++ 1 file changed, 876 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e194a95cdcc0..09cc884f0969 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -86,6 +86,8 @@ cpu0: cpu@0 { qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -126,6 +128,8 @@ cpu1: cpu@100 { qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -153,6 +157,8 @@ cpu2: cpu@200 { qcom,freq-domain = <&cpufreq_hw 3>; + operating-points-v2 = <&cpu2_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -187,6 +193,8 @@ cpu3: cpu@300 { qcom,freq-domain = <&cpufreq_hw 3>; + operating-points-v2 = <&cpu2_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -214,6 +222,8 @@ cpu4: cpu@400 { qcom,freq-domain = <&cpufreq_hw 3>; + operating-points-v2 = <&cpu2_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -248,6 +258,8 @@ cpu5: cpu@500 { qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu5_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -282,6 +294,8 @@ cpu6: cpu@600 { qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu5_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -316,6 +330,8 @@ cpu7: cpu@700 { qcom,freq-domain = <&cpufreq_hw 2>; + operating-points-v2 = <&cpu7_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -483,6 +499,866 @@ memory@a0000000 { reg = <0 0xa0000000 0 0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-364800000 { + opp-hz = /bits/ 64 <364800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>; + }; + + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(466000 * 16) (547000 * 4) (940800 * 32)>; + }; + + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <(466000 * 16) (547000 * 4) (1036800 * 32)>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1132800 * 32)>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; + }; + + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; + }; + + opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; + }; + + opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; + }; + + opp-1689600000 { + opp-hz = /bits/ 64 <1689600000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; + }; + + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; + }; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; + }; + + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; + }; + + opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; + }; + + opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; + }; + + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; + }; + + opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (2035200 * 32)>; + }; + }; + + cpu2_opp_table: opp-table-cpu2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; + }; + + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1075200000 { + opp-hz = /bits/ 64 <1075200000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; + }; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; + }; + + opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2438400000 { + opp-hz = /bits/ 64 <2438400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2515200000 { + opp-hz = /bits/ 64 <2515200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2572800000 { + opp-hz = /bits/ 64 <2572800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2630400000 { + opp-hz = /bits/ 64 <2630400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2707200000 { + opp-hz = /bits/ 64 <2707200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2764800000 { + opp-hz = /bits/ 64 <2764800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; + }; + + opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2899200000 { + opp-hz = /bits/ 64 <2899200000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2956800000 { + opp-hz = /bits/ 64 <2956800000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3014400000 { + opp-hz = /bits/ 64 <3014400000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3072000000 { + opp-hz = /bits/ 64 <3072000000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3148800000 { + opp-hz = /bits/ 64 <3148800000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; + }; + }; + + cpu5_opp_table: opp-table-cpu5 { + compatible = "operating-points-v2"; + opp-shared; + + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; + }; + + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1075200000 { + opp-hz = /bits/ 64 <1075200000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; + }; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; + }; + + opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2438400000 { + opp-hz = /bits/ 64 <2438400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2515200000 { + opp-hz = /bits/ 64 <2515200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2572800000 { + opp-hz = /bits/ 64 <2572800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2630400000 { + opp-hz = /bits/ 64 <2630400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2707200000 { + opp-hz = /bits/ 64 <2707200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2764800000 { + opp-hz = /bits/ 64 <2764800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; + }; + + opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2899200000 { + opp-hz = /bits/ 64 <2899200000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2956800000 { + opp-hz = /bits/ 64 <2956800000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3014400000 { + opp-hz = /bits/ 64 <3014400000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3072000000 { + opp-hz = /bits/ 64 <3072000000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3148800000 { + opp-hz = /bits/ 64 <3148800000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; + }; + }; + + cpu7_opp_table: opp-table-cpu7 { + compatible = "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1075200000 { + opp-hz = /bits/ 64 <1075200000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1305600000 { + opp-hz = /bits/ 64 <1305600000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; + }; + + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <(806000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2438400000 { + opp-hz = /bits/ 64 <2438400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2496000000 { + opp-hz = /bits/ 64 <2496000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2630400000 { + opp-hz = /bits/ 64 <2630400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2688000000 { + opp-hz = /bits/ 64 <2688000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2745600000 { + opp-hz = /bits/ 64 <2745600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; + }; + + opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2880000000 { + opp-hz = /bits/ 64 <2880000000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2937600000 { + opp-hz = /bits/ 64 <2937600000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2995200000 { + opp-hz = /bits/ 64 <2995200000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3052800000 { + opp-hz = /bits/ 64 <3052800000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3187200000 { + opp-hz = /bits/ 64 <3187200000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; + }; + + opp-3302400000 { + opp-hz = /bits/ 64 <3302400000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; + }; + }; + pmu-a520 { compatible = "arm,cortex-a520-pmu"; interrupts = ; From 914d16b4a9c4569cc8091a1dfda432dab2fcb9d1 Mon Sep 17 00:00:00 2001 From: Janaki Ramaiah Thota Date: Fri, 21 Feb 2025 22:40:14 +0530 Subject: [PATCH 009/308] arm64: dts: qcom: qcs6490-rb3gen2: add and enable BT node Add the PMU node for WCN6750 present on the qcs6490-rb3gen2 board and assign its power outputs to the Bluetooth module. In WCN6750 module sw_ctrl and wifi-enable pins are handled in the wifi controller firmware. Therefore, it is not required to have those pins' entries in the PMU node. Signed-off-by: Janaki Ramaiah Thota Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250221171014.120946-2-quic_janathot@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 171 ++++++++++++++++++- 1 file changed, 170 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index fe2d14865a75..a651e9b6d56b 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -36,6 +36,7 @@ / { aliases { serial0 = &uart5; + serial1 = &uart7; }; chosen { @@ -258,6 +259,63 @@ vph_pwr: vph-pwr-regulator { regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; }; + + wcn6750-pmu { + compatible = "qcom,wcn6750-pmu"; + pinctrl-0 = <&bt_en>; + pinctrl-names = "default"; + vddaon-supply = <&vreg_s7b_0p972>; + vddasd-supply = <&vreg_l11c_2p8>; + vddpmu-supply = <&vreg_s7b_0p972>; + vddrfa0p8-supply = <&vreg_s7b_0p972>; + vddrfa1p2-supply = <&vreg_s8b_1p272>; + vddrfa1p7-supply = <&vreg_s1b_1p872>; + vddrfa2p2-supply = <&vreg_s1c_2p19>; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -907,6 +965,39 @@ &pon_resin { status = "okay"; }; +&qup_uart7_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + &qupv3_id_0 { status = "okay"; }; @@ -950,12 +1041,90 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ + + bt_en: bt-en-state { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; }; &uart5 { status = "okay"; }; +&uart7 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-1 = <&qup_uart7_sleep_cts>, + <&qup_uart7_sleep_rts>, + <&qup_uart7_sleep_tx>, + <&qup_uart7_sleep_rx>; + pinctrl-names = "default", + "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + max-speed = <3200000>; + }; +}; + &usb_1 { status = "okay"; }; From 44ebb21f6080ec0d6492a01eb3d2a125655fbb51 Mon Sep 17 00:00:00 2001 From: Wojciech Slenska Date: Tue, 12 Nov 2024 13:46:49 +0100 Subject: [PATCH 010/308] arm64: dts: qcom: qcm2290: Add uart3 node Add node to support uart3. Signed-off-by: Wojciech Slenska Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20241112124651.215537-1-wojciech.slenska@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index f0746123e594..496e493c5845 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -550,6 +550,13 @@ qup_uart0_default: qup-uart0-default-state { bias-disable; }; + qup_uart3_default: qup-uart3-default-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "qup3"; + drive-strength = <2>; + bias-disable; + }; + qup_uart4_default: qup-uart4-default-state { pins = "gpio12", "gpio13"; function = "qup4"; @@ -1239,6 +1246,23 @@ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, status = "disabled"; }; + uart3: serial@4a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart3_default>; + pinctrl-names = "default"; + interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG + &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + status = "disabled"; + }; + i2c4: i2c@4a90000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x04a90000 0x0 0x4000>; From 0a05ddb42ea942b21c7459f1b80d68508fea225e Mon Sep 17 00:00:00 2001 From: Sanjay Chitroda Date: Mon, 3 Feb 2025 13:30:59 +0530 Subject: [PATCH 011/308] ARM: dts: qcom: Fix indentation errors Corrected indentation issues in the qcom devicetree files as identified by ./scripts/checkpatch.pl. Signed-off-by: Sanjay Chitroda Link: https://lore.kernel.org/r/40fc9c914f5972decbd6d639396d65bf080d3ceb.1738568609.git.quic_ckantibh@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts | 4 ++-- arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts index 6fce0112361f..34b0cf35fdac 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts @@ -149,7 +149,7 @@ &mdss { }; &pm8941_gpios { - msm_keys_default: pm8941-gpio-keys-state { + msm_keys_default: pm8941-gpio-keys-state { pins = "gpio5", "gpio23"; function = "normal"; input-enable; @@ -157,7 +157,7 @@ msm_keys_default: pm8941-gpio-keys-state { bias-pull-up; qcom,drive-strength = ; power-source = ; /* 1.8V */ - }; + }; }; &pm8941_lpg { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi index cc88cf5f0d9b..5a95a2d03c42 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi @@ -43,7 +43,7 @@ nand_pins: nand-state { "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69"; function = "qpic"; - }; + }; }; serial@78af000 { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 06b20c196faf..ecfb6e41bf05 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -126,7 +126,7 @@ opp-500000000 { opp-716000000 { opp-hz = /bits/ 64 <716000000>; clock-latency-ns = <256000>; - }; + }; }; memory { From 8d6a7321514964ca2814edc6232ae47122874a5e Mon Sep 17 00:00:00 2001 From: Tingguo Cheng Date: Wed, 8 Jan 2025 19:00:17 +0800 Subject: [PATCH 012/308] arm64: dts: qcom: qcs8300: Adds SPMI support Add the SPMI bus arbiter(Version:5.2.0) node for QCS8300 SoC which connected with PMICs on QCS8300 boards. Reviewed-by: Dmitry Baryshkov Signed-off-by: Tingguo Cheng Link: https://lore.kernel.org/r/20250108-adds-spmi-pmic-peripherals-for-qcs8300-v3-1-ee94642279ff@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 4a057f7c0d9f..d08f70731c87 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -3027,6 +3027,28 @@ IPCC_MPROC_SIGNAL_GLINK_QMP #clock-cells = <0>; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + qcom,channel = <0>; + qcom,ee = <0>; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,qcs8300-tlmm"; reg = <0x0 0x0f100000 0x0 0x300000>; From 9221ec2a65bc8beabb28fcbd9a3c53e743633b3f Mon Sep 17 00:00:00 2001 From: Tingguo Cheng Date: Wed, 8 Jan 2025 19:00:18 +0800 Subject: [PATCH 013/308] arm64: dts: qcom: qcs8300-ride: Enable PMIC peripherals Enable PMIC and PMIC peripherals for qcs8300-ride board. The qcs8 300-ride uses 2 pmics(pmm8620au:0,pmm8650au:1) on the board, which are variants of pmm8654au used on sa8775p/qcs9100 -ride(4x pmics). Reviewed-by: Dmitry Baryshkov Signed-off-by: Tingguo Cheng Link: https://lore.kernel.org/r/20250108-adds-spmi-pmic-peripherals-for-qcs8300-v3-2-ee94642279ff@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300-pmics.dtsi | 51 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 1 + 2 files changed, 52 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs8300-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs8300-pmics.dtsi b/arch/arm64/boot/dts/qcom/qcs8300-pmics.dtsi new file mode 100644 index 000000000000..a94b0bfa98dc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8300-pmics.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + pmm8620au_0: pmic@0 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8620au_0_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + allow-set-time; + }; + + pmm8620au_0_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8620au_0_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmm8650au_1: pmic@2 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmm8650au_1_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8650au_1_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index b5c9f89b3435..916d4e6da922 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -9,6 +9,7 @@ #include #include "qcs8300.dtsi" +#include "qcs8300-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. QCS8300 Ride"; compatible = "qcom,qcs8300-ride", "qcom,qcs8300"; From 5429861bdc33bdc37697909b1f62b1214cd335a9 Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Sun, 23 Feb 2025 19:01:51 +0800 Subject: [PATCH 014/308] arm64: dts: qcom: sc8280xp: Fix clock for spi0 to spi7 Enabling spi6 caused boot loop on my device(Huawei Matebook E Go), &spi6 { pinctrl-0 = <&spi6_default>; pinctrl-names = "default"; status = "okay"; }; After looking into this, I found the clocks for spi0 to spi7 are wrong, we can derive the correct clocks from the regular pattern between spi8 to spi15, spi16 to spi23. Or we can verify it according to the hex file of BSRC_QSPI.bin(From windows driver qcspi8280.cab) 000035d0: 0700 4445 5649 4345 0001 000a 005c 5f53 ..DEVICE.....\_S 000035e0: 422e 5350 4937 0003 0076 0001 000a 0043 B.SPI7...v.....C 000035f0: 4f4d 504f 4e45 4e54 0000 0008 0000 0000 OMPONENT........ 00003600: 0000 0000 0003 0017 0001 0007 0046 5354 .............FST 00003610: 4154 4500 0000 0800 0000 0000 0000 0000 ATE............. 00003620: 0300 3d00 0100 1400 4449 5343 4f56 4552 ..=.....DISCOVER 00003630: 4142 4c45 5f50 5354 4154 4500 0100 0600 ABLE_PSTATE..... 00003640: 434c 4f43 4b00 0100 1700 6763 635f 7175 CLOCK.....gcc_qu 00003650: 7076 335f 7772 6170 305f 7336 5f63 6c6b pv3_wrap0_s6_clk Signed-off-by: Pengyu Luo Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250223110152.47192-1-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 01501acb1790..f57c23c244b6 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1221,7 +1221,7 @@ spi0: spi@980000 { reg = <0 0x00980000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; interrupts = ; power-domains = <&rpmhpd SC8280XP_CX>; @@ -1253,7 +1253,7 @@ spi1: spi@984000 { reg = <0 0x00984000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; interrupts = ; power-domains = <&rpmhpd SC8280XP_CX>; @@ -1285,7 +1285,7 @@ spi2: spi@988000 { reg = <0 0x00988000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; interrupts = ; power-domains = <&rpmhpd SC8280XP_CX>; @@ -1331,7 +1331,7 @@ spi3: spi@98c000 { reg = <0 0x0098c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; interrupts = ; power-domains = <&rpmhpd SC8280XP_CX>; @@ -1363,7 +1363,7 @@ spi4: spi@990000 { reg = <0 0x00990000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; interrupts = ; power-domains = <&rpmhpd SC8280XP_CX>; @@ -1395,7 +1395,7 @@ spi5: spi@994000 { reg = <0 0x00994000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; interrupts = ; power-domains = <&rpmhpd SC8280XP_CX>; @@ -1427,7 +1427,7 @@ spi6: spi@998000 { reg = <0 0x00998000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; interrupts = ; power-domains = <&rpmhpd SC8280XP_CX>; @@ -1459,7 +1459,7 @@ spi7: spi@99c000 { reg = <0 0x0099c000 0 0x4000>; #address-cells = <1>; #size-cells = <0>; - clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; interrupts = ; power-domains = <&rpmhpd SC8280XP_CX>; From 7373610dde49566fe091545aa0b753cc5e34116d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 22 Feb 2025 02:43:04 +0200 Subject: [PATCH 015/308] arm64: dts: qcom: sdm845-db845c: enable sensors DSP Enable SLPI, sensors DSP, on the Qualcomm Robotics RB3 platform. The firmware for the DSP is a part of linux-firmware repository. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250222-rb3-rb5-slpi-v1-1-6739be1684b6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 1cc0f571e1f7..cd6af2fbc5ef 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -756,6 +756,12 @@ &sdhc_2 { cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; }; +&slpi_pas { + firmware-name = "qcom/sdm845/Thundercomm/db845c/slpi.mbn"; + + status = "okay"; +}; + &sound { compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard"; pinctrl-0 = <&quat_mi2s_active From 341e66232128b674300d4474557c23bb32b7aeba Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 22 Feb 2025 02:43:05 +0200 Subject: [PATCH 016/308] arm64: dts: qcom: qrb5165-rb5: enable sensors DSP Enable SLPI, sensors DSP, on the Qualcomm Robotics RB5 platform. The firmware for the DSP is a part of linux-firmware repository. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250222-rb3-rb5-slpi-v1-2-6739be1684b6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 7afa5acac3fc..15b187300810 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1032,6 +1032,12 @@ &sdhc_2 { no-mmc; }; +&slpi { + firmware-name = "qcom/sm8250/Thundercomm/RB5/slpi.mbn"; + + status = "okay"; +}; + &sound { compatible = "qcom,qrb5165-rb5-sndcard"; pinctrl-0 = <&tert_mi2s_active>; From 45bd6ff900cfe5038e2718a900f153ded3fa5392 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Thu, 9 Jan 2025 21:52:31 +0100 Subject: [PATCH 017/308] arm64: dts: qcom: x1e80100: Mark usb_2 as dma-coherent Make this USB controller consistent with the others on this platform. Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Signed-off-by: Mark Kettenis Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250109205232.92336-1-kettenis@openbsd.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 766f1f996baa..b927a7772701 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4814,6 +4814,8 @@ usb_2_dwc3: usb@a200000 { snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; + dma-coherent; + ports { #address-cells = <1>; #size-cells = <0>; From bd3801a8d44e0c538f3ffe011274a5c8a9a0a629 Mon Sep 17 00:00:00 2001 From: Cheng Jiang Date: Fri, 10 Jan 2025 14:39:14 +0800 Subject: [PATCH 018/308] arm64: dts: qcom: sa8775p-ride: Add firmware-name in BT node The sa8775p-ride platform uses the QCA6698 Bluetooth chip. While the QCA6698 shares the same IP core as the WCN6855, it has different RF components and RAM sizes, requiring new firmware files. Use the firmware-name property to specify the NVM and rampatch firmware to load. Signed-off-by: Cheng Jiang Reviewed-by: Zijun Hu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250110063914.28001-2-quic_chejiang@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi index 175f8b1e3b2d..1697c11f5c65 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -937,6 +937,7 @@ &uart17 { bluetooth { compatible = "qcom,wcn6855-bt"; + firmware-name = "QCA6698/hpnv21", "QCA6698/hpbtfw21.tlv"; vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; vddaon-supply = <&vreg_pmu_aon_0p59>; From 144230e5840c09984ad743c3df9de5fb443159a9 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 10 Feb 2025 15:01:18 +0800 Subject: [PATCH 019/308] arm64: dts: qcom: ipq6018: add 1.2GHz CPU Frequency The final version of IPQ6000 (SoC id: IPQ6000, SBL version: BOOT.XF.0.3-00086-IPQ60xxLZB-1) has a max design frequency of 1.2GHz, so add this CPU frequency. Signed-off-by: Chukun Pan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250210070122.208842-2-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index dbf6716bcb59..57ad6f0e6e34 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -119,6 +119,13 @@ opp-1056000000 { clock-latency-ns = <200000>; }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x4>; + clock-latency-ns = <200000>; + }; + opp-1320000000 { opp-hz = /bits/ 64 <1320000000>; opp-microvolt = <862500>; From a96e765a7b3f64429f7eec3471a2093355ab041e Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 10 Feb 2025 15:01:19 +0800 Subject: [PATCH 020/308] arm64: dts: qcom: ipq6018: add 1.5GHz CPU Frequency The early version of IPQ6000 (SoC id: IPQ6018, SBL version: BOOT.XF.0.3-00077-IPQ60xxLZB-2) and IPQ6005 SoCs can reach a max frequency of 1.5GHz, so add this CPU frequency. Signed-off-by: Chukun Pan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250210070122.208842-3-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 57ad6f0e6e34..7514919132b6 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -140,6 +140,13 @@ opp-1440000000 { clock-latency-ns = <200000>; }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <937500>; + opp-supported-hw = <0x2>; + clock-latency-ns = <200000>; + }; + opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <987500>; From 0c4c0f14b7d704bcb728d018a74788771dc9286b Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 10 Feb 2025 15:01:20 +0800 Subject: [PATCH 021/308] arm64: dts: qcom: ipq6018: move mp5496 regulator out of soc dtsi Some IPQ60xx SoCs don't come with the mp5496 pmic chip. The mp5496 pmic was never part of the IPQ60xx SoC, it's optional, so we moved it out of the soc dtsi. Signed-off-by: Chukun Pan Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250210070122.208842-4-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 35 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 -------- 3 files changed, 36 insertions(+), 15 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index f5f4827c0e17..9c69d3027b43 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "ipq6018.dtsi" +#include "ipq6018-mp5496.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi new file mode 100644 index 000000000000..fe2152df69f4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * ipq6018-mp5496.dtsi describes common properties (e.g. regulators) that + * apply to most devices that make use of the IPQ6018 SoC and MP5496 PMIC. + */ + +#include "ipq6018.dtsi" + +&cpu0 { + cpu-supply = <&ipq6018_s2>; +}; + +&cpu1 { + cpu-supply = <&ipq6018_s2>; +}; + +&cpu2 { + cpu-supply = <&ipq6018_s2>; +}; + +&cpu3 { + cpu-supply = <&ipq6018_s2>; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq6018_s2: s2 { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 7514919132b6..a02aa641cb90 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -43,7 +43,6 @@ cpu0: cpu@0 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -56,7 +55,6 @@ cpu1: cpu@1 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -69,7 +67,6 @@ cpu2: cpu@2 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -82,7 +79,6 @@ cpu3: cpu@3 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; #cooling-cells = <2>; }; @@ -184,16 +180,6 @@ glink-edge { rpm_requests: rpm-requests { compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm"; qcom,glink-channels = "rpm_requests"; - - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - - ipq6018_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; - }; }; }; }; From e60f872c2dc4c1d9227977c8714373fe6328699c Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 10 Feb 2025 15:01:21 +0800 Subject: [PATCH 022/308] arm64: dts: qcom: ipq6018: rename labels of mp5496 regulator Change the labels of mp5496 regulator from ipq6018 to mp5496. Suggested-by: Konrad Dybcio Suggested-by: Dmitry Baryshkov Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250210070122.208842-5-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi index fe2152df69f4..08b54b1e5249 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi @@ -7,26 +7,26 @@ #include "ipq6018.dtsi" &cpu0 { - cpu-supply = <&ipq6018_s2>; + cpu-supply = <&mp5496_s2>; }; &cpu1 { - cpu-supply = <&ipq6018_s2>; + cpu-supply = <&mp5496_s2>; }; &cpu2 { - cpu-supply = <&ipq6018_s2>; + cpu-supply = <&mp5496_s2>; }; &cpu3 { - cpu-supply = <&ipq6018_s2>; + cpu-supply = <&mp5496_s2>; }; &rpm_requests { regulators { compatible = "qcom,rpm-mp5496-regulators"; - ipq6018_s2: s2 { + mp5496_s2: s2 { regulator-min-microvolt = <725000>; regulator-max-microvolt = <1062500>; regulator-always-on; From a566fb9ba8ffecb56c50729390a9ea076f5c9532 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 10 Feb 2025 15:01:22 +0800 Subject: [PATCH 023/308] arm64: dts: qcom: ipq6018: add LDOA2 regulator Add LDOA2 regulator from MP5496 to support SDCC voltage scaling. Suggested-by: Robert Marko Signed-off-by: Chukun Pan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250210070122.208842-6-amadeus@jmu.edu.cn Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi index 08b54b1e5249..d6b111a77f79 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi @@ -31,5 +31,14 @@ mp5496_s2: s2 { regulator-max-microvolt = <1062500>; regulator-always-on; }; + + mp5496_l2: l2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; }; }; + +&sdhc { + vqmmc-supply = <&mp5496_l2>; +}; From 3fe12c798f9abf26933b35b91d7aaaa77349c63c Mon Sep 17 00:00:00 2001 From: Praveenkumar I Date: Mon, 10 Feb 2025 17:34:33 +0530 Subject: [PATCH 024/308] arm64: dts: qcom: ipq5332: Add tsens node IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsens node with nvmem cells for calibration data. Reviewed-by: Konrad Dybcio Signed-off-by: Praveenkumar I Signed-off-by: Manikanta Mylavarapu Link: https://lore.kernel.org/r/20250210120436.821684-4-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 66 +++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index ca3da95730bd..cb3657bb8aee 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -177,6 +177,46 @@ cpu_speed_bin: cpu-speed-bin@1d { reg = <0x1d 0x2>; bits = <7 2>; }; + + tsens_sens11_off: s11@3a5 { + reg = <0x3a5 0x1>; + bits = <4 4>; + }; + + tsens_sens12_off: s12@3a6 { + reg = <0x3a6 0x1>; + bits = <0 4>; + }; + + tsens_sens13_off: s13@3a6 { + reg = <0x3a6 0x1>; + bits = <4 4>; + }; + + tsens_sens14_off: s14@3ad { + reg = <0x3ad 0x2>; + bits = <7 4>; + }; + + tsens_sens15_off: s15@3ae { + reg = <0x3ae 0x1>; + bits = <3 4>; + }; + + tsens_mode: mode@3e1 { + reg = <0x3e1 0x1>; + bits = <0 3>; + }; + + tsens_base0: base0@3e1 { + reg = <0x3e1 0x2>; + bits = <3 10>; + }; + + tsens_base1: base1@3e2 { + reg = <0x3e2 0x2>; + bits = <5 10>; + }; }; rng: rng@e3000 { @@ -186,6 +226,32 @@ rng: rng@e3000 { clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5332-tsens"; + reg = <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + interrupts = ; + interrupt-names = "combined"; + nvmem-cells = <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&tsens_sens11_off>, + <&tsens_sens12_off>, + <&tsens_sens13_off>, + <&tsens_sens14_off>, + <&tsens_sens15_off>; + nvmem-cell-names = "mode", + "base0", + "base1", + "tsens_sens11_off", + "tsens_sens12_off", + "tsens_sens13_off", + "tsens_sens14_off", + "tsens_sens15_off"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5332-tlmm"; reg = <0x01000000 0x300000>; From 9b341f34293f92096044431957a8dbd6793c8aa6 Mon Sep 17 00:00:00 2001 From: Praveenkumar I Date: Mon, 10 Feb 2025 17:34:34 +0530 Subject: [PATCH 025/308] arm64: dts: qcom: ipq5332: Add thermal zone nodes This patch adds thermal zone nodes for sensors present in IPQ5332. Reviewed-by: Dmitry Baryshkov Signed-off-by: Praveenkumar I Signed-off-by: Manikanta Mylavarapu Link: https://lore.kernel.org/r/20250210120436.821684-5-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 69 +++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index cb3657bb8aee..69dda757925d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -547,6 +547,75 @@ frame@b128000 { }; }; + thermal-zones { + rfa-0-thermal { + thermal-sensors = <&tsens 11>; + + trips { + rfa-0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + rfa-1-thermal { + thermal-sensors = <&tsens 12>; + + trips { + rfa-1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + misc-thermal { + thermal-sensors = <&tsens 13>; + + trips { + misc-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-top-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens 14>; + + trips { + cpu-top-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu-passive { + temperature = <105000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + top-glue-thermal { + thermal-sensors = <&tsens 15>; + + trips { + top-glue-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From a61adfe29624bd1a4530046e76808ed60927b9ad Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Mon, 10 Feb 2025 17:34:35 +0530 Subject: [PATCH 026/308] arm64: dts: qcom: ipq5424: Add tsens node IPQ5424 has tsens v2.3.3 peripheral. This patch adds the tsens node with nvmem cells for calibration data. Reviewed-by: Konrad Dybcio Signed-off-by: Manikanta Mylavarapu Link: https://lore.kernel.org/r/20250210120436.821684-6-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 87 +++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 7034d378b1ef..774386d785d5 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -152,6 +152,93 @@ soc@0 { #size-cells = <2>; ranges = <0 0 0 0 0x10 0>; + efuse@a4000 { + compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; + reg = <0 0x000a4000 0 0x741>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_sens9_off: s9@3dc { + reg = <0x3dc 0x1>; + bits = <4 4>; + }; + + tsens_sens10_off: s10@3dd { + reg = <0x3dd 0x1>; + bits = <0 4>; + }; + + tsens_sens11_off: s11@3dd { + reg = <0x3dd 0x1>; + bits = <4 4>; + }; + + tsens_sens12_off: s12@3de { + reg = <0x3de 0x1>; + bits = <0 4>; + }; + + tsens_sens13_off: s13@3de { + reg = <0x3de 0x1>; + bits = <4 4>; + }; + + tsens_sens14_off: s14@3e5 { + reg = <0x3e5 0x2>; + bits = <7 4>; + }; + + tsens_sens15_off: s15@3e6 { + reg = <0x3e6 0x1>; + bits = <3 4>; + }; + + tsens_mode: mode@419 { + reg = <0x419 0x1>; + bits = <0 3>; + }; + + tsens_base0: base0@419 { + reg = <0x419 0x2>; + bits = <3 10>; + }; + + tsens_base1: base1@41a { + reg = <0x41a 0x2>; + bits = <5 10>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5424-tsens"; + reg = <0 0x004a9000 0 0x1000>, + <0 0x004a8000 0 0x1000>; + interrupts = ; + interrupt-names = "combined"; + nvmem-cells = <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&tsens_sens9_off>, + <&tsens_sens10_off>, + <&tsens_sens11_off>, + <&tsens_sens12_off>, + <&tsens_sens13_off>, + <&tsens_sens14_off>, + <&tsens_sens15_off>; + nvmem-cell-names = "mode", + "base0", + "base1", + "tsens_sens9_off", + "tsens_sens10_off", + "tsens_sens11_off", + "tsens_sens12_off", + "tsens_sens13_off", + "tsens_sens14_off", + "tsens_sens15_off"; + #qcom,sensors = <7>; + #thermal-sensor-cells = <1>; + }; + rng: rng@4c3000 { compatible = "qcom,ipq5424-trng", "qcom,trng"; reg = <0 0x004c3000 0 0x1000>; From 017c28788a4caffb14f4895597bdf38ee9fc8f2b Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Mon, 10 Feb 2025 17:34:36 +0530 Subject: [PATCH 027/308] arm64: dts: qcom: ipq5424: Add thermal zone nodes Add thermal zone nodes for sensors present in IPQ5424. Signed-off-by: Manikanta Mylavarapu Link: https://lore.kernel.org/r/20250210120436.821684-7-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 114 ++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 774386d785d5..7a7ad700a382 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -595,6 +595,120 @@ frame@f42d000 { }; + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens 14>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <9000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <9000>; + type = "passive"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens 12>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <9000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <9000>; + type = "passive"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens 11>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <9000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <9000>; + type = "passive"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens 13>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <9000>; + type = "critical"; + }; + + cpu-passive { + temperature = <110000>; + hysteresis = <9000>; + type = "passive"; + }; + }; + }; + + wcss-tile2-thermal { + thermal-sensors = <&tsens 9>; + + trips { + wcss-tile2-critical { + temperature = <125000>; + hysteresis = <9000>; + type = "critical"; + }; + }; + }; + + wcss-tile3-thermal { + thermal-sensors = <&tsens 10>; + + trips { + wcss-tile3-critical { + temperature = <125000>; + hysteresis = <9000>; + type = "critical"; + }; + }; + }; + + top-glue-thermal { + thermal-sensors = <&tsens 15>; + + trips { + top-glue-critical { + temperature = <125000>; + hysteresis = <9000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From 467284a3097f4348cf227053b53eb1bba2af9ae5 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Mon, 24 Feb 2025 12:03:38 +0530 Subject: [PATCH 028/308] arm64: dts: qcom: qcs8300: Add QUPv3 configuration Add DT support for QUPV3 Serial Engines. Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya Link: https://lore.kernel.org/r/20250224063338.27306-1-quic_vdadhani@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1874 ++++++++++++++++++++++++- 1 file changed, 1870 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index d08f70731c87..ff99ec21f88c 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -351,6 +352,15 @@ mc_virt: interconnect-1 { qcom,bcm-voters = <&apps_bcm_voter>; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupts = ; @@ -627,6 +637,29 @@ qfprom: efuse@784000 { #size-cells = <1>; }; + gpi_dma0: dma-controller@900000 { + compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x900000 0x0 0x60000>; + #dma-cells = <3>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x416 0x0>; + dma-channels = <12>; + dma-channel-mask = <0xfff>; + dma-coherent; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x9c0000 0x0 0x2000>; @@ -637,14 +670,527 @@ qupv3_id_0: geniqup@9c0000 { "s-ahb"; #address-cells = <2>; #size-cells = <2>; + iommus = <&apps_smmu 0x403 0x0>; + dma-coherent; status = "disabled"; + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x980000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x980000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart0: serial@980000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x980000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, + <&qup_uart0_tx>, <&qup_uart0_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x984000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x984000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart1: serial@984000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x984000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, + <&qup_uart1_tx>, <&qup_uart1_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x988000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x988000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart2: serial@988000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x988000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, + <&qup_uart2_tx>, <&qup_uart2_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x98c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x98c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart3: serial@98c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x98c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, + <&qup_uart3_tx>, <&qup_uart3_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x990000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x990000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart4: serial@990000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x990000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, + <&qup_uart4_tx>, <&qup_uart4_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x994000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x994000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart5: serial@994000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x994000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, + <&qup_uart5_tx>, <&qup_uart5_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x998000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x998000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart6: serial@998000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x998000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, + <&qup_uart6_tx>, <&qup_uart6_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + uart7: serial@99c000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x0099c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; - pinctrl-0 = <&qup_uart7_default>; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; pinctrl-names = "default"; interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -653,6 +1199,707 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0xa00000 0x0 0x60000>; + #dma-cells = <3>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x456 0x0>; + dma-channels = <12>; + dma-channel-mask = <0xfff>; + dma-coherent; + status = "disabled"; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xac0000 0x0 0x2000>; + ranges; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu 0x443 0x0>; + dma-coherent; + status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart8: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, + <&qup_uart8_tx>, <&qup_uart8_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa84000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa84000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart9: serial@a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa84000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, + <&qup_uart9_tx>, <&qup_uart9_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa88000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa88000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart10: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa88000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, + <&qup_uart10_tx>, <&qup_uart10_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa8c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart11: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa8c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa90000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa90000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart12: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa90000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, + <&qup_uart12_tx>, <&qup_uart12_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa94000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c13_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa94000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart13: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa94000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, + <&qup_uart13_tx>, <&qup_uart13_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa98000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c14_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa98000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart14: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa98000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, + <&qup_uart14_tx>, <&qup_uart14_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa9c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c15_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa9c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart15: serial@a9c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa9c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, + <&qup_uart15_tx>, <&qup_uart15_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + status = "disabled"; + }; + }; + + gpi_dma3: dma-controller@b00000 { + compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0xb00000 0x0 0x60000>; + #dma-cells = <3>; + interrupts = , + , + , + ; + iommus = <&apps_smmu 0x56 0x0>; + dma-channels = <4>; + dma-channel-mask = <0xf>; + dma-coherent; + status = "disabled"; + }; + + qupv3_id_3: geniqup@bc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xbc0000 0x0 0x2000>; + ranges; + clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu 0x43 0x0>; + dma-coherent; + status = "disabled"; + + i2c16: i2c@b80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xb80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c16_data_clk>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, + <&gpi_dma3 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + spi16: spi@b80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xb80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, + <&gpi_dma3 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; + }; + + uart16: serial@b80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xb80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>, + <&qup_uart16_tx>, <&qup_uart16_rx>; + pinctrl-names = "default"; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; }; @@ -3060,11 +4307,630 @@ tlmm: pinctrl@f100000 { #interrupt-cells = <2>; wakeup-parent = <&pdc>; - qup_uart7_default: qup-uart7-state { - /* TX, RX */ - pins = "gpio43", "gpio44"; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + pins = "gpio17", "gpio18"; + function = "qup0_se0"; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + pins = "gpio19", "gpio20"; + function = "qup0_se1"; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + pins = "gpio33", "gpio34"; + function = "qup0_se2"; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + pins = "gpio25", "gpio26"; + function = "qup0_se3"; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + pins = "gpio29", "gpio30"; + function = "qup0_se4"; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + pins = "gpio21", "gpio22"; + function = "qup0_se5"; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + pins = "gpio80", "gpio81"; + function = "qup0_se6"; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + pins = "gpio37", "gpio38"; + function = "qup1_se0"; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + pins = "gpio39", "gpio40"; + function = "qup1_se1"; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + pins = "gpio84", "gpio85"; + function = "qup1_se2"; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + pins = "gpio41", "gpio42"; + function = "qup1_se3"; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + pins = "gpio45", "gpio46"; + function = "qup1_se4"; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + pins = "gpio49", "gpio50"; + function = "qup1_se5"; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + pins = "gpio89", "gpio90"; + function = "qup1_se6"; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + pins = "gpio91", "gpio92"; + function = "qup1_se7"; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + pins = "gpio10", "gpio11"; + function = "qup2_se0"; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + pins = "gpio17", "gpio18", "gpio19"; + function = "qup0_se0"; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio20"; + function = "qup0_se0"; + }; + + qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { + pins = "gpio20"; + function = "gpio"; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + pins = "gpio19", "gpio20", "gpio17"; + function = "qup0_se1"; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio18"; + function = "qup0_se1"; + }; + + qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { + pins = "gpio18"; + function = "gpio"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + pins = "gpio33", "gpio34", "gpio35"; + function = "qup0_se2"; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio36"; + function = "qup0_se2"; + }; + + qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { + pins = "gpio36"; + function = "gpio"; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + pins = "gpio25", "gpio26", "gpio27"; + function = "qup0_se3"; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio28"; + function = "qup0_se3"; + }; + + qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { + pins = "gpio28"; + function = "gpio"; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + pins = "gpio29", "gpio30", "gpio31"; + function = "qup0_se4"; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio32"; + function = "qup0_se4"; + }; + + qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { + pins = "gpio32"; + function = "gpio"; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + pins = "gpio21", "gpio22", "gpio23"; + function = "qup0_se5"; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio24"; + function = "qup0_se5"; + }; + + qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { + pins = "gpio24"; + function = "gpio"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + pins = "gpio80", "gpio81", "gpio82"; + function = "qup0_se6"; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio83"; + function = "qup0_se6"; + }; + + qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { + pins = "gpio83"; + function = "gpio"; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + pins = "gpio37", "gpio38", "gpio39"; + function = "qup1_se0"; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio40"; + function = "qup1_se0"; + }; + + qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { + pins = "gpio40"; + function = "gpio"; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + pins = "gpio39", "gpio40", "gpio37"; + function = "qup1_se1"; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio38"; + function = "qup1_se1"; + }; + + qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { + pins = "gpio38"; + function = "gpio"; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + pins = "gpio84", "gpio85", "gpio86"; + function = "qup1_se2"; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio87"; + function = "qup1_se2"; + }; + + qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { + pins = "gpio87"; + function = "gpio"; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + pins = "gpio45", "gpio46", "gpio47"; + function = "qup1_se4"; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio48"; + function = "qup1_se4"; + }; + + qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { + pins = "gpio48"; + function = "gpio"; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + pins = "gpio49", "gpio50", "gpio51"; + function = "qup1_se5"; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio52"; + function = "qup1_se5"; + }; + + qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { + pins = "gpio52"; + function = "gpio"; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + pins = "gpio89", "gpio90", "gpio91"; + function = "qup1_se6"; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio92"; + function = "qup1_se6"; + }; + + qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { + pins = "gpio92"; + function = "gpio"; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + pins = "gpio91", "gpio92", "gpio89"; + function = "qup1_se7"; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio90"; + function = "qup1_se7"; + }; + + qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { + pins = "gpio90"; + function = "gpio"; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + pins = "gpio10", "gpio11", "gpio12"; + function = "qup2_se0"; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins = "gpio13"; + function = "qup2_se0"; + }; + + qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { + pins = "gpio13"; + function = "gpio"; + }; + + qup_uart0_cts: qup-uart0-cts-state { + pins = "gpio17"; + function = "qup0_se0"; + }; + + qup_uart0_rts: qup-uart0-rts-state { + pins = "gpio18"; + function = "qup0_se0"; + }; + + qup_uart0_tx: qup-uart0-tx-state { + pins = "gpio19"; + function = "qup0_se0"; + }; + + qup_uart0_rx: qup-uart0-rx-state { + pins = "gpio20"; + function = "qup0_se0"; + }; + + qup_uart1_cts: qup-uart1-cts-state { + pins = "gpio19"; + function = "qup0_se1"; + }; + + qup_uart1_rts: qup-uart1-rts-state { + pins = "gpio20"; + function = "qup0_se1"; + }; + + qup_uart1_tx: qup-uart1-tx-state { + pins = "gpio17"; + function = "qup0_se1"; + }; + + qup_uart1_rx: qup-uart1-rx-state { + pins = "gpio18"; + function = "qup0_se1"; + }; + + qup_uart2_cts: qup-uart2-cts-state { + pins = "gpio33"; + function = "qup0_se2"; + }; + + qup_uart2_rts: qup-uart2-rts-state { + pins = "gpio34"; + function = "qup0_se2"; + }; + + qup_uart2_tx: qup-uart2-tx-state { + pins = "gpio35"; + function = "qup0_se2"; + }; + + qup_uart2_rx: qup-uart2-rx-state { + pins = "gpio36"; + function = "qup0_se2"; + }; + + qup_uart3_cts: qup-uart3-cts-state { + pins = "gpio25"; + function = "qup0_se3"; + }; + + qup_uart3_rts: qup-uart3-rts-state { + pins = "gpio26"; + function = "qup0_se3"; + }; + + qup_uart3_tx: qup-uart3-tx-state { + pins = "gpio27"; + function = "qup0_se3"; + }; + + qup_uart3_rx: qup-uart3-rx-state { + pins = "gpio28"; + function = "qup0_se3"; + }; + + qup_uart4_cts: qup-uart4-cts-state { + pins = "gpio29"; + function = "qup0_se4"; + }; + + qup_uart4_rts: qup-uart4-rts-state { + pins = "gpio30"; + function = "qup0_se4"; + }; + + qup_uart4_tx: qup-uart4-tx-state { + pins = "gpio31"; + function = "qup0_se4"; + }; + + qup_uart4_rx: qup-uart4-rx-state { + pins = "gpio32"; + function = "qup0_se4"; + }; + + qup_uart5_cts: qup-uart5-cts-state { + pins = "gpio21"; + function = "qup0_se5"; + }; + + qup_uart5_rts: qup-uart5-rts-state { + pins = "gpio22"; + function = "qup0_se5"; + }; + + qup_uart5_tx: qup-uart5-tx-state { + pins = "gpio23"; + function = "qup0_se5"; + }; + + qup_uart5_rx: qup-uart5-rx-state { + pins = "gpio23"; + function = "qup0_se5"; + }; + + qup_uart6_cts: qup-uart6-cts-state { + pins = "gpio80"; + function = "qup0_se6"; + }; + + qup_uart6_rts: qup-uart6-rts-state { + pins = "gpio81"; + function = "qup0_se6"; + }; + + qup_uart6_tx: qup-uart6-tx-state { + pins = "gpio82"; + function = "qup0_se6"; + }; + + qup_uart6_rx: qup-uart6-rx-state { + pins = "gpio83"; + function = "qup0_se6"; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins = "gpio43"; function = "qup0_se7"; }; + + qup_uart7_rx: qup-uart7-rx-state { + pins = "gpio44"; + function = "qup0_se7"; + }; + + qup_uart8_cts: qup-uart8-cts-state { + pins = "gpio37"; + function = "qup1_se0"; + }; + + qup_uart8_rts: qup-uart8-rts-state { + pins = "gpio38"; + function = "qup1_se0"; + }; + + qup_uart8_tx: qup-uart8-tx-state { + pins = "gpio39"; + function = "qup1_se0"; + }; + + qup_uart8_rx: qup-uart8-rx-state { + pins = "gpio40"; + function = "qup1_se0"; + }; + + qup_uart9_cts: qup-uart9-cts-state { + pins = "gpio39"; + function = "qup1_se1"; + }; + + qup_uart9_rts: qup-uart9-rts-state { + pins = "gpio40"; + function = "qup1_se1"; + }; + + qup_uart9_tx: qup-uart9-tx-state { + pins = "gpio37"; + function = "qup1_se1"; + }; + + qup_uart9_rx: qup-uart9-rx-state { + pins = "gpio38"; + function = "qup1_se1"; + }; + + qup_uart10_cts: qup-uart10-cts-state { + pins = "gpio84"; + function = "qup1_se2"; + }; + + qup_uart10_rts: qup-uart10-rts-state { + pins = "gpio84"; + function = "qup1_se2"; + }; + + qup_uart10_tx: qup-uart10-tx-state { + pins = "gpio85"; + function = "qup1_se2"; + }; + + qup_uart10_rx: qup-uart10-rx-state { + pins = "gpio87"; + function = "qup1_se2"; + }; + + qup_uart11_tx: qup-uart11-tx-state { + pins = "gpio41"; + function = "qup1_se3"; + }; + + qup_uart11_rx: qup-uart11-rx-state { + pins = "gpio42"; + function = "qup1_se3"; + }; + + qup_uart12_cts: qup-uart12-cts-state { + pins = "gpio45"; + function = "qup1_se4"; + }; + + qup_uart12_rts: qup-uart12-rts-state { + pins = "gpio46"; + function = "qup1_se4"; + }; + + qup_uart12_tx: qup-uart12-tx-state { + pins = "gpio47"; + function = "qup1_se4"; + }; + + qup_uart12_rx: qup-uart12-rx-state { + pins = "gpio48"; + function = "qup1_se4"; + }; + + qup_uart13_cts: qup-uart13-cts-state { + pins = "gpio49"; + function = "qup1_se5"; + }; + + qup_uart13_rts: qup-uart13-rts-state { + pins = "gpio50"; + function = "qup1_se5"; + }; + + qup_uart13_tx: qup-uart13-tx-state { + pins = "gpio51"; + function = "qup1_se5"; + }; + + qup_uart13_rx: qup-uart13-rx-state { + pins = "gpio52"; + function = "qup1_se5"; + }; + + qup_uart14_cts: qup-uart14-cts-state { + pins = "gpio89"; + function = "qup1_se6"; + }; + + qup_uart14_rts: qup-uart14-rts-state { + pins = "gpio90"; + function = "qup1_se6"; + }; + + qup_uart14_tx: qup-uart14-tx-state { + pins = "gpio91"; + function = "qup1_se6"; + }; + + qup_uart14_rx: qup-uart14-rx-state { + pins = "gpio92"; + function = "qup1_se6"; + }; + + qup_uart15_cts: qup-uart15-cts-state { + pins = "gpio91"; + function = "qup1_se7"; + }; + + qup_uart15_rts: qup-uart15-rts-state { + pins = "gpio92"; + function = "qup1_se7"; + }; + + qup_uart15_tx: qup-uart15-tx-state { + pins = "gpio89"; + function = "qup1_se7"; + }; + + qup_uart15_rx: qup-uart15-rx-state { + pins = "gpio90"; + function = "qup1_se7"; + }; + + qup_uart16_cts: qup-uart16-cts-state { + pins = "gpio10"; + function = "qup2_se0"; + }; + + qup_uart16_rts: qup-uart16-rts-state { + pins = "gpio11"; + function = "qup2_se0"; + }; + + qup_uart16_tx: qup-uart16-tx-state { + pins = "gpio12"; + function = "qup2_se0"; + }; + + qup_uart16_rx: qup-uart16-rx-state { + pins = "gpio13"; + function = "qup2_se0"; + }; }; sram: sram@146d8000 { From 62ca6669d62eb554eb467f2953cabb4238e18823 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Feb 2025 15:43:23 +0100 Subject: [PATCH 029/308] arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets Asserting the NOCSR reset line keeps the PHY registers in tact. This allows us to avoid programming long tables of magic values in the operating system. Wire up these resets to PCIe PHY4 and 5 (it's there on the others). Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-4-72cd4cdc767b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index b927a7772701..62fa05210f68 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3558,8 +3558,10 @@ pcie5_phy: phy@1c06000 { "pipe", "pipediv2"; - resets = <&gcc GCC_PCIE_5_PHY_BCR>; - reset-names = "phy"; + resets = <&gcc GCC_PCIE_5_PHY_BCR>, + <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; @@ -3692,8 +3694,10 @@ pcie4_phy: phy@1c0e000 { "pipe", "pipediv2"; - resets = <&gcc GCC_PCIE_4_PHY_BCR>; - reset-names = "phy"; + resets = <&gcc GCC_PCIE_4_PHY_BCR>, + <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; From fbf5e007588f3f2bace84309b4a0d428ad619322 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Feb 2025 15:43:24 +0100 Subject: [PATCH 030/308] arm64: dts: qcom: Commonize X1 CRD DTSI Certain X1 SKUs vary very noticeably, but the CRDs based on them don't. Commonize the existing X1E80100 DTSI to allow reuse. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-5-72cd4cdc767b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 1275 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 1270 +------------------- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 3 files changed, 1279 insertions(+), 1268 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/x1-crd.dtsi diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi new file mode 100644 index 000000000000..296b41409ad1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -0,0 +1,1275 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "x1e80100-pmics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. X1E80100 CRD"; + compatible = "qcom,x1e80100-crd", "qcom,x1e80100"; + + aliases { + serial0 = &uart21; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + /* Left-side rear port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + /* Left-side front port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + + /* Right-side port */ + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-CRD"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&nvme_reg_en>; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "SDX_VPH_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna45af01", "samsung,atna33xc20"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie5 { + perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie6a_default>; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; /* 1.8V */ + input-disable; + output-enable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie5_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wwan_sw_en: wwan-sw-en-state { + pins = "gpio221"; + function = "gpio"; + drive-strength = <4>; + bias-disable; + }; +}; + +&uart21 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&pmic_glink_ss2_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index ff5b3472fafd..976b8e44b576 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -5,1278 +5,14 @@ /dts-v1/; -#include -#include -#include -#include -#include - #include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "x1-crd.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 CRD"; compatible = "qcom,x1e80100-crd", "qcom,x1e80100"; - - aliases { - serial0 = &uart21; - }; - - wcd938x: audio-codec { - compatible = "qcom,wcd9385-codec"; - - pinctrl-names = "default"; - pinctrl-0 = <&wcd_default>; - - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - - reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; - - vdd-buck-supply = <&vreg_l15b_1p8>; - vdd-rxtx-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l15b_1p8>; - vdd-mic-bias-supply = <&vreg_bob1>; - - #sound-dai-cells = <1>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&hall_int_n_default>; - pinctrl-names = "default"; - - switch-lid { - gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - wakeup-event-action = ; - }; - }; - - pmic-glink { - compatible = "qcom,x1e80100-pmic-glink", - "qcom,sm8550-pmic-glink", - "qcom,pmic-glink"; - #address-cells = <1>; - #size-cells = <0>; - orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, - <&tlmm 123 GPIO_ACTIVE_HIGH>, - <&tlmm 125 GPIO_ACTIVE_HIGH>; - - /* Left-side rear port */ - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss0_hs_in: endpoint { - remote-endpoint = <&usb_1_ss0_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; - }; - }; - }; - }; - - /* Left-side front port */ - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss1_hs_in: endpoint { - remote-endpoint = <&usb_1_ss1_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; - }; - }; - }; - }; - - /* Right-side port */ - connector@2 { - compatible = "usb-c-connector"; - reg = <2>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss2_hs_in: endpoint { - remote-endpoint = <&usb_1_ss2_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss2_ss_in: endpoint { - remote-endpoint = <&usb_1_ss2_qmpphy_out>; - }; - }; - }; - }; - }; - - reserved-memory { - linux,cma { - compatible = "shared-dma-pool"; - size = <0x0 0x8000000>; - reusable; - linux,cma-default; - }; - }; - - sound { - compatible = "qcom,x1e80100-sndcard"; - model = "X1E80100-CRD"; - audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", - "TweeterLeft IN", "WSA WSA_SPK2 OUT", - "WooferRight IN", "WSA2 WSA_SPK2 OUT", - "TweeterRight IN", "WSA2 WSA_SPK2 OUT", - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "AMIC2", "MIC BIAS2", - "VA DMIC0", "MIC BIAS3", - "VA DMIC1", "MIC BIAS3", - "VA DMIC2", "MIC BIAS1", - "VA DMIC3", "MIC BIAS1", - "VA DMIC0", "VA MIC BIAS3", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", - "VA DMIC3", "VA MIC BIAS1", - "TX SWR_INPUT1", "ADC2_OUTPUT"; - - wcd-playback-dai-link { - link-name = "WCD Playback"; - - cpu { - sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - wcd-capture-dai-link { - link-name = "WCD Capture"; - - cpu { - sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; - }; - - codec { - sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - wsa-dai-link { - link-name = "WSA Playback"; - - cpu { - sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&left_woofer>, <&left_tweeter>, - <&swr0 0>, <&lpass_wsamacro 0>, - <&right_woofer>, <&right_tweeter>, - <&swr3 0>, <&lpass_wsa2macro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - va-dai-link { - link-name = "VA Capture"; - - cpu { - sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; - }; - - codec { - sound-dai = <&lpass_vamacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - }; - - vreg_edp_3p3: regulator-edp-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_EDP_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&edp_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_misc_3p3: regulator-misc-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_MISC_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&misc_3p3_reg_en>; - - regulator-boot-on; - regulator-always-on; - }; - - vreg_nvme: regulator-nvme { - compatible = "regulator-fixed"; - - regulator-name = "VREG_NVME_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&nvme_reg_en>; - - regulator-boot-on; - }; - - vph_pwr: regulator-vph-pwr { - compatible = "regulator-fixed"; - - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - - regulator-always-on; - regulator-boot-on; - }; - - vreg_wwan: regulator-wwan { - compatible = "regulator-fixed"; - - regulator-name = "SDX_VPH_PWR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&wwan_sw_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; }; -&apps_rsc { - regulators-0 { - compatible = "qcom,pm8550-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob1-supply = <&vph_pwr>; - vdd-bob2-supply = <&vph_pwr>; - vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; - vdd-l2-l13-l14-supply = <&vreg_bob1>; - vdd-l5-l16-supply = <&vreg_bob1>; - vdd-l6-l7-supply = <&vreg_bob2>; - vdd-l8-l9-supply = <&vreg_bob1>; - vdd-l12-supply = <&vreg_s5j_1p2>; - vdd-l15-supply = <&vreg_s4c_1p8>; - vdd-l17-supply = <&vreg_bob2>; - - vreg_bob1: bob1 { - regulator-name = "vreg_bob1"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - - vreg_bob2: bob2 { - regulator-name = "vreg_bob2"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l1b_1p8: ldo1 { - regulator-name = "vreg_l1b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2b_3p0: ldo2 { - regulator-name = "vreg_l2b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3100000>; - regulator-initial-mode = ; - }; - - vreg_l4b_1p8: ldo4 { - regulator-name = "vreg_l4b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l5b_3p0: ldo5 { - regulator-name = "vreg_l5b_3p0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = ; - }; - - vreg_l6b_1p8: ldo6 { - regulator-name = "vreg_l6b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l7b_2p8: ldo7 { - regulator-name = "vreg_l7b_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = ; - }; - - vreg_l8b_3p0: ldo8 { - regulator-name = "vreg_l8b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l9b_2p9: ldo9 { - regulator-name = "vreg_l9b_2p9"; - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l10b_1p8: ldo10 { - regulator-name = "vreg_l10b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l12b_1p2: ldo12 { - regulator-name = "vreg_l12b_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l13b_3p0: ldo13 { - regulator-name = "vreg_l13b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3100000>; - regulator-initial-mode = ; - }; - - vreg_l14b_3p0: ldo14 { - regulator-name = "vreg_l14b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l15b_1p8: ldo15 { - regulator-name = "vreg_l15b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l16b_2p9: ldo16 { - regulator-name = "vreg_l16b_2p9"; - regulator-min-microvolt = <2912000>; - regulator-max-microvolt = <2912000>; - regulator-initial-mode = ; - }; - - vreg_l17b_2p5: ldo17 { - regulator-name = "vreg_l17b_2p5"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2504000>; - regulator-initial-mode = ; - }; - }; - - regulators-1 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s4-supply = <&vph_pwr>; - - vreg_s4c_1p8: smps4 { - regulator-name = "vreg_s4c_1p8"; - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_l1c_1p2: ldo1 { - regulator-name = "vreg_l1c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l2c_0p8: ldo2 { - regulator-name = "vreg_l2c_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l3c_0p8: ldo3 { - regulator-name = "vreg_l3c_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - }; - - regulators-2 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "d"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s4c_1p8>; - vdd-s1-supply = <&vph_pwr>; - - vreg_l1d_0p8: ldo1 { - regulator-name = "vreg_l1d_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l2d_0p9: ldo2 { - regulator-name = "vreg_l2d_0p9"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l3d_1p8: ldo3 { - regulator-name = "vreg_l3d_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - regulators-3 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "e"; - - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s5j_1p2>; - - vreg_l2e_0p8: ldo2 { - regulator-name = "vreg_l2e_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l3e_1p2: ldo3 { - regulator-name = "vreg_l3e_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; - - regulators-4 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s5j_1p2>; - vdd-s1-supply = <&vph_pwr>; - - vreg_s1f_0p7: smps1 { - regulator-name = "vreg_s1f_0p7"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = ; - }; - - vreg_l1f_1p0: ldo1 { - regulator-name = "vreg_l1f_1p0"; - regulator-min-microvolt = <1024000>; - regulator-max-microvolt = <1024000>; - regulator-initial-mode = ; - }; - - vreg_l2f_1p0: ldo2 { - regulator-name = "vreg_l2f_1p0"; - regulator-min-microvolt = <1024000>; - regulator-max-microvolt = <1024000>; - regulator-initial-mode = ; - }; - - vreg_l3f_1p0: ldo3 { - regulator-name = "vreg_l3f_1p0"; - regulator-min-microvolt = <1024000>; - regulator-max-microvolt = <1024000>; - regulator-initial-mode = ; - }; - }; - - regulators-6 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "i"; - - vdd-l1-supply = <&vreg_s4c_1p8>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - - vreg_s1i_0p9: smps1 { - regulator-name = "vreg_s1i_0p9"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_s2i_1p0: smps2 { - regulator-name = "vreg_s2i_1p0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = ; - }; - - vreg_l1i_1p8: ldo1 { - regulator-name = "vreg_l1i_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2i_1p2: ldo2 { - regulator-name = "vreg_l2i_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3i_0p8: ldo3 { - regulator-name = "vreg_l3i_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - }; - - regulators-7 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "j"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s5-supply = <&vph_pwr>; - - vreg_s5j_1p2: smps5 { - regulator-name = "vreg_s5j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l1j_0p8: ldo1 { - regulator-name = "vreg_l1j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l2j_1p2: ldo2 { - regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3j_0p8: ldo3 { - regulator-name = "vreg_l3j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - }; -}; - -&gpu { - status = "okay"; - - zap-shader { - firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - - status = "okay"; - - touchpad@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l12b_1p2>; - - pinctrl-0 = <&tpad_default>; - pinctrl-names = "default"; - - wakeup-source; - }; - - keyboard@3a { - compatible = "hid-over-i2c"; - reg = <0x3a>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l12b_1p2>; - - pinctrl-0 = <&kybd_default>; - pinctrl-names = "default"; - - wakeup-source; - }; -}; - -&i2c8 { - clock-frequency = <400000>; - - status = "okay"; - - touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_1p8>; - - pinctrl-0 = <&ts0_default>; - pinctrl-names = "default"; - }; -}; - -&lpass_tlmm { - spkr_01_sd_n_active: spkr-01-sd-n-active-state { - pins = "gpio12"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-low; - }; - - spkr_23_sd_n_active: spkr-23-sd-n-active-state { - pins = "gpio13"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-low; - }; -}; - -&lpass_vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic23_default>; - pinctrl-names = "default"; - - vdd-micb-supply = <&vreg_l1b_1p8>; - qcom,dmic-sample-rate = <4800000>; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dp3 { - compatible = "qcom,x1e80100-dp"; - /delete-property/ #sound-dai-cells; - - status = "okay"; - - aux-bus { - panel { - compatible = "samsung,atna45af01", "samsung,atna33xc20"; - enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; - power-supply = <&vreg_edp_3p3>; - - pinctrl-0 = <&edp_bl_en>; - pinctrl-names = "default"; - - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss_dp3_out>; - }; - }; - }; - }; - - ports { - port@1 { - reg = <1>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; - }; - }; - }; -}; - -&mdss_dp3_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&pcie4_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie4_phy { - vdda-phy-supply = <&vreg_l3i_0p8>; - vdda-pll-supply = <&vreg_l3e_1p2>; - - status = "okay"; -}; - -&pcie5 { - perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - - vddpe-3v3-supply = <&vreg_wwan>; - - pinctrl-0 = <&pcie5_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie5_phy { - vdda-phy-supply = <&vreg_l3i_0p8>; - vdda-pll-supply = <&vreg_l3e_1p2>; - - status = "okay"; -}; - -&pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - - vddpe-3v3-supply = <&vreg_nvme>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie6a_default>; - - status = "okay"; -}; - -&pcie6a_phy { - vdda-phy-supply = <&vreg_l1d_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pm8550ve_8_gpios { - misc_3p3_reg_en: misc-3p3-reg-en-state { - pins = "gpio6"; - function = "normal"; - bias-disable; - input-disable; - output-enable; - drive-push-pull; - power-source = <1>; /* 1.8 V */ - qcom,drive-strength = ; - }; -}; - -&pmc8380_3_gpios { - edp_bl_en: edp-bl-en-state { - pins = "gpio4"; - function = "normal"; - power-source = <1>; /* 1.8V */ - input-disable; - output-enable; - }; -}; - -&qupv3_0 { - status = "okay"; -}; - -&qupv3_1 { - status = "okay"; -}; - -&qupv3_2 { - status = "okay"; -}; - -&remoteproc_adsp { - firmware-name = "qcom/x1e80100/adsp.mbn", - "qcom/x1e80100/adsp_dtb.mbn"; - - status = "okay"; -}; - -&remoteproc_cdsp { - firmware-name = "qcom/x1e80100/cdsp.mbn", - "qcom/x1e80100/cdsp_dtb.mbn"; - - status = "okay"; -}; - -&smb2360_0 { - status = "okay"; -}; - -&smb2360_0_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l2b_3p0>; -}; - -&smb2360_1 { - status = "okay"; -}; - -&smb2360_1_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l14b_3p0>; -}; - -&smb2360_2 { - status = "okay"; -}; - -&smb2360_2_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l8b_3p0>; -}; - -&swr0 { - status = "okay"; - - pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; - pinctrl-names = "default"; - - /* WSA8845, Left Woofer */ - left_woofer: speaker@0,0 { - compatible = "sdw20217020400"; - reg = <0 0>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "WooferLeft"; - vdd-1p8-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l12b_1p2>; - qcom,port-mapping = <1 2 3 7 10 13>; - }; - - /* WSA8845, Left Tweeter */ - left_tweeter: speaker@0,1 { - compatible = "sdw20217020400"; - reg = <0 1>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "TweeterLeft"; - vdd-1p8-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l12b_1p2>; - qcom,port-mapping = <4 5 6 7 11 13>; - }; -}; - -&swr1 { - status = "okay"; - - /* WCD9385 RX */ - wcd_rx: codec@0,4 { - compatible = "sdw20217010d00"; - reg = <0 4>; - qcom,rx-port-mapping = <1 2 3 4 5>; - }; -}; - -&swr2 { - status = "okay"; - - /* WCD9385 TX */ - wcd_tx: codec@0,3 { - compatible = "sdw20217010d00"; - reg = <0 3>; - qcom,tx-port-mapping = <2 2 3 4>; - }; -}; - -&swr3 { - status = "okay"; - - pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; - pinctrl-names = "default"; - - /* WSA8845, Right Woofer */ - right_woofer: speaker@0,0 { - compatible = "sdw20217020400"; - reg = <0 0>; - reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "WooferRight"; - vdd-1p8-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l12b_1p2>; - qcom,port-mapping = <1 2 3 7 10 13>; - }; - - /* WSA8845, Right Tweeter */ - right_tweeter: speaker@0,1 { - compatible = "sdw20217020400"; - reg = <0 1>; - reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "TweeterRight"; - vdd-1p8-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l12b_1p2>; - qcom,port-mapping = <4 5 6 7 11 13>; - }; -}; - -&tlmm { - gpio-reserved-ranges = <34 2>, /* Unused */ - <44 4>, /* SPI (TPM) */ - <238 1>; /* UFS Reset */ - - edp_reg_en: edp-reg-en-state { - pins = "gpio70"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - hall_int_n_default: hall-int-n-state { - pins = "gpio92"; - function = "gpio"; - bias-disable; - }; - - kybd_default: kybd-default-state { - pins = "gpio67"; - function = "gpio"; - bias-disable; - }; - - nvme_reg_en: nvme-reg-en-state { - pins = "gpio18"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins = "gpio147"; - function = "pcie4_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio146"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio148"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie5_default: pcie5-default-state { - clkreq-n-pins { - pins = "gpio150"; - function = "pcie5_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio149"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio151"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie6a_default: pcie6a-default-state { - clkreq-n-pins { - pins = "gpio153"; - function = "pcie6a_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio152"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio154"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - tpad_default: tpad-default-state { - pins = "gpio3"; - function = "gpio"; - bias-disable; - }; - - ts0_default: ts0-default-state { - int-n-pins { - pins = "gpio51"; - function = "gpio"; - bias-disable; - }; - - reset-n-pins { - pins = "gpio48"; - function = "gpio"; - output-high; - drive-strength = <16>; - }; - }; - - wcd_default: wcd-reset-n-active-state { - pins = "gpio191"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-low; - }; - - wwan_sw_en: wwan-sw-en-state { - pins = "gpio221"; - function = "gpio"; - drive-strength = <4>; - bias-disable; - }; -}; - -&uart21 { - compatible = "qcom,geni-debug-uart"; - status = "okay"; -}; - -&usb_1_ss0_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_0_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; - - status = "okay"; -}; - -&usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss0_dwc3_hs { - remote-endpoint = <&pmic_glink_ss0_hs_in>; -}; - -&usb_1_ss0_qmpphy_out { - remote-endpoint = <&pmic_glink_ss0_ss_in>; -}; - -&usb_1_ss1_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_1_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; - - status = "okay"; -}; - -&usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss1_dwc3_hs { - remote-endpoint = <&pmic_glink_ss1_hs_in>; -}; - -&usb_1_ss1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss1_ss_in>; -}; - -&usb_1_ss2_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_2_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; - - status = "okay"; -}; - -&usb_1_ss2 { - status = "okay"; -}; - -&usb_1_ss2_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss2_dwc3_hs { - remote-endpoint = <&pmic_glink_ss2_hs_in>; -}; - -&usb_1_ss2_qmpphy_out { - remote-endpoint = <&pmic_glink_ss2_ss_in>; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 62fa05210f68..ae27e147febf 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3751,7 +3751,7 @@ gpu: gpu@3d00000 { status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&gpu_microcode_mem>; }; From f08edb5299166b7c6d4eae439b1d3f81c31ba50e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Feb 2025 15:43:25 +0100 Subject: [PATCH 031/308] arm64: dts: qcom: Add X1P42100 SoC and CRD The X1 family is split into two parts: the 10- and 12-core parts are variants of the same silicon with different fusing, whereas the 8-core ones are a separate design. Thankfully, the software interface is only barely different, letting us reuse much of the existing X1 work. Introduce support for the X1P42100 SoC and the CRD based on it, through overlaying some bits. Everything we already support on X1E80100 and friends, minus the GPU, should work as-is. Tested-by: Jens Glathe Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-6-72cd4cdc767b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 2 +- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 ++++---- arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 17 ++++ arch/arm64/boot/dts/qcom/x1p42100.dtsi | 81 ++++++++++++++++++++ 5 files changed, 115 insertions(+), 16 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/x1p42100-crd.dts create mode 100644 arch/arm64/boot/dts/qcom/x1p42100.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 140b0b2abfb5..b54f45b3bec8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -298,3 +298,4 @@ dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi index d7a2a2b8fc6c..bf6cdede156b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -110,7 +110,7 @@ trip1 { }; }; - pmc8380-6-thermal { + pmc8380_6_thermal: pmc8380-6-thermal { polling-delay-passive = <100>; thermal-sensors = <&pmc8380_6_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index ae27e147febf..5c091e234ca3 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -252,7 +252,7 @@ core3 { }; }; - cluster2 { + cpu_map_cluster2: cluster2 { core0 { cpu = <&cpu8>; }; @@ -8212,7 +8212,7 @@ opp-9 { }; /* cluster0 */ - pmu@240b3400 { + bwmon_cluster0: pmu@240b3400 { compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b3400 0 0x600>; @@ -8222,6 +8222,19 @@ pmu@240b3400 { &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + + /* cluster2 */ + bwmon_cluster2: pmu@240b5400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b5400 0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; cpu_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; @@ -8252,19 +8265,6 @@ opp-5 { }; }; - /* cluster2 */ - pmu@240b5400 { - compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; - reg = <0 0x240b5400 0 0x600>; - - interrupts = ; - - interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; - - operating-points-v2 = <&cpu_bwmon_opp_table>; - }; - /* cluster1 */ pmu@240b6400 { compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts new file mode 100644 index 000000000000..cf07860a63e9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "x1p42100.dtsi" +#include "x1-crd.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Qualcomm Technologies, Inc. X1P42100 CRD"; + compatible = "qcom,x1p42100-crd", "qcom,x1p42100"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi new file mode 100644 index 000000000000..27f479010bc3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* X1P42100 is heavily based on X1E80100, with some meaningful differences */ +#include "x1e80100.dtsi" + +/delete-node/ &bwmon_cluster0; +/delete-node/ &cluster_pd2; +/delete-node/ &cpu_map_cluster2; +/delete-node/ &cpu8; +/delete-node/ &cpu9; +/delete-node/ &cpu10; +/delete-node/ &cpu11; +/delete-node/ &cpu_pd8; +/delete-node/ &cpu_pd9; +/delete-node/ &cpu_pd10; +/delete-node/ &cpu_pd11; +/delete-node/ &pcie3_phy; + +&gcc { + compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; +}; + +/* The GPU is physically different and will be brought up later */ +&gpu { + /delete-property/ compatible; +}; + +&gpucc { + compatible = "qcom,x1p42100-gpucc"; +}; + +/* PCIe3 has half the lanes compared to X1E80100 */ +&pcie3 { + num-lanes = <4>; +}; + +&pcie6a_phy { + compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; +}; + +&soc { + /* The PCIe3 PHY on X1P42100 uses a different IP block */ + pcie3_phy: phy@1bd4000 { + compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; + reg = <0x0 0x01bd4000 0x0 0x2000>, + <0x0 0x01bd6000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_8L_CLKREF_EN>, + <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3_PIPE_CLK>, + <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_3_PHY_BCR>, + <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie3_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; +}; From 7f9a670396029116424a803d3971ff0e552ff0b3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 3 Feb 2025 14:23:17 +0100 Subject: [PATCH 032/308] arm64: dts: qcom: sm8650: drop cpu thermal passive trip points On the SM8650, the dynamic clock and voltage scaling (DCVS) is done in an hardware controlled loop using the LMH and EPSS blocks with constraints and OPPs programmed in the board firmware. Since the Hardware does a better job at maintaining the CPUs temperature in an acceptable range by taking in account more parameters like the die characteristics or other factory fused values, it makes no sense to try and reproduce a similar set of constraints with the Linux cpufreq thermal core. In addition, the tsens IP is responsible for monitoring the temperature across the SoC and the current settings will heavily trigger the tsens UP/LOW interrupts if the CPU temperatures reaches the hardware thermal constraints which are currently defined in the DT. And since the CPUs are not hooked in the thermal trip points, the potential interrupts and calculations are a waste of system resources. Drop the current passive trip points and only leave the critical trip point that will trigger a software system reboot before an hardware thermal shutdown in the allmost impossible case the hardware DCVS cannot handle the temperature surge. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250203-topic-sm8650-thermal-cpu-idle-v4-1-65e35f307301@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 180 --------------------------- 1 file changed, 180 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 09cc884f0969..e65380fb5fe6 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -6876,18 +6876,6 @@ cpu2-top-thermal { thermal-sensors = <&tsens0 5>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2-critical { temperature = <110000>; hysteresis = <1000>; @@ -6900,18 +6888,6 @@ cpu2-bottom-thermal { thermal-sensors = <&tsens0 6>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2-critical { temperature = <110000>; hysteresis = <1000>; @@ -6924,18 +6900,6 @@ cpu3-top-thermal { thermal-sensors = <&tsens0 7>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu3-critical { temperature = <110000>; hysteresis = <1000>; @@ -6948,18 +6912,6 @@ cpu3-bottom-thermal { thermal-sensors = <&tsens0 8>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu3-critical { temperature = <110000>; hysteresis = <1000>; @@ -6972,18 +6924,6 @@ cpu4-top-thermal { thermal-sensors = <&tsens0 9>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu4-critical { temperature = <110000>; hysteresis = <1000>; @@ -6996,18 +6936,6 @@ cpu4-bottom-thermal { thermal-sensors = <&tsens0 10>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu4-critical { temperature = <110000>; hysteresis = <1000>; @@ -7020,18 +6948,6 @@ cpu5-top-thermal { thermal-sensors = <&tsens0 11>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu5-critical { temperature = <110000>; hysteresis = <1000>; @@ -7044,18 +6960,6 @@ cpu5-bottom-thermal { thermal-sensors = <&tsens0 12>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu5-critical { temperature = <110000>; hysteresis = <1000>; @@ -7068,18 +6972,6 @@ cpu6-top-thermal { thermal-sensors = <&tsens0 13>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu6-critical { temperature = <110000>; hysteresis = <1000>; @@ -7092,18 +6984,6 @@ cpu6-bottom-thermal { thermal-sensors = <&tsens0 14>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu6-critical { temperature = <110000>; hysteresis = <1000>; @@ -7134,18 +7014,6 @@ cpu7-top-thermal { thermal-sensors = <&tsens1 1>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu7-critical { temperature = <110000>; hysteresis = <1000>; @@ -7158,18 +7026,6 @@ cpu7-middle-thermal { thermal-sensors = <&tsens1 2>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu7-critical { temperature = <110000>; hysteresis = <1000>; @@ -7182,18 +7038,6 @@ cpu7-bottom-thermal { thermal-sensors = <&tsens1 3>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu7-critical { temperature = <110000>; hysteresis = <1000>; @@ -7206,18 +7050,6 @@ cpu0-thermal { thermal-sensors = <&tsens1 4>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0-critical { temperature = <110000>; hysteresis = <1000>; @@ -7230,18 +7062,6 @@ cpu1-thermal { thermal-sensors = <&tsens1 5>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu1-critical { temperature = <110000>; hysteresis = <1000>; From 2250f65b32565eb8b757e89248c75977f370f498 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 3 Feb 2025 14:23:18 +0100 Subject: [PATCH 033/308] arm64: dts: qcom: sm8650: setup gpu thermal with higher temperatures On the SM8650, the dynamic clock and voltage scaling (DCVS) for the GPU is done from the HLOS, but the GPU can achieve a much higher temperature before failing according the reference downstream implementation. Set higher temperatures in the GPU trip points corresponding to the temperatures provided by Qualcomm in the dowstream source, much closer to the junction temperature and with a higher critical temperature trip in the case the HLOS DCVS cannot handle the temperature surge. The tsens MAX_THRESHOLD is set to 120C on those platforms, so set the hot to 110C to leave a chance to HLOS to react and critical to 115C to avoid the monitor thermal shutdown. Fixes: 497624ed5506 ("arm64: dts: qcom: sm8650: Throttle the GPU when overheating") Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250203-topic-sm8650-thermal-cpu-idle-v4-2-65e35f307301@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 64 ++++++++++++++-------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e65380fb5fe6..ce54f4497b3c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -7298,20 +7298,20 @@ map0 { trips { gpu0_alert0: trip-point0 { - temperature = <85000>; + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { - temperature = <90000>; + temperature = <110000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { - temperature = <110000>; - hysteresis = <1000>; + temperature = <115000>; + hysteresis = <0>; type = "critical"; }; }; @@ -7331,20 +7331,20 @@ map0 { trips { gpu1_alert0: trip-point0 { - temperature = <85000>; + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { - temperature = <90000>; + temperature = <110000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { - temperature = <110000>; - hysteresis = <1000>; + temperature = <115000>; + hysteresis = <0>; type = "critical"; }; }; @@ -7364,20 +7364,20 @@ map0 { trips { gpu2_alert0: trip-point0 { - temperature = <85000>; + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { - temperature = <90000>; + temperature = <110000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { - temperature = <110000>; - hysteresis = <1000>; + temperature = <115000>; + hysteresis = <0>; type = "critical"; }; }; @@ -7397,20 +7397,20 @@ map0 { trips { gpu3_alert0: trip-point0 { - temperature = <85000>; + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { - temperature = <90000>; + temperature = <110000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { - temperature = <110000>; - hysteresis = <1000>; + temperature = <115000>; + hysteresis = <0>; type = "critical"; }; }; @@ -7430,20 +7430,20 @@ map0 { trips { gpu4_alert0: trip-point0 { - temperature = <85000>; + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { - temperature = <90000>; + temperature = <110000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { - temperature = <110000>; - hysteresis = <1000>; + temperature = <115000>; + hysteresis = <0>; type = "critical"; }; }; @@ -7463,20 +7463,20 @@ map0 { trips { gpu5_alert0: trip-point0 { - temperature = <85000>; + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { - temperature = <90000>; + temperature = <110000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { - temperature = <110000>; - hysteresis = <1000>; + temperature = <115000>; + hysteresis = <0>; type = "critical"; }; }; @@ -7496,20 +7496,20 @@ map0 { trips { gpu6_alert0: trip-point0 { - temperature = <85000>; + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { - temperature = <90000>; + temperature = <110000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { - temperature = <110000>; - hysteresis = <1000>; + temperature = <115000>; + hysteresis = <0>; type = "critical"; }; }; @@ -7529,20 +7529,20 @@ map0 { trips { gpu7_alert0: trip-point0 { - temperature = <85000>; + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; trip-point1 { - temperature = <90000>; + temperature = <110000>; hysteresis = <1000>; type = "hot"; }; trip-point2 { - temperature = <110000>; - hysteresis = <1000>; + temperature = <115000>; + hysteresis = <0>; type = "critical"; }; }; From c516beb248a96f5a93fb4f9a6cb0dda4155eadbb Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 3 Feb 2025 14:23:19 +0100 Subject: [PATCH 034/308] arm64: dts: qcom: sm8650: harmonize all unregulated thermal trip points While the CPUs thermal is handled by the LMH, and GPU has a passive cooldowm via the HLOS DCVS, all the other thermal blocks only have hot and critical and no passive/active trip points. Passive or active thermal management for those blocks should be either defined if somehow we can express those in DT or in the board definition if there's an active cooling device available. The tsens MAX_THRESHOLD is set to 120C on those platforms, so set the hot to 110C to leave a chance to HLOS to react and critical to 115C to avoid the monitor thermal shutdown. In the case a passive or active cooling device would be available, the downstream reference implementation uses the 95C "tj" trip point, as we already use for the gpuss thermal blocks. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250203-topic-sm8650-thermal-cpu-idle-v4-3-65e35f307301@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 170 +++++++++++++-------------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index ce54f4497b3c..8926c90c131a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -6786,14 +6786,14 @@ aoss0-thermal { thermal-sensors = <&tsens0 0>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + aoss0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; aoss0-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -6804,14 +6804,14 @@ cpuss0-thermal { thermal-sensors = <&tsens0 1>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + cpuss0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; cpuss0-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -6822,14 +6822,14 @@ cpuss1-thermal { thermal-sensors = <&tsens0 2>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + cpuss1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; cpuss1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -6840,14 +6840,14 @@ cpuss2-thermal { thermal-sensors = <&tsens0 3>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + cpuss2-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; cpuss2-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -6858,14 +6858,14 @@ cpuss3-thermal { thermal-sensors = <&tsens0 4>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + cpuss3-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; cpuss3-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -6996,14 +6996,14 @@ aoss1-thermal { thermal-sensors = <&tsens1 0>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + aoss1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; aoss1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7076,14 +7076,14 @@ nsphvx0-thermal { thermal-sensors = <&tsens2 6>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphvx0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; - nsphvx1-critical { - temperature = <110000>; + nsphvx0-critical { + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7096,14 +7096,14 @@ nsphvx1-thermal { thermal-sensors = <&tsens2 7>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphvx1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; nsphvx1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7116,14 +7116,14 @@ nsphmx0-thermal { thermal-sensors = <&tsens2 8>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphmx0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; nsphmx0-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7136,14 +7136,14 @@ nsphmx1-thermal { thermal-sensors = <&tsens2 9>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphmx1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; nsphmx1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7156,14 +7156,14 @@ nsphmx2-thermal { thermal-sensors = <&tsens2 10>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphmx2-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; nsphmx2-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7176,14 +7176,14 @@ nsphmx3-thermal { thermal-sensors = <&tsens2 11>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphmx3-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; nsphmx3-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7196,14 +7196,14 @@ video-thermal { thermal-sensors = <&tsens1 12>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + video-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; video-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7216,14 +7216,14 @@ ddr-thermal { thermal-sensors = <&tsens1 13>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + ddr-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; ddr-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7234,14 +7234,14 @@ camera0-thermal { thermal-sensors = <&tsens1 14>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + camera0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; camera0-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7252,14 +7252,14 @@ camera1-thermal { thermal-sensors = <&tsens1 15>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + camera1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; camera1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7270,14 +7270,14 @@ aoss2-thermal { thermal-sensors = <&tsens2 0>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + aoss2-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; aoss2-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7552,14 +7552,14 @@ modem0-thermal { thermal-sensors = <&tsens2 9>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + modem0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; modem0-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7570,14 +7570,14 @@ modem1-thermal { thermal-sensors = <&tsens2 10>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + modem1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; modem1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7588,14 +7588,14 @@ modem2-thermal { thermal-sensors = <&tsens2 11>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + modem2-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; modem2-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -7606,14 +7606,14 @@ modem3-thermal { thermal-sensors = <&tsens2 12>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + modem3-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; modem3-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; From 30235bb8b0487537ddd7dd4a480c907add6cd19b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 3 Feb 2025 14:23:20 +0100 Subject: [PATCH 035/308] arm64: dts: qcom: sm8650: drop remaining polling-delay-passive properties Remove the remaining polling-delay-passive properties from thermal nodes without a passive trip point. Suggested-by: Konrad Dybcio Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250203-topic-sm8650-thermal-cpu-idle-v4-4-65e35f307301@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 8926c90c131a..de75cd50d5e9 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -7071,8 +7071,6 @@ cpu1-critical { }; nsphvx0-thermal { - polling-delay-passive = <10>; - thermal-sensors = <&tsens2 6>; trips { @@ -7091,8 +7089,6 @@ nsphvx0-critical { }; nsphvx1-thermal { - polling-delay-passive = <10>; - thermal-sensors = <&tsens2 7>; trips { @@ -7111,8 +7107,6 @@ nsphvx1-critical { }; nsphmx0-thermal { - polling-delay-passive = <10>; - thermal-sensors = <&tsens2 8>; trips { @@ -7131,8 +7125,6 @@ nsphmx0-critical { }; nsphmx1-thermal { - polling-delay-passive = <10>; - thermal-sensors = <&tsens2 9>; trips { @@ -7151,8 +7143,6 @@ nsphmx1-critical { }; nsphmx2-thermal { - polling-delay-passive = <10>; - thermal-sensors = <&tsens2 10>; trips { @@ -7171,8 +7161,6 @@ nsphmx2-critical { }; nsphmx3-thermal { - polling-delay-passive = <10>; - thermal-sensors = <&tsens2 11>; trips { @@ -7191,8 +7179,6 @@ nsphmx3-critical { }; video-thermal { - polling-delay-passive = <10>; - thermal-sensors = <&tsens1 12>; trips { @@ -7211,8 +7197,6 @@ video-critical { }; ddr-thermal { - polling-delay-passive = <10>; - thermal-sensors = <&tsens1 13>; trips { From 542b34247f3a5aeb4d094b21522803448005685a Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Mon, 3 Feb 2025 14:14:26 +0300 Subject: [PATCH 036/308] arm64: dts: qcom: sm7325-nothing-spacewar: Add CAM fixed-regulators Two regulators (GPIO 72 & 107) for the IMX766 sensor are missing here. Without a driver, it's unclear if they're extra supplies or pwdn/power GPIOs (labeled "custom" in the downstream kernel). So add only those fixed regulators that are currently predictable for camera sensors, camera EEPROMs and camera actuators. Signed-off-by: Danila Tikhonov Link: https://lore.kernel.org/r/20250203111429.22062-2-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm7325-nothing-spacewar.dts | 125 ++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts index a5cda478bd78..4f964e5d34da 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -253,6 +253,124 @@ vph_pwr: vph-pwr-regulator { regulator-max-microvolt = <3700000>; }; + vreg_cam_vio_1p8: regulator-cam-vio { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam_vio_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* Always-on prevents CCI bus timeouts */ + regulator-always-on; + + vin-supply = <&vreg_bob>; + }; + + vreg_camf_vana_2p8: regulator-camf-vana { + compatible = "regulator-fixed"; + regulator-name = "vreg_camf_vana_2p8"; + + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_camf_vdig_1p1: regulator-camf-vdig { + compatible = "regulator-fixed"; + regulator-name = "vreg_camf_vdig_1p1"; + + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + + gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_s8b_1p256>; + }; + + vreg_camu_vaf_1p8: regulator-camu-vaf { + compatible = "regulator-fixed"; + regulator-name = "vreg_camu_vaf_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 71 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_camu_vana_2p8: regulator-camu-vana { + compatible = "regulator-fixed"; + regulator-name = "vreg_camu_vana_2p8"; + + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&tlmm 68 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_camu_vdig_1p1: regulator-camu-vdig { + compatible = "regulator-fixed"; + regulator-name = "vreg_camu_vdig_1p1"; + + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + + gpio = <&tlmm 50 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_s8b_1p256>; + }; + + vreg_camw_vaf_1p8: regulator-camw-vaf { + compatible = "regulator-fixed"; + regulator-name = "vreg_camw_vaf_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_camw_vana_2p8: regulator-camw-vana { + compatible = "regulator-fixed"; + regulator-name = "vreg_camw_vana_2p8"; + + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&tlmm 79 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_camw_vdig_1p1: regulator-camw-vdig { + compatible = "regulator-fixed"; + regulator-name = "vreg_camw_vdig_1p1"; + + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + + gpio = <&tlmm 108 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_s8b_1p256>; + }; + // S2B is really ebi.lvl but it's there for supply map completeness sake. vreg_s2b_0p7: smpa3-regulator { compatible = "regulator-fixed"; @@ -714,6 +832,13 @@ vreg_bob: bob { }; &cci0 { + /* + * cci0_i2c1 bus is unused and GPIO 71&72 are repurposed. + * So set only cci0_i2c0 pinctrl here. + */ + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + status = "okay"; }; From 588a6d006d640fde038d794bbf8db99a2cc2646f Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Mon, 3 Feb 2025 14:14:29 +0300 Subject: [PATCH 037/308] arm64: dts: qcom: sm7325-nothing-spacewar: Enable camera EEPROMs Configure the EEPROMs which are found on the different camera sensors on this device. The pull-up regulator for these I2C busses is vreg_cam_vio_1p8, the same supply that powers VCC of all the EEPROMs. Signed-off-by: Danila Tikhonov Link: https://lore.kernel.org/r/20250203111429.22062-5-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm7325-nothing-spacewar.dts | 32 +++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts index 4f964e5d34da..0c89f7726865 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -843,7 +843,15 @@ &cci0 { }; &cci0_i2c0 { - /* sony,imx471 (Front) */ + /* D-PHY sony,imx471 (Front) @ 0x1a */ + + camf_p24c64f: eeprom@52 { + compatible = "puya,p24c64f", + "atmel,24c64"; + reg = <0x52>; + vcc-supply = <&vreg_cam_vio_1p8>; + read-only; + }; }; &cci1 { @@ -851,11 +859,29 @@ &cci1 { }; &cci1_i2c0 { - /* samsung,s5kjn1 (Rear-aux UW) */ + /* actuator (For Ultra Wide sensor) @ 0xc */ + /* D-PHY samsung,s5kjn1 (Ultra Wide) @ 0x2d */ + + camu_gt24p128e: eeprom@51 { + compatible = "giantec,gt24p128e", + "atmel,24c128"; + reg = <0x51>; + vcc-supply = <&vreg_cam_vio_1p8>; + read-only; + }; }; &cci1_i2c1 { - /* sony,imx766 (Rear Wide) */ + /* actuator (For Wide sensor) @ 0xc */ + /* C-PHY sony,imx766 (Wide) @ 0x10 */ + + camw_gt24p128e: eeprom@50 { + compatible = "giantec,gt24p128e", + "atmel,24c128"; + reg = <0x50>; + vcc-supply = <&vreg_cam_vio_1p8>; + read-only; + }; }; &gcc { From c365a026155ca926f878dee528715be8a02dabc7 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 2 Feb 2025 23:45:51 +0100 Subject: [PATCH 038/308] arm64: dts: qcom: qcm6490-fairphone-fp5: Enable display Configure the MDSS nodes for the phone and add the panel node. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Marijn Suijten Link: https://lore.kernel.org/r/20250202-fp5-display-v1-1-f52bf546e38f@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcm6490-fairphone-fp5.dts | 94 ++++++++++++++++++- 1 file changed, 89 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 769c66cb5d19..cc4ff2c7a726 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -138,6 +138,34 @@ vreg_ois_dvdd_1p1: regulator-ois-dvdd-1p1 { vin-supply = <&vreg_s8b>; }; + vreg_oled_dvdd: regulator-oled-dvdd { + compatible = "regulator-fixed"; + regulator-name = "oled_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_s1b>; + + regulator-boot-on; + }; + + vreg_oled_vci: regulator-oled-vci { + compatible = "regulator-fixed"; + regulator-name = "oled_vci"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_l13c>; + + regulator-boot-on; + }; + reserved-memory { cont_splash_mem: cont-splash@e1000000 { reg = <0x0 0xe1000000 0x0 0x2300000>; @@ -597,11 +625,6 @@ eeprom@51 { }; }; -&dispcc { - /* Disable for now so simple-framebuffer continues working */ - status = "disabled"; -}; - &gcc { protected-clocks = , , @@ -733,6 +756,46 @@ &ipa { status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi { + vdda-supply = <&vreg_l6b>; + status = "okay"; + + panel@0 { + compatible = "fairphone,fp5-rm692e5-boe", "raydium,rm692e5"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; + + vci-supply = <&vreg_oled_vci>; + vddio-supply = <&vreg_l12c>; + dvdd-supply = <&vreg_oled_dvdd>; + + pinctrl-0 = <&disp_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp_reset_n_suspend>, <&mdp_vsync>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c>; + status = "okay"; +}; + &pm7250b_adc { pinctrl-0 = <&pm7250b_adc_default>; pinctrl-names = "default"; @@ -1015,6 +1078,20 @@ bluetooth_enable_default: bluetooth-enable-default-state { bias-disable; }; + disp_reset_n_active: disp-reset-n-active-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp_reset_n_suspend: disp-reset-n-suspend-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + hall_sensor_default: hall-sensor-default-state { pins = "gpio155"; function = "gpio"; @@ -1022,6 +1099,13 @@ hall_sensor_default: hall-sensor-default-state { bias-pull-up; }; + mdp_vsync: mdp-vsync-state { + pins = "gpio80"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + pm8008_int_default: pm8008-int-default-state { pins = "gpio25"; function = "gpio"; From 984748d30cd3ce0e11d63b0ba16dcbd61f7b4b9d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 2 Feb 2025 23:45:52 +0100 Subject: [PATCH 039/308] arm64: dts: qcom: qcm6490-fairphone-fp5: Enable the GPU Enable the Adreno GPU and point to the correct ZAP fw path. Signed-off-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250202-fp5-display-v1-2-f52bf546e38f@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index cc4ff2c7a726..377e92c554e1 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -651,6 +651,14 @@ &gpi_dma1 { status = "okay"; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcm6490/fairphone5/a660_zap.mbn"; +}; + &i2c1 { status = "okay"; From 54df5e52777e1126862778a2796c3809df85acd7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:53 +0100 Subject: [PATCH 040/308] arm64: dts: qcom: sm8550: use ICC tag for all interconnect phandles Use the proper QCOM_ICC_TAG_ define instead of passing 0 in all interconnect paths phandle third argument. Use QCOM_ICC_TAG_ALWAYS which is the fallback mask if 0 is used as third phandle argument. Signed-off-by: Neil Armstrong Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-1-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 387 ++++++++++++++++++--------- 1 file changed, 258 insertions(+), 129 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index eac8de4005d8..cc754684bf05 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -331,7 +331,8 @@ firmware { scm: scm { compatible = "qcom,scm-sm8550", "qcom,scm"; qcom,dload-mode = <&tcsr 0x19000>; - interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; }; @@ -850,9 +851,12 @@ i2c8: i2c@880000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; @@ -868,9 +872,12 @@ spi8: spi@880000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; @@ -890,9 +897,12 @@ i2c9: i2c@884000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; @@ -908,9 +918,12 @@ spi9: spi@884000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; @@ -930,9 +943,12 @@ i2c10: i2c@888000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; @@ -948,9 +964,12 @@ spi10: spi@888000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; @@ -970,9 +989,12 @@ i2c11: i2c@88c000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; @@ -988,9 +1010,12 @@ spi11: spi@88c000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; @@ -1010,9 +1035,12 @@ i2c12: i2c@890000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; @@ -1028,9 +1056,12 @@ spi12: spi@890000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; @@ -1050,9 +1081,12 @@ i2c13: i2c@894000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; @@ -1068,9 +1102,12 @@ spi13: spi@894000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; @@ -1088,8 +1125,10 @@ uart14: serial@898000 { pinctrl-names = "default"; pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; interrupts = ; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1104,9 +1143,12 @@ i2c15: i2c@89c000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, <&gpi_dma2 1 7 QCOM_GPI_I2C>; @@ -1122,9 +1164,12 @@ spi15: spi@89c000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, - <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, <&gpi_dma2 1 7 QCOM_GPI_SPI>; @@ -1156,8 +1201,10 @@ i2c_hub_0: i2c@980000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1173,8 +1220,10 @@ i2c_hub_1: i2c@984000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1190,8 +1239,10 @@ i2c_hub_2: i2c@988000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1207,8 +1258,10 @@ i2c_hub_3: i2c@98c000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1224,8 +1277,10 @@ i2c_hub_4: i2c@990000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1241,8 +1296,10 @@ i2c_hub_5: i2c@994000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1258,8 +1315,10 @@ i2c_hub_6: i2c@998000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1275,8 +1334,10 @@ i2c_hub_7: i2c@99c000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1292,8 +1353,10 @@ i2c_hub_8: i2c@9a0000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1309,8 +1372,10 @@ i2c_hub_9: i2c@9a4000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1347,7 +1412,8 @@ qupv3_id_0: geniqup@ac0000 { clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; iommus = <&apps_smmu 0xa3 0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core"; dma-coherent; #address-cells = <2>; @@ -1364,9 +1430,12 @@ i2c0: i2c@a80000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; @@ -1382,9 +1451,12 @@ spi0: spi@a80000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; @@ -1404,9 +1476,12 @@ i2c1: i2c@a84000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; @@ -1422,9 +1497,12 @@ spi1: spi@a84000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; @@ -1444,9 +1522,12 @@ i2c2: i2c@a88000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; @@ -1462,9 +1543,12 @@ spi2: spi@a88000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; @@ -1484,9 +1568,12 @@ i2c3: i2c@a8c000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; @@ -1502,9 +1589,12 @@ spi3: spi@a8c000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; @@ -1524,9 +1614,12 @@ i2c4: i2c@a90000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; @@ -1542,9 +1635,12 @@ spi4: spi@a90000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; @@ -1562,9 +1658,12 @@ i2c5: i2c@a94000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_data_clk>; interrupts = ; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; @@ -1582,9 +1681,12 @@ spi5: spi@a94000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; @@ -1602,9 +1704,12 @@ i2c6: i2c@a98000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_data_clk>; interrupts = ; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; @@ -1622,9 +1727,12 @@ spi6: spi@a98000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, - <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; @@ -1643,8 +1751,10 @@ uart7: serial@a9c000 { pinctrl-0 = <&qup_uart7_default>; interrupts = ; interconnect-names = "qup-core", "qup-config"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; status = "disabled"; }; }; @@ -1768,8 +1878,10 @@ pcie0: pcie@1c00000 { "ddrss_sf_tbu", "noc_aggr"; - interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "pcie-mem", "cpu-pcie"; msi-map = <0x0 &gic_its 0x1400 0x1>, @@ -1891,8 +2003,10 @@ pcie1: pcie@1c08000 { assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "pcie-mem", "cpu-pcie"; msi-map = <0x0 &gic_its 0x1480 0x1>, @@ -1969,7 +2083,8 @@ crypto: crypto@1dfa000 { dma-names = "rx", "tx"; iommus = <&apps_smmu 0x480 0x0>, <&apps_smmu 0x481 0x0>; - interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "memory"; }; @@ -2013,8 +2128,10 @@ ufs_mem_hc: ufshc@1d84000 { dma-coherent; operating-points-v2 = <&ufs_opp_table>; - interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; interconnect-names = "ufs-ddr", "cpu-ufs"; clock-names = "core_clk", @@ -2314,8 +2431,10 @@ ipa: ipa@3f40000 { clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; - interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; + interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; interconnect-names = "memory", "config"; @@ -2349,7 +2468,8 @@ remoteproc_mpss: remoteproc@4080000 { <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; - interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; @@ -2390,7 +2510,8 @@ remoteproc_adsp: remoteproc@6800000 { <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; - interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; @@ -2848,8 +2969,10 @@ sdhc_2: mmc@8804000 { power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; - interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; bus-width = <4>; dma-coherent; @@ -3020,7 +3143,8 @@ mdss: display-subsystem@ae00000 { power-domains = <&dispcc MDSS_GDSC>; - interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "mdp0-mem"; iommus = <&apps_smmu 0x1c00 0x2>; @@ -3493,8 +3617,10 @@ usb_1: usb@a6f8800 { resets = <&gcc GCC_USB30_PRIM_BCR>; - interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "usb-ddr", "apps-usb"; status = "disabled"; @@ -4617,7 +4743,8 @@ pmu@24091000 { compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>; interrupts = ; - interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; operating-points-v2 = <&llcc_bwmon_opp_table>; @@ -4666,7 +4793,8 @@ pmu@240b6400 { compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b6400 0 0x600>; interrupts = ; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; operating-points-v2 = <&cpu_bwmon_opp_table>; @@ -4750,7 +4878,8 @@ remoteproc_cdsp: remoteproc@32300000 { <&rpmhpd RPMHPD_NSP>; power-domain-names = "cx", "mxc", "nsp"; - interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; From 48c84d96dcd022de3b445e20d4cdfc96c2b05538 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:54 +0100 Subject: [PATCH 041/308] arm64: dts: qcom: sm8550: set CPU interconnect paths as ACTIVE_ONLY In all interconnect paths involving the cpu (MASTER_APPSS_PROC), use the QCOM_ICC_TAG_ACTIVE_ONLY which will only retain the vote if the CPU is online, leaving the firmware disabling the path when the CPUs goes in suspend-idle. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-2-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 184 +++++++++++++-------------- 1 file changed, 92 insertions(+), 92 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index cc754684bf05..a04a405a3f78 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -853,8 +853,8 @@ i2c8: i2c@880000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -874,8 +874,8 @@ spi8: spi@880000 { pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -899,8 +899,8 @@ i2c9: i2c@884000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -920,8 +920,8 @@ spi9: spi@884000 { pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -945,8 +945,8 @@ i2c10: i2c@888000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -966,8 +966,8 @@ spi10: spi@888000 { pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -991,8 +991,8 @@ i2c11: i2c@88c000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1012,8 +1012,8 @@ spi11: spi@88c000 { pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1037,8 +1037,8 @@ i2c12: i2c@890000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1058,8 +1058,8 @@ spi12: spi@890000 { pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1083,8 +1083,8 @@ i2c13: i2c@894000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1104,8 +1104,8 @@ spi13: spi@894000 { pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1127,8 +1127,8 @@ uart14: serial@898000 { interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1145,8 +1145,8 @@ i2c15: i2c@89c000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1166,8 +1166,8 @@ spi15: spi@89c000 { pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1203,8 +1203,8 @@ i2c_hub_0: i2c@980000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1222,8 +1222,8 @@ i2c_hub_1: i2c@984000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1241,8 +1241,8 @@ i2c_hub_2: i2c@988000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1260,8 +1260,8 @@ i2c_hub_3: i2c@98c000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1279,8 +1279,8 @@ i2c_hub_4: i2c@990000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1298,8 +1298,8 @@ i2c_hub_5: i2c@994000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1317,8 +1317,8 @@ i2c_hub_6: i2c@998000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1336,8 +1336,8 @@ i2c_hub_7: i2c@99c000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1355,8 +1355,8 @@ i2c_hub_8: i2c@9a0000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1374,8 +1374,8 @@ i2c_hub_9: i2c@9a4000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1432,8 +1432,8 @@ i2c0: i2c@a80000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1453,8 +1453,8 @@ spi0: spi@a80000 { pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1478,8 +1478,8 @@ i2c1: i2c@a84000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1499,8 +1499,8 @@ spi1: spi@a84000 { pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1524,8 +1524,8 @@ i2c2: i2c@a88000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1545,8 +1545,8 @@ spi2: spi@a88000 { pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1570,8 +1570,8 @@ i2c3: i2c@a8c000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1591,8 +1591,8 @@ spi3: spi@a8c000 { pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1616,8 +1616,8 @@ i2c4: i2c@a90000 { #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1637,8 +1637,8 @@ spi4: spi@a90000 { pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1660,8 +1660,8 @@ i2c5: i2c@a94000 { interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1683,8 +1683,8 @@ spi5: spi@a94000 { pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1706,8 +1706,8 @@ i2c6: i2c@a98000 { interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1729,8 +1729,8 @@ spi6: spi@a98000 { pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; @@ -1753,8 +1753,8 @@ uart7: serial@a9c000 { interconnect-names = "qup-core", "qup-config"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; status = "disabled"; }; }; @@ -1880,8 +1880,8 @@ pcie0: pcie@1c00000 { interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; msi-map = <0x0 &gic_its 0x1400 0x1>, @@ -2005,8 +2005,8 @@ pcie1: pcie@1c08000 { interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; msi-map = <0x0 &gic_its 0x1480 0x1>, @@ -2130,8 +2130,8 @@ ufs_mem_hc: ufshc@1d84000 { operating-points-v2 = <&ufs_opp_table>; interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "ufs-ddr", "cpu-ufs"; clock-names = "core_clk", @@ -2433,8 +2433,8 @@ ipa: ipa@3f40000 { interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "memory", "config"; @@ -2971,8 +2971,8 @@ sdhc_2: mmc@8804000 { interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; bus-width = <4>; dma-coherent; @@ -3619,8 +3619,8 @@ usb_1: usb@a6f8800 { interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "usb-ddr", "apps-usb"; status = "disabled"; From 0acd169330b81036aebd27c025b0a5bb8a77ea4b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:55 +0100 Subject: [PATCH 042/308] arm64: dts: qcom: sm8550: add OPP table support to PCIe The PCIe bus interconnect path can be scaled depending on the PCIe link established, add the OPP table with all the possible link speeds and the associated power domain level. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-3-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 89 ++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index a04a405a3f78..4b3c51fad9f1 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1897,8 +1897,49 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie0_phy>; phy-names = "pciephy"; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + }; + pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; @@ -2023,8 +2064,56 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie1_phy>; phy-names = "pciephy"; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; From ac2b7b1e8432fc758f6cd345e9a2472b269cb1c5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:56 +0100 Subject: [PATCH 043/308] arm64: dts: qcom: sm8550: add QUP serial engines OPP tables The QUP Serial Engines requires different power domain level depending on their working frequency, add the required OPP table with the level associated with all possible frequencies. For the "I2C Hub" serial engines, sinse they only support a single Operating Point, only add a single power domain level property. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-4-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 122 +++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 4b3c51fad9f1..d02d80d731b9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -348,6 +348,48 @@ mc_virt: interconnect-1 { qcom,bcm-voters = <&apps_bcm_voter>; }; + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_120mhz: opp-table-qup120mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_125mhz: opp-table-qup125mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + memory@a0000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -861,6 +903,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; status = "disabled"; }; @@ -882,6 +926,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -907,6 +953,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; status = "disabled"; }; @@ -928,6 +976,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -953,6 +1003,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; status = "disabled"; }; @@ -974,6 +1026,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -999,6 +1053,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; status = "disabled"; }; @@ -1020,6 +1076,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1045,6 +1103,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; status = "disabled"; }; @@ -1066,6 +1126,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1091,6 +1153,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; status = "disabled"; }; @@ -1112,6 +1176,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1130,6 +1196,8 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_125mhz>; status = "disabled"; }; @@ -1153,6 +1221,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, <&gpi_dma2 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1174,6 +1244,8 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, <&gpi_dma2 1 7 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1206,6 +1278,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; }; @@ -1225,6 +1299,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; }; @@ -1244,6 +1320,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; }; @@ -1263,6 +1341,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; }; @@ -1282,6 +1362,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; }; @@ -1301,6 +1383,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; }; @@ -1320,6 +1404,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; }; @@ -1339,6 +1425,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; }; @@ -1358,6 +1446,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; }; @@ -1377,6 +1467,8 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; }; }; @@ -1440,6 +1532,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; status = "disabled"; }; @@ -1461,6 +1555,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1486,6 +1582,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; status = "disabled"; }; @@ -1507,6 +1605,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1532,6 +1632,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1553,6 +1655,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1578,6 +1682,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1599,6 +1705,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1624,6 +1732,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1645,6 +1755,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1668,6 +1780,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1691,6 +1805,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1714,6 +1830,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1737,6 +1855,8 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1755,6 +1875,8 @@ uart7: serial@a9c000 { &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; }; From ee6dfc9c75d43a2e2b2ea4c5055e31545b2aee83 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:57 +0100 Subject: [PATCH 044/308] arm64: dts: qcom: sm8650: use ICC tag for IPA interconnect phandles Use the proper QCOM_ICC_TAG_ define instead of passing 0 in the IPA interconnect paths phandle third argument Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-5-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index de75cd50d5e9..e17a050b8c4f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3822,8 +3822,10 @@ ipa: ipa@3f40000 { clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; - interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; + interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; interconnect-names = "memory", "config"; From a4da40505d72385495ef5d4f1cc8479ab75b95e4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:58 +0100 Subject: [PATCH 045/308] arm64: dts: qcom: sm8650: set CPU interconnect paths as ACTIVE_ONLY In all interconnect paths involving the cpu (MASTER_APPSS_PROC), use the QCOM_ICC_TAG_ACTIVE_ONLY which will only retain the vote if the CPU is online, leaving the firmware disabling the path when the CPUs goes in suspend-idle. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-6-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 180 +++++++++++++-------------- 1 file changed, 90 insertions(+), 90 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e17a050b8c4f..4c376e3a7b62 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -1814,8 +1814,8 @@ i2c8: i2c@880000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1847,8 +1847,8 @@ spi8: spi@880000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1880,8 +1880,8 @@ i2c9: i2c@884000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1913,8 +1913,8 @@ spi9: spi@884000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1946,8 +1946,8 @@ i2c10: i2c@888000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -1979,8 +1979,8 @@ spi10: spi@888000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2012,8 +2012,8 @@ i2c11: i2c@88c000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2045,8 +2045,8 @@ spi11: spi@88c000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2078,8 +2078,8 @@ i2c12: i2c@890000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2111,8 +2111,8 @@ spi12: spi@890000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2144,8 +2144,8 @@ i2c13: i2c@894000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2177,8 +2177,8 @@ spi13: spi@894000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2210,8 +2210,8 @@ uart14: serial@898000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2232,8 +2232,8 @@ uart15: serial@89c000 { interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2270,8 +2270,8 @@ i2c_hub_0: i2c@980000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2297,8 +2297,8 @@ i2c_hub_1: i2c@984000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2324,8 +2324,8 @@ i2c_hub_2: i2c@988000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2351,8 +2351,8 @@ i2c_hub_3: i2c@98c000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2378,8 +2378,8 @@ i2c_hub_4: i2c@990000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2405,8 +2405,8 @@ i2c_hub_5: i2c@994000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2432,8 +2432,8 @@ i2c_hub_6: i2c@998000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2459,8 +2459,8 @@ i2c_hub_7: i2c@99c000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2486,8 +2486,8 @@ i2c_hub_8: i2c@9a0000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2513,8 +2513,8 @@ i2c_hub_9: i2c@9a4000 { interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; @@ -2589,8 +2589,8 @@ i2c0: i2c@a80000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2622,8 +2622,8 @@ spi0: spi@a80000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2655,8 +2655,8 @@ i2c1: i2c@a84000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2688,8 +2688,8 @@ spi1: spi@a84000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2721,8 +2721,8 @@ i2c2: i2c@a88000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2754,8 +2754,8 @@ spi2: spi@a88000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2787,8 +2787,8 @@ i2c3: i2c@a8c000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2820,8 +2820,8 @@ spi3: spi@a8c000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2853,8 +2853,8 @@ i2c4: i2c@a90000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2886,8 +2886,8 @@ spi4: spi@a90000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2919,8 +2919,8 @@ i2c5: i2c@a94000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2952,8 +2952,8 @@ spi5: spi@a94000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -2985,8 +2985,8 @@ i2c6: i2c@a98000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -3018,8 +3018,8 @@ spi6: spi@a98000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -3051,8 +3051,8 @@ i2c7: i2c@a9c000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -3084,8 +3084,8 @@ spi7: spi@a9c000 { interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", @@ -3234,8 +3234,8 @@ pcie0: pcie@1c00000 { interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; @@ -3373,8 +3373,8 @@ pcie1: pcie@1c08000 { interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; @@ -3542,8 +3542,8 @@ ufs_mem_hc: ufshc@1d84000 { interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "ufs-ddr", "cpu-ufs"; @@ -3824,8 +3824,8 @@ ipa: ipa@3f40000 { interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "memory", "config"; @@ -4407,8 +4407,8 @@ sdhc_2: mmc@8804000 { interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; From e61d8377c7b5e9fa6c4d57a5478118043e94d907 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jan 2025 14:43:59 +0100 Subject: [PATCH 046/308] arm64: dts: qcom: sm8650: add USB interconnect paths Add the interconnect paths for the USB controller. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-7-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 4c376e3a7b62..ded6afd220a5 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5081,6 +5081,13 @@ usb_1: usb@a6f8800 { resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; From 5cddecc3d1dce1e20bb64364cb6cd5d8edf376b3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jan 2025 14:44:00 +0100 Subject: [PATCH 047/308] arm64: dts: qcom: sm8650: add OPP table support to PCIe The PCIe bus interconnect path can be scaled depending on the PCIe link established, add the OPP table with all the possible link speeds and the associated power domain level. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-8-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 89 ++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index ded6afd220a5..e6938d04c40b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3241,6 +3241,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, power-domains = <&gcc PCIE_0_GDSC>; + operating-points-v2 = <&pcie0_opp_table>; + iommu-map = <0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; @@ -3271,6 +3273,45 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + }; + pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; @@ -3380,6 +3421,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, power-domains = <&gcc PCIE_1_GDSC>; + operating-points-v2 = <&pcie1_opp_table>; + iommu-map = <0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; @@ -3410,6 +3453,52 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; From 2c885d85dff832d9be99093bdae73e77795f0aec Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jan 2025 14:44:01 +0100 Subject: [PATCH 048/308] arm64: dts: qcom: sm8650: add QUP serial engines OPP tables The QUP Serial Engines requires different power domain level depending on their working frequency, add the required OPP table with the level associated with all possible frequencies. For the "I2C Hub" serial engines, sinse they only support a single Operating Point, only add a single power domain level property. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-9-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 216 +++++++++++++++++++++++++++ 1 file changed, 216 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e6938d04c40b..38c433e79fac 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -493,6 +493,62 @@ mc_virt: interconnect-1 { qcom,bcm-voters = <&apps_bcm_voter>; }; + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_120mhz: opp-table-qup120mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_128mhz: opp-table-qup128mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_240mhz: opp-table-qup240mhz { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + memory@a0000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -1822,6 +1878,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names = "tx", @@ -1855,6 +1915,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names = "tx", @@ -1888,6 +1952,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names = "tx", @@ -1921,6 +1989,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names = "tx", @@ -1954,6 +2026,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names = "tx", @@ -1987,6 +2063,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names = "tx", @@ -2020,6 +2100,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", @@ -2053,6 +2137,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names = "tx", @@ -2086,6 +2174,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", @@ -2119,6 +2211,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names = "tx", @@ -2152,6 +2248,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names = "tx", @@ -2185,6 +2285,10 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", @@ -2215,6 +2319,10 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_128mhz>; + pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; pinctrl-names = "default"; @@ -2237,6 +2345,10 @@ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + pinctrl-0 = <&qup_uart15_default>; pinctrl-names = "default"; @@ -2275,6 +2387,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c0_data_clk>; pinctrl-names = "default"; @@ -2302,6 +2418,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c1_data_clk>; pinctrl-names = "default"; @@ -2329,6 +2449,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c2_data_clk>; pinctrl-names = "default"; @@ -2356,6 +2480,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c3_data_clk>; pinctrl-names = "default"; @@ -2383,6 +2511,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c4_data_clk>; pinctrl-names = "default"; @@ -2410,6 +2542,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c5_data_clk>; pinctrl-names = "default"; @@ -2437,6 +2573,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c6_data_clk>; pinctrl-names = "default"; @@ -2464,6 +2604,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c7_data_clk>; pinctrl-names = "default"; @@ -2491,6 +2635,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c8_data_clk>; pinctrl-names = "default"; @@ -2518,6 +2666,10 @@ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c9_data_clk>; pinctrl-names = "default"; @@ -2597,6 +2749,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", @@ -2630,6 +2786,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", @@ -2663,6 +2823,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", @@ -2696,6 +2860,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", @@ -2729,6 +2897,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_240mhz>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", @@ -2762,6 +2934,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_240mhz>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", @@ -2795,6 +2971,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", @@ -2828,6 +3008,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", @@ -2861,6 +3045,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", @@ -2894,6 +3082,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", @@ -2927,6 +3119,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", @@ -2960,6 +3156,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", @@ -2993,6 +3193,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", @@ -3026,6 +3230,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names = "tx", @@ -3059,6 +3267,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", @@ -3092,6 +3304,10 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, <&gpi_dma1 1 7 QCOM_GPI_SPI>; dma-names = "tx", From 61dcbf45110bb3c3bfd7c92abaca9fffb84110e0 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 15 Jan 2025 14:44:02 +0100 Subject: [PATCH 049/308] arm64: dts: qcom: sm8650: add UFS OPP table instead of freq-table-hz property Swich to an OPP table for the UFS frequency scaling instead of the deprecated freq-table-hz property. The Operating Point table will also provide the associated power domain level. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-10-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 50 +++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 38c433e79fac..de960bcaf3cc 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3833,14 +3833,6 @@ ufs_mem_hc: ufshc@1d84000 { "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; - freq-table-hz = <100000000 403000000>, - <0 0>, - <0 0>, - <100000000 403000000>, - <100000000 403000000>, - <0 0>, - <0 0>, - <0 0>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; @@ -3855,6 +3847,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, power-domains = <&gcc UFS_PHY_GDSC>; required-opps = <&rpmhpd_opp_nom>; + operating-points-v2 = <&ufs_opp_table>; + iommus = <&apps_smmu 0x60 0>; lanes-per-direction = <2>; @@ -3866,6 +3860,46 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, #reset-cells = <1>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz = /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ice: crypto@1d88000 { From 0e2a500eff87c710f3947926e274fd83d0cabb02 Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Mon, 3 Feb 2025 09:34:26 +0300 Subject: [PATCH 050/308] arm64: dts: qcom: sdm630: Add missing resets to mmc blocks Add resets to eMMC/SD card blocks so linux can properly reset them during initialization. Signed-off-by: Alexey Minnekhanov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250203063427.358327-4-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index a2c079bac1a7..3722e405a97c 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1379,6 +1379,7 @@ sdhc_2: mmc@c084000 { <&xo_board>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; interconnects = <&a2noc 3 &a2noc 10>, <&gnoc 0 &cnoc 28>; @@ -1433,6 +1434,8 @@ sdhc_1: mmc@c0c4000 { <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface", "core", "xo", "ice"; + resets = <&gcc GCC_SDCC1_BCR>; + interconnects = <&a2noc 2 &a2noc 10>, <&gnoc 0 &cnoc 27>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; From 92979f12a201c54ea94b8b3c9f0737c33bb45e23 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 28 Jan 2025 12:53:32 +0100 Subject: [PATCH 051/308] arm64: dts: qcom: sa8775p: Partially revert "arm64: dts: qcom: sa8775p: add QCrypto nodes" Partially revert commit 7ff3da43ef44 ("arm64: dts: qcom: sa8775p: add QCrypto nodes") by dropping the untested QCE device node. Devicetree bindings test failures were reported on mailing list on 16th of January and after two weeks still no fixes: sa8775p-ride.dtb: crypto@1dfa000: compatible: 'oneOf' conditional failed, one must be fixed: ... 'qcom,sa8775p-qce' is not one of ['qcom,ipq4019-qce', 'qcom,sm8150-qce'] Reported-by: Rob Herring Closes: https://lore.kernel.org/all/CAL_JsqJG_w9jyWjVR=QnPuJganG4uj9+9cEXZ__UAiCw2ZYZZA@mail.gmail.com/ Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250128115333.95021-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3394ae2d1300..23049cc58896 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2418,17 +2418,6 @@ cryptobam: dma-controller@1dc4000 { <&apps_smmu 0x481 0x00>; }; - crypto: crypto@1dfa000 { - compatible = "qcom,sa8775p-qce", "qcom,qce"; - reg = <0x0 0x01dfa000 0x0 0x6000>; - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x480 0x00>, - <&apps_smmu 0x481 0x00>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "memory"; - }; - stm: stm@4002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x4002000 0x0 0x1000>, From cdc117c40537c5babfa7f261360d5a98e434d59e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 28 Jan 2025 12:53:33 +0100 Subject: [PATCH 052/308] arm64: dts: qcom: qcs8300: Partially revert "arm64: dts: qcom: qcs8300: add QCrypto nodes" Partially revert commit a86d84409947 ("arm64: dts: qcom: qcs8300: add QCrypto nodes") by dropping the untested QCE device node. Devicetree bindings test failures were reported on mailing list on 16th of January and after two weeks still no fixes: qcs8300-ride.dtb: crypto@1dfa000: compatible: 'oneOf' conditional failed, one must be fixed: ... 'qcom,qcs8300-qce' is not one of ['qcom,ipq4019-qce', 'qcom,sm8150-qce'] Reported-by: Rob Herring Closes: https://lore.kernel.org/all/CAL_JsqL0HzzGXnCD+z4GASeXNsBxrdw8-qyfHj8S+C2ucK6EPQ@mail.gmail.com/ Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250128115333.95021-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index ff99ec21f88c..cdd412706b5b 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2045,18 +2045,6 @@ cryptobam: dma-controller@1dc4000 { <&apps_smmu 0x481 0x00>; }; - crypto: crypto@1dfa000 { - compatible = "qcom,qcs8300-qce", "qcom,qce"; - reg = <0x0 0x01dfa000 0x0 0x6000>; - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x480 0x00>, - <&apps_smmu 0x481 0x00>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "memory"; - }; - ice: crypto@1d88000 { compatible = "qcom,qcs8300-inline-crypto-engine", "qcom,inline-crypto-engine"; From fb03174d17ec98e939dac81e29b372c9b568fca9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:30:51 +0100 Subject: [PATCH 053/308] arm64: dts: qcom: x1e80100-slim7x: Drop incorrect qcom,ath12k-calibration-variant There is no such property as qcom,ath12k-calibration-variant: neither in the bindings nor in the driver. See dtbs_check: x1e80100-lenovo-yoga-slim7x.dtb: wifi@0: 'qcom,ath12k-calibration-variant' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250225093051.58406-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index a3d53f2ba2c3..9aff5a1f044d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -674,8 +674,6 @@ &pcie4_port0 { wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; - - qcom,ath12k-calibration-variant = "LES790"; }; }; From 327d489d1ecaf16182952f079cc21f04cf83f967 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 27 Feb 2025 10:00:32 +0100 Subject: [PATCH 054/308] arm64: dts: qcom: sm8550: add missing cpu-cfg interconnect path in the mdss node The bindings requires the mdp0-mem and the cpu-cfg interconnect path, add the missing cpu-cfg path to fix the dtbs check error and also to ensure that MDSS has enough bandwidth to let HLOS write config registers. Fixes: b8591df49cde ("arm64: dts: qcom: sm8550: correct MDSS interconnects") Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250227-topic-sm8x50-mdss-interconnect-bindings-fix-v5-1-bf6233c6ebe5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d02d80d731b9..18bcb4ac6bd8 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3355,8 +3355,10 @@ mdss: display-subsystem@ae00000 { power-domains = <&dispcc MDSS_GDSC>; interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "mdp0-mem"; + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", "cpu-cfg"; iommus = <&apps_smmu 0x1c00 0x2>; From f22be5c1dd3e12519e3f3b80c14d10b90be2c2fc Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 27 Feb 2025 10:00:33 +0100 Subject: [PATCH 055/308] arm64: dts: qcom: sm8650: add missing cpu-cfg interconnect path in the mdss node The bindings requires the mdp0-mem and the cpu-cfg interconnect path, add the missing cpu-cfg path to fix the dtbs check error and also to ensure that MDSS has enough bandwidth to let HLOS write config registers. Fixes: 9fa33cbca3d2 ("arm64: dts: qcom: sm8650: correct MDSS interconnects") Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250227-topic-sm8x50-mdss-interconnect-bindings-fix-v5-2-bf6233c6ebe5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index de960bcaf3cc..719ad437756a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4930,8 +4930,11 @@ mdss: display-subsystem@ae00000 { resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "mdp0-mem"; + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; power-domains = <&dispcc MDSS_GDSC>; From 801befff4c827aa72e3698367c5afc18987a6a3f Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 19 Feb 2025 12:36:18 +0100 Subject: [PATCH 056/308] arm64: dts: qcom: x1e80100: Fix video thermal zone MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A passive trip point at 125°C is pretty high, this is usually the temperature for the critical shutdown trip point. Also, we don't have any passive cooling devices attached to the video thermal zone. Change this to be a critical trip point, and add a "hot" trip point at 90°C for consistency with the other thermal zones. Cc: stable@vger.kernel.org Fixes: 4e915987ff5b ("arm64: dts: qcom: x1e80100: Enable tsens and thermal zone nodes") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250219-x1e80100-thermal-fixes-v1-1-d110e44ac3f9@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5c091e234ca3..7d750a899e80 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -8740,15 +8740,19 @@ mem-critical { }; video-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 12>; trips { trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + video-critical { temperature = <125000>; hysteresis = <1000>; - type = "passive"; + type = "critical"; }; }; }; From 03f2b8eed73418269a158ccebad5d8d8f2f6daa1 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 19 Feb 2025 12:36:19 +0100 Subject: [PATCH 057/308] arm64: dts: qcom: x1e80100: Apply consistent critical thermal shutdown MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The firmware configures the TSENS controller with a maximum temperature of 120°C. When reaching that temperature, the hardware automatically triggers a reset of the entire platform. Some of the thermal zones in x1e80100.dtsi use a critical trip point of 125°C. It's impossible to reach those. It's preferable to shut down the system cleanly before reaching the hardware trip point. Make the critical temperature trip points consistent by setting all of them to 115°C and apply a consistent hysteresis. The ACPI tables also specify 115°C as critical shutdown temperature. Cc: stable@vger.kernel.org Fixes: 4e915987ff5b ("arm64: dts: qcom: x1e80100: Enable tsens and thermal zone nodes") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250219-x1e80100-thermal-fixes-v1-2-d110e44ac3f9@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 128 ++++++++++++------------- 1 file changed, 64 insertions(+), 64 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 7d750a899e80..e0ef5665f862 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -8470,8 +8470,8 @@ trip-point0 { }; aoss0-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -8496,7 +8496,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8522,7 +8522,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8548,7 +8548,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8574,7 +8574,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8600,7 +8600,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8626,7 +8626,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8652,7 +8652,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8678,7 +8678,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8696,8 +8696,8 @@ trip-point0 { }; cpuss2-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -8714,8 +8714,8 @@ trip-point0 { }; cpuss2-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -8732,7 +8732,7 @@ trip-point0 { }; mem-critical { - temperature = <125000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -8750,7 +8750,7 @@ trip-point0 { }; video-critical { - temperature = <125000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8768,8 +8768,8 @@ trip-point0 { }; aoss0-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -8794,7 +8794,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8820,7 +8820,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8846,7 +8846,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8872,7 +8872,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8898,7 +8898,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8924,7 +8924,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8950,7 +8950,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8976,7 +8976,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -8994,8 +8994,8 @@ trip-point0 { }; cpuss2-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9012,8 +9012,8 @@ trip-point0 { }; cpuss2-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9030,8 +9030,8 @@ trip-point0 { }; aoss0-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9056,7 +9056,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9082,7 +9082,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9108,7 +9108,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9134,7 +9134,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9160,7 +9160,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9186,7 +9186,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9212,7 +9212,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9238,7 +9238,7 @@ trip-point1 { }; cpu-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9256,8 +9256,8 @@ trip-point0 { }; cpuss2-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9274,8 +9274,8 @@ trip-point0 { }; cpuss2-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9292,8 +9292,8 @@ trip-point0 { }; aoss0-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9310,8 +9310,8 @@ trip-point0 { }; nsp0-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9328,8 +9328,8 @@ trip-point0 { }; nsp1-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9346,8 +9346,8 @@ trip-point0 { }; nsp2-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9364,8 +9364,8 @@ trip-point0 { }; nsp3-critical { - temperature = <125000>; - hysteresis = <0>; + temperature = <115000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9390,7 +9390,7 @@ trip-point1 { }; trip-point2 { - temperature = <125000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9416,7 +9416,7 @@ trip-point1 { }; trip-point2 { - temperature = <125000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9442,7 +9442,7 @@ trip-point1 { }; trip-point2 { - temperature = <125000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9468,7 +9468,7 @@ trip-point1 { }; trip-point2 { - temperature = <125000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9494,7 +9494,7 @@ trip-point1 { }; trip-point2 { - temperature = <125000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9520,7 +9520,7 @@ trip-point1 { }; trip-point2 { - temperature = <125000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9546,7 +9546,7 @@ trip-point1 { }; trip-point2 { - temperature = <125000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9572,7 +9572,7 @@ trip-point1 { }; trip-point2 { - temperature = <125000>; + temperature = <115000>; hysteresis = <1000>; type = "critical"; }; @@ -9591,7 +9591,7 @@ trip-point0 { camera0-critical { temperature = <115000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -9609,7 +9609,7 @@ trip-point0 { camera0-critical { temperature = <115000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; From 5ba21fa11f473c9827f378ace8c9f983de9e0287 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 19 Feb 2025 12:36:20 +0100 Subject: [PATCH 058/308] arm64: dts: qcom: x1e80100: Add GPU cooling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unlike the CPU, the GPU does not throttle its speed automatically when it reaches high temperatures. With certain high GPU loads it is possible to reach the critical hardware shutdown temperature of 120°C, endangering the hardware and making it impossible to run certain applications. Set up GPU cooling similar to the ACPI tables, by throttling the GPU speed when reaching 95°C and polling every 200ms. Cc: stable@vger.kernel.org Fixes: 721e38301b79 ("arm64: dts: qcom: x1e80100: Add gpu support") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250219-x1e80100-thermal-fixes-v1-3-d110e44ac3f9@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++------------ 1 file changed, 89 insertions(+), 80 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index e0ef5665f862..9382a2fce2f3 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -20,6 +20,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -9372,24 +9373,25 @@ nsp3-critical { }; gpuss-0-thermal { - polling-delay-passive = <10>; + polling-delay-passive = <200>; thermal-sensors = <&tsens3 5>; + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <85000>; + gpuss0_alert0: trip-point0 { + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; - trip-point1 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - - trip-point2 { + gpu-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; @@ -9398,24 +9400,25 @@ trip-point2 { }; gpuss-1-thermal { - polling-delay-passive = <10>; + polling-delay-passive = <200>; thermal-sensors = <&tsens3 6>; + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <85000>; + gpuss1_alert0: trip-point0 { + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; - trip-point1 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - - trip-point2 { + gpu-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; @@ -9424,24 +9427,25 @@ trip-point2 { }; gpuss-2-thermal { - polling-delay-passive = <10>; + polling-delay-passive = <200>; thermal-sensors = <&tsens3 7>; + cooling-maps { + map0 { + trip = <&gpuss2_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <85000>; + gpuss2_alert0: trip-point0 { + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; - trip-point1 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - - trip-point2 { + gpu-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; @@ -9450,24 +9454,25 @@ trip-point2 { }; gpuss-3-thermal { - polling-delay-passive = <10>; + polling-delay-passive = <200>; thermal-sensors = <&tsens3 8>; + cooling-maps { + map0 { + trip = <&gpuss3_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <85000>; + gpuss3_alert0: trip-point0 { + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; - trip-point1 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - - trip-point2 { + gpu-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; @@ -9476,24 +9481,25 @@ trip-point2 { }; gpuss-4-thermal { - polling-delay-passive = <10>; + polling-delay-passive = <200>; thermal-sensors = <&tsens3 9>; + cooling-maps { + map0 { + trip = <&gpuss4_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <85000>; + gpuss4_alert0: trip-point0 { + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; - trip-point1 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - - trip-point2 { + gpu-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; @@ -9502,24 +9508,25 @@ trip-point2 { }; gpuss-5-thermal { - polling-delay-passive = <10>; + polling-delay-passive = <200>; thermal-sensors = <&tsens3 10>; + cooling-maps { + map0 { + trip = <&gpuss5_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <85000>; + gpuss5_alert0: trip-point0 { + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; - trip-point1 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - - trip-point2 { + gpu-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; @@ -9528,24 +9535,25 @@ trip-point2 { }; gpuss-6-thermal { - polling-delay-passive = <10>; + polling-delay-passive = <200>; thermal-sensors = <&tsens3 11>; + cooling-maps { + map0 { + trip = <&gpuss6_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <85000>; + gpuss6_alert0: trip-point0 { + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; - trip-point1 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - - trip-point2 { + gpu-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; @@ -9554,24 +9562,25 @@ trip-point2 { }; gpuss-7-thermal { - polling-delay-passive = <10>; + polling-delay-passive = <200>; thermal-sensors = <&tsens3 12>; + cooling-maps { + map0 { + trip = <&gpuss7_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <85000>; + gpuss7_alert0: trip-point0 { + temperature = <95000>; hysteresis = <1000>; type = "passive"; }; - trip-point1 { - temperature = <90000>; - hysteresis = <1000>; - type = "hot"; - }; - - trip-point2 { + gpu-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; From 06eadce936971dd11279e53b6dfb151804137836 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 19 Feb 2025 12:36:21 +0100 Subject: [PATCH 059/308] arm64: dts: qcom: x1e80100: Drop unused passive thermal trip points for CPU There are currently two passive trip points defined for the CPU, but no cooling devices are attached to the thermal zones. We don't have support for cpufreq upstream yet, but actually this is redundant anyway because the CPU is throttled automatically when reaching high temperatures. Drop the passive trip points and keep just the critical shutdown as safety measure in case the throttling fails. Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20250219-x1e80100-thermal-fixes-v1-4-d110e44ac3f9@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 372 ------------------------- 1 file changed, 372 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 9382a2fce2f3..46b79fce92c9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -8479,23 +8479,9 @@ aoss0-critical { }; cpu0-0-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 1>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8505,23 +8491,9 @@ cpu-critical { }; cpu0-0-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 2>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8531,23 +8503,9 @@ cpu-critical { }; cpu0-1-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 3>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8557,23 +8515,9 @@ cpu-critical { }; cpu0-1-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 4>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8583,23 +8527,9 @@ cpu-critical { }; cpu0-2-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 5>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8609,23 +8539,9 @@ cpu-critical { }; cpu0-2-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 6>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8635,23 +8551,9 @@ cpu-critical { }; cpu0-3-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 7>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8661,23 +8563,9 @@ cpu-critical { }; cpu0-3-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens0 8>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8690,12 +8578,6 @@ cpuss0-top-thermal { thermal-sensors = <&tsens0 9>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cpuss2-critical { temperature = <115000>; hysteresis = <1000>; @@ -8708,12 +8590,6 @@ cpuss0-btm-thermal { thermal-sensors = <&tsens0 10>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cpuss2-critical { temperature = <115000>; hysteresis = <1000>; @@ -8777,23 +8653,9 @@ aoss0-critical { }; cpu1-0-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens1 1>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8803,23 +8665,9 @@ cpu-critical { }; cpu1-0-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens1 2>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8829,23 +8677,9 @@ cpu-critical { }; cpu1-1-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens1 3>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8855,23 +8689,9 @@ cpu-critical { }; cpu1-1-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens1 4>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8881,23 +8701,9 @@ cpu-critical { }; cpu1-2-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens1 5>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8907,23 +8713,9 @@ cpu-critical { }; cpu1-2-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens1 6>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8933,23 +8725,9 @@ cpu-critical { }; cpu1-3-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens1 7>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8959,23 +8737,9 @@ cpu-critical { }; cpu1-3-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens1 8>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -8988,12 +8752,6 @@ cpuss1-top-thermal { thermal-sensors = <&tsens1 9>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cpuss2-critical { temperature = <115000>; hysteresis = <1000>; @@ -9006,12 +8764,6 @@ cpuss1-btm-thermal { thermal-sensors = <&tsens1 10>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cpuss2-critical { temperature = <115000>; hysteresis = <1000>; @@ -9039,23 +8791,9 @@ aoss0-critical { }; cpu2-0-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens2 1>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -9065,23 +8803,9 @@ cpu-critical { }; cpu2-0-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens2 2>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -9091,23 +8815,9 @@ cpu-critical { }; cpu2-1-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens2 3>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -9117,23 +8827,9 @@ cpu-critical { }; cpu2-1-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens2 4>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -9143,23 +8839,9 @@ cpu-critical { }; cpu2-2-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens2 5>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -9169,23 +8851,9 @@ cpu-critical { }; cpu2-2-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens2 6>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -9195,23 +8863,9 @@ cpu-critical { }; cpu2-3-top-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens2 7>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -9221,23 +8875,9 @@ cpu-critical { }; cpu2-3-btm-thermal { - polling-delay-passive = <250>; - thermal-sensors = <&tsens2 8>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu-critical { temperature = <115000>; hysteresis = <1000>; @@ -9250,12 +8890,6 @@ cpuss2-top-thermal { thermal-sensors = <&tsens2 9>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cpuss2-critical { temperature = <115000>; hysteresis = <1000>; @@ -9268,12 +8902,6 @@ cpuss2-btm-thermal { thermal-sensors = <&tsens2 10>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - cpuss2-critical { temperature = <115000>; hysteresis = <1000>; From 2a26a02e668ff101580647221c898d75ed93f8f5 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Thu, 27 Feb 2025 19:26:48 +0500 Subject: [PATCH 060/308] arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Drop CMA heap Initially added, the cma heap was supposed to help with libcamera swisp, however a mistake was made such that the node was never applied as part of the overlay since the change was added to the overlay root ("/") and not with a reference to the target dtb root ("&{/}"). Moveover libcamera doesn't require CMA heap on Qualcomm platforms anymore as it can now use UDMA buffers instead. Drop the CMA heap node. This change has no effect on the final dtb. This reverts commit 99d557cfe4fcf89664762796678e26009aa3bdd9. Fixes: 99d557cfe4fc ("arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Add cma heap for libcamera softisp support") Suggested-by: Bryan O'Donoghue Signed-off-by: Nikita Travkin Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250227-qcom-nonroot-overlays-v2-1-bde44f708cbe@trvn.ru Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dtso | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dtso index ae256c713a36..5fe331923dd3 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5-vision-mezzanine.dtso @@ -9,17 +9,6 @@ #include #include -/ { - reserved-memory { - linux,cma { - compatible = "shared-dma-pool"; - size = <0x0 0x8000000>; - reusable; - linux,cma-default; - }; - }; -}; - &camcc { status = "okay"; }; From 4de3e8d657f2111dd8d45c2ba0eef8b2437b85f2 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Thu, 27 Feb 2025 19:26:49 +0500 Subject: [PATCH 061/308] arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Drop CMA heap Initially added, the cma heap was supposed to help with libcamera swisp, however a mistake was made such that the node was never applied as part of the overlay since the change was added to the overlay root ("/") and not with a reference to the target dtb root ("&{/}"). Moveover libcamera doesn't require CMA heap on Qualcomm platforms anymore as it can now use UDMA buffers instead. Drop the CMA heap node. This change has no effect on the final dtb. This reverts commit d40fd02c1faf8faad57a7579b573bc5be51faabe. Fixes: d40fd02c1faf ("arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Add cma heap for libcamera softisp support") Suggested-by: Bryan O'Donoghue Signed-off-by: Nikita Travkin Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250227-qcom-nonroot-overlays-v2-2-bde44f708cbe@trvn.ru Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-db845c-navigation-mezzanine.dtso | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso index 59970082da45..51f1a4883ab8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso @@ -9,17 +9,6 @@ #include #include -/ { - reserved-memory { - linux,cma { - compatible = "shared-dma-pool"; - size = <0x0 0x8000000>; - reusable; - linux,cma-default; - }; - }; -}; - &camss { vdda-phy-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l26a_1p2>; From 01a3d5e3cdc833292bdc80a4320235551083982f Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Thu, 27 Feb 2025 00:12:09 +0100 Subject: [PATCH 062/308] arm64: dts: qcom: x1e80100-dell-xps13-9345: Enable external DP support Particular laptops comes with two USB Type-C ports, both supporting DP alt mode. Enable output on both of them. Explicitly list supported frequencies including HBR3/8.1Gbps for all external DisplayPort(s). Due to support missing in the USB/DisplayPort combo PHY driver, the external DisplayPort is limited to 2 lanes. Derived from: arm64: dts: qcom: x1e80100-t14s: Add external DP support Signed-off-by: Aleksandrs Vinarskis Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250226231436.16138-2-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 86e87f03b0ec..124051334be0 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -770,6 +770,24 @@ &mdss { status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dp3 { /delete-property/ #sound-dai-cells; From 027dcb3de88dfd1b82f5f712361d216f209110b0 Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Thu, 27 Feb 2025 00:12:10 +0100 Subject: [PATCH 063/308] arm64: dts: qcom: x1e001de-devkit: Enable HBR3 on external DPs When no link frequencies are set, msm/dp driver defaults to HBR2 speed. Explicitly list supported frequencies including HBR3/8.1Gbps for all external DisplayPort(s). Signed-off-by: Aleksandrs Vinarskis Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250226231436.16138-3-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 5e3970b26e2f..602bd793e09c 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -942,6 +942,7 @@ &mdss_dp0 { &mdss_dp0_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp1 { @@ -950,6 +951,7 @@ &mdss_dp1 { &mdss_dp1_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp2 { @@ -958,6 +960,7 @@ &mdss_dp2 { &mdss_dp2_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &pcie4 { From 9a49698252b78471a61873b4fe27dfd2e2fe2bad Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Thu, 27 Feb 2025 00:12:11 +0100 Subject: [PATCH 064/308] arm64: dts: qcom: x1e80100-hp-x14: Enable HBR3 on external DPs When no link frequencies are set, msm/dp driver defaults to HBR2 speed. Explicitly list supported frequencies including HBR3/8.1Gbps for all external DisplayPort(s). Signed-off-by: Aleksandrs Vinarskis Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250226231436.16138-4-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index cd860a246c45..569748c48200 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -1139,6 +1139,7 @@ &mdss_dp0 { &mdss_dp0_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp1 { @@ -1147,6 +1148,7 @@ &mdss_dp1 { &mdss_dp1_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { From c72c7105c82de59fb711f8379843f80b4abef7e3 Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Thu, 27 Feb 2025 00:12:12 +0100 Subject: [PATCH 065/308] arm64: dts: qcom: x1e80100-qcp: Enable HBR3 on external DPs When no link frequencies are set, msm/dp driver defaults to HBR2 speed. Explicitly list supported frequencies including HBR3/8.1Gbps for all external DisplayPort(s). Signed-off-by: Aleksandrs Vinarskis Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250226231436.16138-5-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index ec594628304a..600d0c8a08ef 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -751,6 +751,7 @@ &mdss_dp0 { &mdss_dp0_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp1 { @@ -759,6 +760,7 @@ &mdss_dp1 { &mdss_dp1_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp2 { @@ -767,6 +769,7 @@ &mdss_dp2 { &mdss_dp2_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { From adbbdcf4b2d6556721b580385ba387baca5c26ee Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:58:58 +0100 Subject: [PATCH 066/308] ARM: dts: qcom: ipq4018: Switch to undeprecated qcom,calibration-variant The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-1-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi index a6d4390efa7c..be76bc39ac27 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi @@ -251,7 +251,7 @@ &wifi1 { status = "okay"; nvmem-cell-names = "pre-calibration"; nvmem-cells = <&precal_art_5000>; - qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; + qcom,calibration-variant = "ALFA-Network-AP120C-AC"; }; &usb3_hs_phy { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts index 6640ea7b6acb..15baaf0d1529 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts @@ -179,13 +179,13 @@ &mdio { &wifi0 { status = "okay"; - qcom,ath10k-calibration-variant = "8devices-Jalapeno"; + qcom,calibration-variant = "8devices-Jalapeno"; }; &wifi1 { status = "okay"; - qcom,ath10k-calibration-variant = "8devices-Jalapeno"; + qcom,calibration-variant = "8devices-Jalapeno"; }; &usb3_ss_phy { From f1bf8a943bea70c7432731c11761d161882aeedc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:58:59 +0100 Subject: [PATCH 067/308] arm64: dts: qcom: msm8998: Switch to undeprecated qcom,calibration-variant The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-2-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts index 901f6ac0084d..f160ba562b0a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts @@ -101,5 +101,5 @@ i2c5_hid_active: i2c5-hid-active-state { }; &wifi { - qcom,ath10k-calibration-variant = "Lenovo_Miix630"; + qcom,calibration-variant = "Lenovo_Miix630"; }; From 41eeff2fc2292c56592206741b05fde63acef4f0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:00 +0100 Subject: [PATCH 068/308] arm64: dts: qcom: qrb2210-rb1: Switch to undeprecated qcom,calibration-variant The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-3-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 7a789b41c2f1..bef1fa782f12 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -620,7 +620,7 @@ &wifi { vdd-1.8-xo-supply = <&pm4125_l13>; vdd-1.3-rfa-supply = <&pm4125_l10>; vdd-3.3-ch0-supply = <&pm4125_l22>; - qcom,ath10k-calibration-variant = "Thundercomm_RB1"; + qcom,calibration-variant = "Thundercomm_RB1"; firmware-name = "qcm2290"; status = "okay"; }; From a83356f7ba575f536dd2bf2338cafd0d1d2d51ec Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:01 +0100 Subject: [PATCH 069/308] arm64: dts: qcom: qrb4210-rb2: Switch to undeprecated qcom,calibration-variant The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-4-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 52db18847803..d485249bcda4 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -749,7 +749,7 @@ &wifi { vdd-1.8-xo-supply = <&vreg_l16a_1p3>; vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l23a_3p3>; - qcom,ath10k-calibration-variant = "Thundercomm_RB2"; + qcom,calibration-variant = "Thundercomm_RB2"; firmware-name = "qrb4210"; status = "okay"; From 4f8fc2038b3ce9fa1fd52491e774e43bf5e67547 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:02 +0100 Subject: [PATCH 070/308] arm64: dts: qcom: sc7180: Switch to undeprecated qcom,calibration-variant The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-5-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index f57976906d63..8fee8d7a7d4c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -188,7 +188,7 @@ &sound_multimedia1_codec { }; &wifi { - qcom,ath10k-calibration-variant = "GO_HOMESTAR"; + qcom,calibration-variant = "GO_HOMESTAR"; }; /* PINCTRL - modifications to sc7180-trogdor.dtsi */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts index 655bea928e52..26514640a1ae 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts @@ -79,7 +79,7 @@ &pp3300_dx_edp { }; &wifi { - qcom,ath10k-calibration-variant = "GO_KINGOFTOWN"; + qcom,calibration-variant = "GO_KINGOFTOWN"; }; /* PINCTRL - modifications to sc7180-trogdor.dtsi */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index c3fd6760de7a..eb9c9e713a89 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -69,7 +69,7 @@ &trackpad { }; &wifi { - qcom,ath10k-calibration-variant = "GO_LAZOR"; + qcom,calibration-variant = "GO_LAZOR"; }; /* PINCTRL - modifications to sc7180-trogdor.dtsi */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi index 89034b6702f4..a2224de841b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi @@ -59,5 +59,5 @@ CROS_STD_MAIN_KEYMAP }; &wifi { - qcom,ath10k-calibration-variant = "GO_PAZQUEL360"; + qcom,calibration-variant = "GO_PAZQUEL360"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index f7300ffbb451..4f5ab378cf8e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -181,7 +181,7 @@ &usb_c1 { }; &wifi { - qcom,ath10k-calibration-variant = "GO_POMPOM"; + qcom,calibration-variant = "GO_POMPOM"; }; /* PINCTRL - board-specific pinctrl */ diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index d4925be3b1fc..17908c936520 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -196,7 +196,7 @@ &pp2800_wf_cam { }; &wifi { - qcom,ath10k-calibration-variant = "GO_WORMDINGLER"; + qcom,calibration-variant = "GO_WORMDINGLER"; }; /* From 218718e0c2536bc17c1a10eed35e99100bed5b46 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:03 +0100 Subject: [PATCH 071/308] arm64: dts: qcom: sdm845: Switch to undeprecated qcom,calibration-variant The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-6-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 2 +- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index cd6af2fbc5ef..8fd761aa571e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1172,7 +1172,7 @@ &wifi { vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; qcom,snoc-host-cap-8bit-quirk; - qcom,ath10k-calibration-variant = "Thundercomm_DB845C"; + qcom,calibration-variant = "Thundercomm_DB845C"; }; /* PINCTRL - additions to nodes defined in sdm845.dtsi */ diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 2391f842c903..aa482e8fd9e2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -789,7 +789,7 @@ &wifi { vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; qcom,snoc-host-cap-8bit-quirk; - qcom,ath10k-calibration-variant = "Qualcomm_sdm845mtp"; + qcom,calibration-variant = "Qualcomm_sdm845mtp"; }; /* PINCTRL - additions to nodes defined in sdm845.dtsi */ diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index f18050848cd8..bf45511b24b3 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -910,7 +910,7 @@ &wifi { vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; qcom,snoc-host-cap-8bit-quirk; - qcom,ath10k-calibration-variant = "Lenovo_C630"; + qcom,calibration-variant = "Lenovo_C630"; }; &crypto { From 020ec05884e97175a181b33eb60d556ceaa32de8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:04 +0100 Subject: [PATCH 072/308] arm64: dts: qcom: sda660-ifc6560: Switch to undeprecated qcom,calibration-variant The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-7-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index d402f4c85b11..4a5107689069 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -507,7 +507,7 @@ &wifi { vdd-3.3-ch0-supply = <&vreg_l19a_3p3>; vdd-3.3-ch1-supply = <&vreg_l8b_3p3>; - qcom,ath10k-calibration-variant = "Inforce_IFC6560"; + qcom,calibration-variant = "Inforce_IFC6560"; status = "okay"; }; From d39d4fd49337be1e8f6c28e4d31344a2124acb57 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:05 +0100 Subject: [PATCH 073/308] arm64: dts: qcom: sm6115: Switch to undeprecated qcom,calibration-variant The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-8-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 2 +- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index f60d36c03b9b..ad347ccd1975 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -566,7 +566,7 @@ &wifi { vdd-1.3-rfa-supply = <&pm6125_l17a>; vdd-3.3-ch0-supply = <&pm6125_l23a>; - qcom,ath10k-calibration-variant = "Fxtec_QX1050"; + qcom,calibration-variant = "Fxtec_QX1050"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 9d78bb3f7190..c17545111f49 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -379,7 +379,7 @@ &wifi { vdd-1.8-xo-supply = <&pm6125_l16>; vdd-1.3-rfa-supply = <&pm6125_l17>; vdd-3.3-ch0-supply = <&pm6125_l23>; - qcom,ath10k-calibration-variant = "Lenovo_P11"; + qcom,calibration-variant = "Lenovo_P11"; status = "okay"; }; From b187df5a0224d2e1b5ab8ea19c98d6ebbe554fe8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:06 +0100 Subject: [PATCH 074/308] arm64: dts: qcom: sm8150-hdk: Switch to undeprecated qcom,calibration-variant The property qcom,ath10k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-9-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 6ea883b1edfa..9ac9854b35fd 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -719,5 +719,5 @@ &wifi { vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; - qcom,ath10k-calibration-variant = "Qualcomm_sm8150hdk"; + qcom,calibration-variant = "Qualcomm_sm8150hdk"; }; From cfbcd6d483dc7203db230cb24c9ee286033682fa Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:07 +0100 Subject: [PATCH 075/308] arm64: dts: qcom: qcm6490: Switch to undeprecated qcom,calibration-variant The property qcom,ath11k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-10-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 2 +- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 2 +- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 2 +- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 377e92c554e1..356cee8aeba9 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -1282,6 +1282,6 @@ &venus { }; &wifi { - qcom,ath11k-calibration-variant = "Fairphone_5"; + qcom,calibration-variant = "Fairphone_5"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 9209efcc49b5..f26c5c2fde6b 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -755,7 +755,7 @@ &usb_1_qmpphy { &wifi { memory-region = <&wlan_fw_mem>; - qcom,ath11k-calibration-variant = "Qualcomm_qcm6490idp"; + qcom,calibration-variant = "Qualcomm_qcm6490idp"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index 75930f957696..712f29fbe85e 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -953,7 +953,7 @@ &usb_1_qmpphy { }; &wifi { - qcom,ath11k-calibration-variant = "SHIFTphone_8"; + qcom,calibration-variant = "SHIFTphone_8"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index a651e9b6d56b..fa7c54f882a4 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1196,7 +1196,7 @@ &venus { &wifi { memory-region = <&wlan_fw_mem>; - qcom,ath11k-calibration-variant = "Qualcomm_rb3gen2"; + qcom,calibration-variant = "Qualcomm_rb3gen2"; status = "okay"; }; From fda76284e9b4c4606758fb62cfd81dd57e8f2516 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:08 +0100 Subject: [PATCH 076/308] arm64: dts: qcom: sa8775p-ride: Switch to undeprecated qcom,calibration-variant The property qcom,ath11k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-11-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi index 1697c11f5c65..a14564054e94 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -878,7 +878,7 @@ wifi@0 { compatible = "pci17cb,1101"; reg = <0x10000 0x0 0x0 0x0 0x0>; - qcom,ath11k-calibration-variant = "QC_SA8775P_Ride"; + qcom,calibration-variant = "QC_SA8775P_Ride"; vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; vddaon-supply = <&vreg_pmu_aon_0p59>; From d12ce84c88013cd4ea770d244d44362f691e1690 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:09 +0100 Subject: [PATCH 077/308] arm64: dts: qcom: sc8280xp: Switch to undeprecated qcom,calibration-variant The property qcom,ath11k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-12-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 2 +- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 2 +- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 75adaa19d1c3..e7251b76d91e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -686,7 +686,7 @@ wifi@0 { vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - qcom,ath11k-calibration-variant = "QC_8280XP_CRD"; + qcom,calibration-variant = "QC_8280XP_CRD"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index f3190f408f4b..6ddb954a04fd 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -998,7 +998,7 @@ wifi@0 { vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - qcom,ath11k-calibration-variant = "LE_X13S"; + qcom,calibration-variant = "LE_X13S"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index ae5daeac8fe2..d00889fa6f0b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -536,7 +536,7 @@ wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; - qcom,ath11k-calibration-variant = "MS_SP9_5G"; + qcom,calibration-variant = "MS_SP9_5G"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index fa9d94105052..812251324002 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -670,7 +670,7 @@ wifi@0 { vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - qcom,ath11k-calibration-variant = "MS_Volterra"; + qcom,calibration-variant = "MS_Volterra"; }; }; From 37eb85ae550004790c98605762c2e0326a82e160 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 25 Feb 2025 10:59:10 +0100 Subject: [PATCH 078/308] arm64: dts: qcom: sm8250-elish: Switch to undeprecated qcom,calibration-variant The property qcom,ath11k-calibration-variant was deprecated in favor of recently introduced generic qcom,calibration-variant, common to all Qualcomm Atheros WiFi bindings. Change will affect out of tree users, like other projects, of this DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250225-dts-qcom-wifi-calibration-v1-13-347e9c72dcfc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 813b009b7bd6..01a321d801af 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -699,7 +699,7 @@ wifi@0 { vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; - qcom,ath11k-calibration-variant = "Xiaomi_Pad_5Pro"; + qcom,calibration-variant = "Xiaomi_Pad_5Pro"; }; }; From 83934b5d6b1a9664867beb4e822a6f9fa1fac687 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Fri, 21 Feb 2025 15:39:57 +0800 Subject: [PATCH 079/308] arm64: dts: qcom: qcs615: Add Command DB support Command DB is a database in the shared memory of QCOM SoCs, that provides a mapping between resource key and the resource address for a system resource managed by a remote processor. The data is stored in a shared memory region and is loaded by the remote processor. Therefore, enabling Command DB ensures that those resources function properly. Signed-off-by: Lijuan Gao Link: https://lore.kernel.org/r/20250221-add_command_db_support-v1-1-d60acbf913aa@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index f4abfad474ea..4e060ce68e6c 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -417,6 +417,12 @@ reserved-memory { #size-cells = <2>; ranges; + aop_cmd_db_mem: aop-cmd-db@85f20000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85f20000 0x0 0x20000>; + no-map; + }; + smem_region: smem@86000000 { compatible = "qcom,smem"; reg = <0x0 0x86000000 0x0 0x200000>; From 09a3840bcb72bcd9b43cbffbb7dedccf85e6d558 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 22 Feb 2025 14:00:47 +0100 Subject: [PATCH 080/308] arm64: dts: qcom: sdm632-fairphone-fp3: Move status properties last As is common style nowadays, move the status properties to be the last property of a node. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250222-fp3-remoteprocs-firmware-v1-1-237ed21c334a@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 2c1172aa97e4..957288853da2 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -45,10 +45,11 @@ vph_pwr: vph-pwr-regulator { }; &hsusb_phy { - status = "okay"; vdd-supply = <&pm8953_l3>; vdda-pll-supply = <&pm8953_l7>; vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; }; &i2c_3 { @@ -85,8 +86,8 @@ &lpass { }; &pm8953_resin { - status = "okay"; linux,code = ; + status = "okay"; }; &pmi632_lpg { @@ -148,17 +149,19 @@ &pmi632_vib { }; &sdhc_1 { - status = "okay"; vmmc-supply = <&pm8953_l8>; vqmmc-supply = <&pm8953_l5>; + + status = "okay"; }; &sdhc_2 { - status = "okay"; vmmc-supply = <&pm8953_l11>; vqmmc-supply = <&pm8953_l12>; cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + status = "okay"; }; &rpm_requests { @@ -276,9 +279,9 @@ &usb_dwc3_hs { }; &wcnss { - status = "okay"; - vddpx-supply = <&pm8953_l5>; + + status = "okay"; }; &wcnss_iris { From a4600b160eca7f889c4b4a370d42e4619fa5162a Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 22 Feb 2025 14:00:48 +0100 Subject: [PATCH 081/308] arm64: dts: qcom: sdm632-fairphone-fp3: Add newlines between regulator nodes As is common style nowadays, make sure there's an empty line between regulator subnodes. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250222-fp3-remoteprocs-firmware-v1-2-237ed21c334a@lucaweiss.eu Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm632-fairphone-fp3.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 957288853da2..08ffe77d762c 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -178,10 +178,12 @@ pm8953_s3: s3 { regulator-min-microvolt = <984000>; regulator-max-microvolt = <1240000>; }; + pm8953_s4: s4 { regulator-min-microvolt = <1036000>; regulator-max-microvolt = <2040000>; }; + pm8953_s5: s5 { regulator-min-microvolt = <1036000>; regulator-max-microvolt = <2040000>; @@ -191,66 +193,82 @@ pm8953_l1: l1 { regulator-min-microvolt = <975000>; regulator-max-microvolt = <1050000>; }; + pm8953_l2: l2 { regulator-min-microvolt = <975000>; regulator-max-microvolt = <1175000>; }; + pm8953_l3: l3 { regulator-min-microvolt = <925000>; regulator-max-microvolt = <925000>; }; + pm8953_l5: l5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + pm8953_l6: l6 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + pm8953_l7: l7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1900000>; }; + pm8953_l8: l8 { regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; + pm8953_l9: l9 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; }; + pm8953_l10: l10 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3000000>; }; + pm8953_l11: l11 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; }; + pm8953_l12: l12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2950000>; }; + pm8953_l13: l13 { regulator-min-microvolt = <3125000>; regulator-max-microvolt = <3125000>; }; + pm8953_l16: l16 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + pm8953_l17: l17 { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; }; + pm8953_l19: l19 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; }; + pm8953_l22: l22 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; + pm8953_l23: l23 { regulator-min-microvolt = <975000>; regulator-max-microvolt = <1225000>; From 9ab813d5191f61301dbaeaf8e82d21e689b080f4 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 22 Feb 2025 14:00:49 +0100 Subject: [PATCH 082/308] arm64: dts: qcom: sdm632-fairphone-fp3: Add firmware-name for adsp & wcnss Set the paths where the device-specific firmware can be found for this device. Fairphone 3 was shipped with secure-boot off so any testkey-signed firmware is accepted. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250222-fp3-remoteprocs-firmware-v1-3-237ed21c334a@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 08ffe77d762c..5611209dbfa4 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -82,6 +82,8 @@ nfc@28 { }; &lpass { + firmware-name = "qcom/msm8953/fairphone/fp3/adsp.mbn"; + status = "okay"; }; @@ -297,11 +299,16 @@ &usb_dwc3_hs { }; &wcnss { + firmware-name = "qcom/msm8953/fairphone/fp3/wcnss.mbn"; vddpx-supply = <&pm8953_l5>; status = "okay"; }; +&wcnss_ctrl { + firmware-name = "qcom/msm8953/fairphone/fp3/WCNSS_qcom_wlan_nv.bin"; +}; + &wcnss_iris { compatible = "qcom,wcn3680"; From d0c38cbe3556fea446b9350ec597a8e9c2cdaf36 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 22 Feb 2025 14:00:50 +0100 Subject: [PATCH 083/308] arm64: dts: qcom: sdm632-fairphone-fp3: Enable modem Add the necessary supplies and set an appropriete firmware-name for the modem and enable it. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250222-fp3-remoteprocs-firmware-v1-4-237ed21c334a@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 5611209dbfa4..31ed26c31e6e 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -87,6 +87,14 @@ &lpass { status = "okay"; }; +&mpss { + firmware-name = "qcom/msm8953/fairphone/fp3/mba.mbn", + "qcom/msm8953/fairphone/fp3/modem.mbn"; + pll-supply = <&pm8953_l7>; + + status = "okay"; +}; + &pm8953_resin { linux,code = ; status = "okay"; From 91e3ac15523fda23f5429d641248ab31b0d46fe7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Feb 2025 10:07:50 +0100 Subject: [PATCH 084/308] arm64: dts: qcom: sm8750: Change labels to lower-case DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250219090751.124267-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 3bbd7d18598e..abb92c81c76b 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -95,11 +95,11 @@ cpu6: cpu@10000 { compatible = "qcom,oryon"; reg = <0x0 0x10000>; enable-method = "psci"; - next-level-cache = <&L2_1>; + next-level-cache = <&l2_1>; power-domains = <&cpu_pd6>; power-domain-names = "psci"; - L2_1: l2-cache { + l2_1: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -111,7 +111,7 @@ cpu7: cpu@10100 { compatible = "qcom,oryon"; reg = <0x0 0x10100>; enable-method = "psci"; - next-level-cache = <&L2_1>; + next-level-cache = <&l2_1>; power-domains = <&cpu_pd7>; power-domain-names = "psci"; }; From 27fd3266e8bd615af8ec5e91addac0b1dedc0b29 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Feb 2025 10:07:51 +0100 Subject: [PATCH 085/308] arm64: dts: qcom: Correct white-space style There should be exactly one space before and after '=', and one space before '{'. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250219090751.124267-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 40 +++++++++---------- .../boot/dts/qcom/msm8917-xiaomi-riva.dts | 2 +- arch/arm64/boot/dts/qcom/msm8917.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs615.dtsi | 16 ++++---- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 5 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 942290028972..cac58352182e 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -876,11 +876,11 @@ frame@b128000 { pcie1: pcie@10000000 { compatible = "qcom,pcie-ipq9574"; - reg = <0x10000000 0xf1d>, - <0x10000f20 0xa8>, - <0x10001000 0x1000>, - <0x000f8000 0x4000>, - <0x10100000 0x1000>; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x10001000 0x1000>, + <0x000f8000 0x4000>, + <0x10100000 0x1000>; reg-names = "dbi", "elbi", "atu", "parf", "config"; device_type = "pci"; linux,pci-domain = <1>; @@ -956,11 +956,11 @@ pcie1: pcie@10000000 { pcie3: pcie@18000000 { compatible = "qcom,pcie-ipq9574"; - reg = <0x18000000 0xf1d>, - <0x18000f20 0xa8>, - <0x18001000 0x1000>, - <0x000f0000 0x4000>, - <0x18100000 0x1000>; + reg = <0x18000000 0xf1d>, + <0x18000f20 0xa8>, + <0x18001000 0x1000>, + <0x000f0000 0x4000>, + <0x18100000 0x1000>; reg-names = "dbi", "elbi", "atu", "parf", "config"; device_type = "pci"; linux,pci-domain = <3>; @@ -1036,11 +1036,11 @@ pcie3: pcie@18000000 { pcie2: pcie@20000000 { compatible = "qcom,pcie-ipq9574"; - reg = <0x20000000 0xf1d>, - <0x20000f20 0xa8>, - <0x20001000 0x1000>, - <0x00088000 0x4000>, - <0x20100000 0x1000>; + reg = <0x20000000 0xf1d>, + <0x20000f20 0xa8>, + <0x20001000 0x1000>, + <0x00088000 0x4000>, + <0x20100000 0x1000>; reg-names = "dbi", "elbi", "atu", "parf", "config"; device_type = "pci"; linux,pci-domain = <2>; @@ -1116,11 +1116,11 @@ pcie2: pcie@20000000 { pcie0: pci@28000000 { compatible = "qcom,pcie-ipq9574"; - reg = <0x28000000 0xf1d>, - <0x28000f20 0xa8>, - <0x28001000 0x1000>, - <0x00080000 0x4000>, - <0x28100000 0x1000>; + reg = <0x28000000 0xf1d>, + <0x28000f20 0xa8>, + <0x28001000 0x1000>, + <0x00080000 0x4000>, + <0x28100000 0x1000>; reg-names = "dbi", "elbi", "atu", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; diff --git a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts index f1d22535fedd..df135f9891a8 100644 --- a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts +++ b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts @@ -119,7 +119,7 @@ bq27426@55 { monitored-battery = <&battery>; }; - bq25601@6b{ + bq25601@6b { compatible = "ti,bq25601"; reg = <0x6b>; interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qcom/msm8917.dtsi index 7bf58dd0146e..9d8358745c91 100644 --- a/arch/arm64/boot/dts/qcom/msm8917.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi @@ -587,7 +587,7 @@ tsens_s4_p2: s4-p2@217 { bits = <1 6>; }; - tsens_s9_p1: s9-p1@230{ + tsens_s9_p1: s9-p1@230 { reg = <0x230 1>; bits = <0 6>; }; diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 4e060ce68e6c..ec427bb84ec8 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -1825,7 +1825,7 @@ replicator@6046000 { in-ports { port { replicator0_in: endpoint { - remote-endpoint= <&tmc_etf_out>; + remote-endpoint = <&tmc_etf_out>; }; }; }; @@ -1838,7 +1838,7 @@ port@1 { reg = <1>; replicator0_out1: endpoint { - remote-endpoint= <&replicator1_in>; + remote-endpoint = <&replicator1_in>; }; }; }; @@ -1878,7 +1878,7 @@ replicator@604a000 { in-ports { port { replicator1_in: endpoint { - remote-endpoint= <&replicator0_out1>; + remote-endpoint = <&replicator0_out1>; }; }; }; @@ -1886,7 +1886,7 @@ replicator1_in: endpoint { out-ports { port { replicator1_out: endpoint { - remote-endpoint= <&funnel_swao_in6>; + remote-endpoint = <&funnel_swao_in6>; }; }; }; @@ -2317,7 +2317,7 @@ port@6 { reg = <6>; funnel_swao_in6: endpoint { - remote-endpoint= <&replicator1_out>; + remote-endpoint = <&replicator1_out>; }; }; @@ -2325,7 +2325,7 @@ port@7 { reg = <7>; funnel_swao_in7: endpoint { - remote-endpoint= <&tpda_swao_out>; + remote-endpoint = <&tpda_swao_out>; }; }; }; @@ -2349,7 +2349,7 @@ tmc@6b09000 { in-ports { port { tmc_etf_swao_in: endpoint { - remote-endpoint= <&funnel_swao_out>; + remote-endpoint = <&funnel_swao_out>; }; }; }; @@ -2357,7 +2357,7 @@ tmc_etf_swao_in: endpoint { out-ports { port { tmc_etf_swao_out: endpoint { - remote-endpoint= <&replicator_swao_in>; + remote-endpoint = <&replicator_swao_in>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index abb92c81c76b..f81a3c3ae334 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -990,7 +990,7 @@ uart14: serial@898000 { clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; From 97bf440d95f1bafd8345739663ad3c04627f1505 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 18 Feb 2025 11:21:48 +0530 Subject: [PATCH 086/308] arm64: dts: qcom: sm8750: Add RPMh sleep stats Add RPMh stats to read low power statistics for various subsystem and SoC sleep modes. Signed-off-by: Maulik Shah Reviewed-by: Konrad Dybcio Tested-by: Konrad Dybcio # 8750 QRD Link: https://lore.kernel.org/r/20250218-sm8750_stats-v1-1-8902e213f82d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index f81a3c3ae334..529e4e4e1d0e 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -1978,6 +1978,11 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c3f0000 0x0 0x400>; + }; + spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c400000 0x0 0x3000>, From d09ab685a8f51ba412d37305ea62628a01cbea57 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 17 Feb 2025 18:55:23 +0100 Subject: [PATCH 087/308] arm64: dts: qcom: x1e80100-qcp: Add WiFi/BT pwrseq Add the WiFi/BT nodes for QCP and describe the regulators for the WCN7850 combo chip using the new power sequencing bindings. All voltages are derived from chained fixed regulators controlled using a single GPIO. The same setup also works for CRD (and likely most of the other X1E80100 laptops). However, unlike the QCP they use soldered or removable M.2 cards supplied by a single 3.3V fixed regulator. The other necessary voltages are then derived inside the M.2 card. Describing this properly requires new bindings, so this commit only adds QCP for now. Signed-off-by: Stephan Gerhold Reviewed-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250217-x1e80100-pwrseq-qcp-v3-1-a0525cc01666@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 144 ++++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 600d0c8a08ef..28086a2bcf4c 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -17,6 +17,7 @@ / { aliases { serial0 = &uart21; + serial1 = &uart14; }; wcd938x: audio-codec { @@ -281,6 +282,42 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + usb-1-ss0-sbu-mux { compatible = "onnn,fsusb42", "gpio-sbu-mux"; @@ -337,6 +374,65 @@ usb_1_ss2_sbu_mux: endpoint { }; }; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -828,6 +924,23 @@ &pcie4_phy { status = "okay"; }; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie6a { perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; @@ -1138,6 +1251,37 @@ wcd_default: wcd-reset-n-active-state { bias-disable; output-low; }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; }; &uart21 { From aeb520ce520a2fc69e7d692a44f72da431769b0a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 27 Feb 2025 09:55:26 +0100 Subject: [PATCH 088/308] arm64: dts: qcom: sm8650: add all 8 coresight ETE nodes Only CPU0 Embedded Trace Extension (ETE) was added, but there's one for all 8 CPUs, so add the missing ones. Fixes: 256e6937e48a ("arm64: dts: qcom: sm8650: Add coresight nodes") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250227-topic-sm8650-upstream-add-all-coresight-cpus-v3-1-48ae516be0d5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 163 ++++++++++++++++++++++++++- 1 file changed, 161 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 719ad437756a..d5037cc306c2 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -438,7 +438,7 @@ cluster_sleep_1: cluster-sleep-1 { }; }; - ete0 { + ete-0 { compatible = "arm,embedded-trace-extension"; cpu = <&cpu0>; @@ -452,15 +452,174 @@ ete0_out_funnel_ete: endpoint { }; }; + ete-1 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu1>; + + out-ports { + port { + ete1_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete1>; + }; + }; + }; + }; + + ete-2 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu2>; + + out-ports { + port { + ete2_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete2>; + }; + }; + }; + }; + + ete-3 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu3>; + + out-ports { + port { + ete3_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete3>; + }; + }; + }; + }; + + ete-4 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu4>; + + out-ports { + port { + ete4_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete4>; + }; + }; + }; + }; + + ete-5 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu5>; + + out-ports { + port { + ete5_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete5>; + }; + }; + }; + }; + + ete-6 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu6>; + + out-ports { + port { + ete6_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete6>; + }; + }; + }; + }; + + ete-7 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu7>; + + out-ports { + port { + ete7_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete7>; + }; + }; + }; + }; + funnel-ete { compatible = "arm,coresight-static-funnel"; in-ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ete_in_ete0: endpoint { remote-endpoint = <&ete0_out_funnel_ete>; }; }; + + port@1 { + reg = <1>; + + funnel_ete_in_ete1: endpoint { + remote-endpoint = <&ete1_out_funnel_ete>; + }; + }; + + port@2 { + reg = <2>; + + funnel_ete_in_ete2: endpoint { + remote-endpoint = <&ete2_out_funnel_ete>; + }; + }; + + port@3 { + reg = <3>; + + funnel_ete_in_ete3: endpoint { + remote-endpoint = <&ete3_out_funnel_ete>; + }; + }; + + port@4 { + reg = <4>; + + funnel_ete_in_ete4: endpoint { + remote-endpoint = <&ete4_out_funnel_ete>; + }; + }; + + port@5 { + reg = <5>; + + funnel_ete_in_ete5: endpoint { + remote-endpoint = <&ete5_out_funnel_ete>; + }; + }; + + port@6 { + reg = <6>; + + funnel_ete_in_ete6: endpoint { + remote-endpoint = <&ete6_out_funnel_ete>; + }; + }; + + port@7 { + reg = <7>; + + funnel_ete_in_ete7: endpoint { + remote-endpoint = <&ete7_out_funnel_ete>; + }; + }; }; out-ports { From 0783c8b3c06b9cf16b5108d558e2faffb8c533b7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 4 Mar 2025 18:10:46 +0100 Subject: [PATCH 089/308] arm64: dts: qcom: x1e80100-romulus: Keep L12B and L15B always on These regulators power some electronic components onboard. They're most likely kept online by other pieces of firmware, but you can never be sure enough. Fixes: 09d77be56093 ("arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devices") Reported-by: Johan Hovold Signed-off-by: Konrad Dybcio Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20250304-topic-sl7_vregs_aon-v1-1-b2dc706e4157@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 5867953c7356..6a883fafe3c7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -510,6 +510,7 @@ vreg_l12b: ldo12 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l13b: ldo13 { @@ -531,6 +532,7 @@ vreg_l15b: ldo15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l16b: ldo16 { From 9db543299ec0d765083dd9a0bdb15707b33f7d73 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 4 Mar 2025 12:57:46 +0200 Subject: [PATCH 090/308] arm64: dts: qcom: x1e80100-crd: Describe the Parade PS8830 retimers The X Elite CRD board comes with 3 Parade PS8830 retimers, one for each Type-C port. These handle the orientation and altmode switching and are controlled over I2C. In the connection chain, they sit between the USB/DisplayPort combo PHY and the Type-C connector. Describe the retimers and all gpio controlled voltage regulators used by each retimer. Also, modify the pmic glink graph to include the retimers in between the SuperSpeed/Sideband in endpoints and the QMP PHY out endpoints. Reviewed-by: Johan Hovold Tested-by: Johan Hovold Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20250304-x1e80100-dts-crd-t14s-enable-typec-retimers-v6-1-e5a49fae4e94@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 449 ++++++++++++++++++++++++++- 1 file changed, 443 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 296b41409ad1..34e203fb7a4b 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -97,7 +97,15 @@ port@1 { reg = <1>; pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; }; }; }; @@ -126,7 +134,15 @@ port@1 { reg = <1>; pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; }; }; }; @@ -155,7 +171,15 @@ port@1 { reg = <1>; pmic_glink_ss2_ss_in: endpoint { - remote-endpoint = <&usb_1_ss2_qmpphy_out>; + remote-endpoint = <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss2_con_sbu_out>; }; }; }; @@ -308,6 +332,150 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -728,6 +896,177 @@ keyboard@3a { }; }; +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK5>; + + vdd-supply = <&vreg_rtmr2_1p15>; + vdd33-supply = <&vreg_rtmr2_3p3>; + vdd33-cap-supply = <&vreg_rtmr2_3p3>; + vddar-supply = <&vreg_rtmr2_1p15>; + vddat-supply = <&vreg_rtmr2_1p15>; + vddio-supply = <&vreg_rtmr2_1p8>; + + reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr2_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + &i2c8 { clock-frequency = <400000>; @@ -876,6 +1215,26 @@ &pcie6a_phy { status = "okay"; }; +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pm8550ve_8_gpios { misc_3p3_reg_en: misc-3p3-reg-en-state { pins = "gpio6"; @@ -889,6 +1248,17 @@ misc_3p3_reg_en: misc-3p3-reg-en-state { }; }; +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pmc8380_3_gpios { edp_bl_en: edp-bl-en-state { pins = "gpio4"; @@ -899,6 +1269,17 @@ edp_bl_en: edp-bl-en-state { }; }; +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &qupv3_0 { status = "okay"; }; @@ -1136,6 +1517,20 @@ wake-n-pins { }; }; + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_default: rtmr2-reset-n-active-state { + pins = "gpio185"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + tpad_default: tpad-default-state { pins = "gpio3"; function = "gpio"; @@ -1157,6 +1552,48 @@ reset-n-pins { }; }; + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p15_reg_en: usb2-pwr-1p15-reg-en-state { + pins = "gpio189"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p8_reg_en: usb2-pwr-1p8-reg-en-state { + pins = "gpio126"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state { + pins = "gpio187"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio191"; function = "gpio"; @@ -1207,7 +1644,7 @@ &usb_1_ss0_dwc3_hs { }; &usb_1_ss0_qmpphy_out { - remote-endpoint = <&pmic_glink_ss0_ss_in>; + remote-endpoint = <&retimer_ss0_ss_in>; }; &usb_1_ss1_hsphy { @@ -1239,7 +1676,7 @@ &usb_1_ss1_dwc3_hs { }; &usb_1_ss1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss1_ss_in>; + remote-endpoint = <&retimer_ss1_ss_in>; }; &usb_1_ss2_hsphy { @@ -1271,5 +1708,5 @@ &usb_1_ss2_dwc3_hs { }; &usb_1_ss2_qmpphy_out { - remote-endpoint = <&pmic_glink_ss2_ss_in>; + remote-endpoint = <&retimer_ss2_ss_in>; }; From d9ff9537baea7433f9f6479876b8f1ef4d822bc7 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 4 Mar 2025 12:57:47 +0200 Subject: [PATCH 091/308] arm64: dts: qcom: x1e80100-crd: Enable external DisplayPort support The X Elite CRD provides external DisplayPort on all 3 USB Type-C ports. Each one of this ports is connected to a dedicated DisplayPort controller. Due to support missing in the USB/DisplayPort combo PHY driver, the external DisplayPort is limited to 2 lanes. So enable all 3 remaining DisplayPort controllers and limit their data lanes number to 2. Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold Tested-by: Johan Hovold Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20250304-x1e80100-dts-crd-t14s-enable-typec-retimers-v6-2-e5a49fae4e94@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 34e203fb7a4b..53f329c32019 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1117,6 +1117,30 @@ &mdss { status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + data-lanes = <0 1>; +}; + &mdss_dp3 { compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; From b7e331d18cd012bf972269f676d292604e23ae5e Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 4 Mar 2025 12:57:48 +0200 Subject: [PATCH 092/308] arm64: dts: qcom: x1e80100-t14s: Describe the Parade PS8830 retimers The Lenovo ThinkPad T14s Gen6 laptop comes with 3 Parade PS8830 retimers, one for each Type-C port. These handle the orientation and altmode switching and are controlled over I2C. In the connection chain, they sit between the USB/DisplayPort combo PHY and the Type-C connector. Describe the retimers and all gpio controlled voltage regulators used by each retimer. Also, modify the pmic glink graph to include the retimers in between the SuperSpeed/Sideband in endpoints and the QMP PHY out endpoints. Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold Tested-by: Johan Hovold Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20250304-x1e80100-dts-crd-t14s-enable-typec-retimers-v6-3-e5a49fae4e94@linaro.org Signed-off-by: Bjorn Andersson --- .../qcom/x1e78100-lenovo-thinkpad-t14s.dts | 304 +++++++++++++++++- 1 file changed, 300 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts index b2c2347f54fa..9c0903b84363 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts @@ -92,7 +92,15 @@ port@1 { reg = <1>; pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; }; }; }; @@ -121,7 +129,15 @@ port@1 { reg = <1>; pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; }; }; }; @@ -169,6 +185,102 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -607,6 +719,63 @@ keyboard@3a { }; }; +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + &i2c5 { clock-frequency = <400000>; @@ -655,6 +824,63 @@ eusb6_repeater: redriver@4f { }; }; +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + &i2c8 { clock-frequency = <400000>; @@ -777,6 +1003,37 @@ &pcie6a_phy { status = "okay"; }; +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pmc8380_3_gpios { edp_bl_en: edp-bl-en-state { pins = "gpio4"; @@ -787,6 +1044,17 @@ edp_bl_en: edp-bl-en-state { }; }; +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &qupv3_0 { status = "okay"; }; @@ -1007,6 +1275,34 @@ wake-n-pins { }; }; + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio191"; function = "gpio"; @@ -1045,7 +1341,7 @@ &usb_1_ss0_dwc3_hs { }; &usb_1_ss0_qmpphy_out { - remote-endpoint = <&pmic_glink_ss0_ss_in>; + remote-endpoint = <&retimer_ss0_ss_in>; }; &usb_1_ss1_hsphy { @@ -1077,7 +1373,7 @@ &usb_1_ss1_dwc3_hs { }; &usb_1_ss1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss1_ss_in>; + remote-endpoint = <&retimer_ss1_ss_in>; }; &usb_2 { From 49215915cc57e6d506e464df2ccc810f11babd26 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 4 Mar 2025 12:57:49 +0200 Subject: [PATCH 093/308] arm64: dts: qcom: x1e80100-t14s: Enable external DisplayPort support The Lenovo ThinkPad T14s Gen6 provides external DisplayPort on all 2 USB Type-C ports. Each one of this ports is connected to a dedicated DisplayPort controller. Due to support missing in the USB/DisplayPort combo PHY driver, the external DisplayPort is limited to 2 lanes. So enable the first and second DisplayPort controllers and limit their data lanes number to 2. Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold Tested-by: Johan Hovold Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20250304-x1e80100-dts-crd-t14s-enable-typec-retimers-v6-4-e5a49fae4e94@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts index 9c0903b84363..05b2f3bf1fc8 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts @@ -923,6 +923,22 @@ &mdss { status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; +}; + &mdss_dp3 { compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; From eb8b09e61bd2419263a15c37b068982be620eab6 Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Tue, 25 Feb 2025 19:38:52 +0300 Subject: [PATCH 094/308] arm64: dts: qcom: sdm845: enable gmu Leave gmu enabled, because it's only probed when GPU is. Reviewed-by: Konrad Dybcio Signed-off-by: Dzmitry Sankouski Link: https://lore.kernel.org/r/20250225-starqltechn_integration_upstream-v9-1-a5d80375cb66@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ---- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 4 ---- arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 4 ---- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 -- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 4 ---- 10 files changed, 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 743c339ba108..b7e514f81f92 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -741,10 +741,6 @@ touchscreen@10 { }; }; -&gmu { - status = "okay"; -}; - &gpu { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 8fd761aa571e..a5932a61893b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -444,10 +444,6 @@ &gcc { ; }; -&gmu { - status = "okay"; -}; - &gpi_dma0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index aa482e8fd9e2..cd5172ad2490 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -414,10 +414,6 @@ &gcc { ; }; -&gmu { - status = "okay"; -}; - &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 46e25c53829a..8a0f154bffc3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -345,10 +345,6 @@ &gcc { ; }; -&gmu { - status = "okay"; -}; - &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index ddb82ecb0a92..e5da58d11064 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -419,10 +419,6 @@ &gcc { ; }; -&gmu { - status = "okay"; -}; - &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index b02a1dc5fecd..a3a304e1ac87 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -415,10 +415,6 @@ &gcc { ; }; -&gmu { - status = "okay"; -}; - &gpi_dma0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 617b17b2d7d9..f790eb73abdd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -239,10 +239,6 @@ &gcc { ; }; -&gmu { - status = "okay"; -}; - &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index e386b504e978..501575c9beda 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -381,10 +381,6 @@ &gcc { ; }; -&gmu { - status = "okay"; -}; - &gpi_dma0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e0ce804bb1a3..dc939360f74c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4952,8 +4952,6 @@ gmu: gmu@506a000 { operating-points-v2 = <&gmu_opp_table>; - status = "disabled"; - gmu_opp_table: opp-table { compatible = "operating-points-v2"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index bf45511b24b3..e8012205954e 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -355,10 +355,6 @@ &gcc { ; }; -&gmu { - status = "okay"; -}; - &gpu { status = "okay"; zap-shader { From 2d3dd4b237638853b8a99353401ab8d88a6afb6c Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Tue, 25 Feb 2025 19:38:53 +0300 Subject: [PATCH 095/308] arm64: dts: qcom: sdm845-starqltechn: remove wifi Starqltechn has broadcom chip for wifi, so sdm845 wifi part can be disabled. Fixes: d711b22eee55 ("arm64: dts: qcom: starqltechn: add initial device tree for starqltechn") Reviewed-by: Konrad Dybcio Signed-off-by: Dzmitry Sankouski Fixes: d711b22eee55 ("arm64: dts: qcom: starqltechn: add initial device tree for starqltechn") Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250225-starqltechn_integration_upstream-v9-2-a5d80375cb66@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index d37a433130b9..6fc30fd1262b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -418,14 +418,6 @@ &usb_1_qmpphy { status = "okay"; }; -&wifi { - vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; - status = "okay"; -}; - &tlmm { gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>; From 242e4126ee007b95765c21a9d74651fdcf221f2b Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Tue, 25 Feb 2025 19:38:54 +0300 Subject: [PATCH 096/308] arm64: dts: qcom: sdm845-starqltechn: fix usb regulator mistake Usb regulator was wrongly pointed to vreg_l1a_0p875. However, on starqltechn it's powered from vreg_l5a_0p8. Fixes: d711b22eee55 ("arm64: dts: qcom: starqltechn: add initial device tree for starqltechn") Reviewed-by: Konrad Dybcio Signed-off-by: Dzmitry Sankouski Link: https://lore.kernel.org/r/20250225-starqltechn_integration_upstream-v9-3-a5d80375cb66@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 6fc30fd1262b..f3f2b25883d8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -135,8 +135,6 @@ vdda_pll_cc_ebi23: vdda_sp_sensor: vdda_ufs1_core: vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: vreg_l1a_0p875: ldo1 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; @@ -157,6 +155,7 @@ vreg_l3a_1p0: ldo3 { regulator-initial-mode = ; }; + vdda_usb1_ss_core: vdd_wcss_cx: vdd_wcss_mx: vdda_wcss_pll: From cba1dd3d851ebc1b6c5ae4000208a9753320694b Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Tue, 25 Feb 2025 19:38:55 +0300 Subject: [PATCH 097/308] arm64: dts: qcom: sdm845-starqltechn: refactor node order Fixes: d711b22eee55 ("arm64: dts: qcom: starqltechn: add initial device tree for starqltechn") Signed-off-by: Dzmitry Sankouski Link: https://lore.kernel.org/r/20250225-starqltechn_integration_upstream-v9-4-a5d80375cb66@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index f3f2b25883d8..8a0d63bd594b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -382,8 +382,8 @@ &ufs_mem_phy { }; &sdhc_2 { - pinctrl-names = "default"; pinctrl-0 = <&sdc2_clk_state &sdc2_cmd_state &sdc2_data_state &sd_card_det_n_state>; + pinctrl-names = "default"; cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; vmmc-supply = <&vreg_l21a_2p95>; vqmmc-supply = <&vddpx_2>; From fb5fce873b952f8b1c5f7edcabcc8611ef45ea7a Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Tue, 25 Feb 2025 19:38:56 +0300 Subject: [PATCH 098/308] arm64: dts: qcom: sdm845-starqltechn: remove excess reserved gpios Starqltechn has 2 reserved gpio ranges <27 4>, <85 4>. <27 4> is spi for eSE(embedded Secure Element). <85 4> is spi for fingerprint. Remove excess reserved gpio regions. Fixes: d711b22eee55 ("arm64: dts: qcom: starqltechn: add initial device tree for starqltechn") Reviewed-by: Konrad Dybcio Signed-off-by: Dzmitry Sankouski Link: https://lore.kernel.org/r/20250225-starqltechn_integration_upstream-v9-5-a5d80375cb66@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 8a0d63bd594b..5948b401165c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -418,7 +418,8 @@ &usb_1_qmpphy { }; &tlmm { - gpio-reserved-ranges = <0 4>, <27 4>, <81 4>, <85 4>; + gpio-reserved-ranges = <27 4>, /* SPI (eSE - embedded Secure Element) */ + <85 4>; /* SPI (fingerprint reader) */ sdc2_clk_state: sdc2-clk-state { pins = "sdc2_clk"; From b58e67cd607e43b56f7cd509bdef0577d4658f10 Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Tue, 25 Feb 2025 19:38:57 +0300 Subject: [PATCH 099/308] arm64: dts: qcom: sdm845-starqltechn: add gpio keys Add support for phone buttons. Reviewed-by: Konrad Dybcio Signed-off-by: Dzmitry Sankouski Link: https://lore.kernel.org/r/20250225-starqltechn_integration_upstream-v9-6-a5d80375cb66@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-samsung-starqltechn.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 5948b401165c..38c09e50ccfb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -7,9 +7,11 @@ /dts-v1/; +#include #include #include #include "sdm845.dtsi" +#include "pm8998.dtsi" / { chassis-type = "handset"; @@ -69,6 +71,25 @@ memory@a1300000 { pmsg-size = <0x40000>; }; }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-vol-up { + label = "Volume Up"; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-wink { + label = "Bixby"; + gpios = <&pm8998_gpios 19 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; }; @@ -417,6 +438,11 @@ &usb_1_qmpphy { status = "okay"; }; +&pm8998_resin { + linux,code = ; + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <27 4>, /* SPI (eSE - embedded Secure Element) */ <85 4>; /* SPI (fingerprint reader) */ From 7a88a931d09564b3ae84e7abd5cd412af1dd5280 Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Tue, 25 Feb 2025 19:38:58 +0300 Subject: [PATCH 100/308] arm64: dts: qcom: sdm845-starqltechn: add max77705 PMIC Add support for max77705 MFD device. Supported sub-devices: charger, fuelgauge, haptic, led Reviewed-by: Konrad Dybcio Signed-off-by: Dzmitry Sankouski Link: https://lore.kernel.org/r/20250225-starqltechn_integration_upstream-v9-7-a5d80375cb66@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-samsung-starqltechn.dts | 130 ++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 38c09e50ccfb..bd5c8b319ddf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -9,6 +9,7 @@ #include #include +#include #include #include "sdm845.dtsi" #include "pm8998.dtsi" @@ -18,6 +19,16 @@ / { model = "Samsung Galaxy S9 SM-G9600"; compatible = "samsung,starqltechn", "qcom,sdm845"; + battery: battery { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <2150000>; + charge-full-design-microamp-hours = <3000000>; + + over-voltage-threshold-microvolt = <4500000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4350000>; + }; + chosen { #address-cells = <2>; #size-cells = <2>; @@ -32,6 +43,19 @@ framebuffer: framebuffer@9d400000 { }; }; + vib_regulator: gpio-regulator { + compatible = "regulator-fixed"; + + regulator-name = "haptic"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8998_gpios 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-boot-on; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -90,6 +114,17 @@ key-wink { debounce-interval = <15>; }; }; + + vib_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + assigned-clock-parents = <&rpmhcc RPMH_CXO_CLK>; + assigned-clocks = <&gcc GCC_GP1_CLK_SRC>; + clocks = <&gcc GCC_GP1_CLK>; + pinctrl-0 = <&motor_pwm_default_state>; + pinctrl-1 = <&motor_pwm_suspend_state>; + pinctrl-names = "default", "suspend"; + }; }; @@ -385,10 +420,79 @@ &qupv3_id_1 { status = "okay"; }; +&gpi_dma1 { + status = "okay"; +}; + &uart9 { status = "okay"; }; +&i2c14 { + status = "okay"; + + pmic@66 { + compatible = "maxim,max77705"; + reg = <0x66>; + interrupt-parent = <&pm8998_gpios>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_int_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + leds { + compatible = "maxim,max77705-rgb"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; + }; + + haptic { + compatible = "maxim,max77705-haptic"; + haptic-supply = <&vib_regulator>; + pwms = <&vib_pwm 0 52084>; + }; + }; + + max77705_charger: charger@69 { + reg = <0x69>; + compatible = "maxim,max77705-charger"; + monitored-battery = <&battery>; + interrupt-parent = <&pm8998_gpios>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + }; + + fuel-gauge@36 { + reg = <0x36>; + compatible = "maxim,max77705-battery"; + power-supplies = <&max77705_charger>; + maxim,rsns-microohm = <5000>; + interrupt-parent = <&pm8998_gpios>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; vcc-supply = <&vreg_l20a_2p95>; @@ -443,10 +547,36 @@ &pm8998_resin { status = "okay"; }; +&pm8998_gpios { + pmic_int_default: pmic-int-default-state { + pins = "gpio11"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + }; +}; + &tlmm { gpio-reserved-ranges = <27 4>, /* SPI (eSE - embedded Secure Element) */ <85 4>; /* SPI (fingerprint reader) */ + motor_pwm_default_state: motor-pwm-active-state { + pins = "gpio57"; + function = "gcc_gp1"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + motor_pwm_suspend_state: motor-pwm-suspend-state { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + sdc2_clk_state: sdc2-clk-state { pins = "sdc2_clk"; bias-disable; From 3a4600448befafe598f30d7e30aa89cef8226519 Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Tue, 25 Feb 2025 19:38:59 +0300 Subject: [PATCH 101/308] arm64: dts: qcom: sdm845-starqltechn: add display PMIC Add support for s2dos05 display / touchscreen PMIC Reviewed-by: Konrad Dybcio Signed-off-by: Dzmitry Sankouski Link: https://lore.kernel.org/r/20250225-starqltechn_integration_upstream-v9-8-a5d80375cb66@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-samsung-starqltechn.dts | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index bd5c8b319ddf..77abfadb4cc5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -40,6 +40,9 @@ framebuffer: framebuffer@9d400000 { height = <2960>; stride = <(1440 * 4)>; format = "a8r8g8b8"; + vci-supply = <&s2dos05_ldo4>; + vddr-supply = <&s2dos05_buck>; + vdd3-supply = <&s2dos05_ldo1>; }; }; @@ -96,6 +99,66 @@ memory@a1300000 { }; }; + i2c21 { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; + scl-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <2>; + pinctrl-0 = <&i2c21_sda_state &i2c21_scl_state>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + pmic@60 { + compatible = "samsung,s2dos05"; + reg = <0x60>; + + regulators { + s2dos05_ldo1: ldo1 { + regulator-active-discharge = <1>; + regulator-enable-ramp-delay = <12000>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2000000>; + regulator-name = "ldo1"; + }; + + s2dos05_ldo2: ldo2 { + regulator-active-discharge = <1>; + regulator-boot-on; + regulator-enable-ramp-delay = <12000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "ldo2"; + }; + + s2dos05_ldo3: ldo3 { + regulator-active-discharge = <1>; + regulator-boot-on; + regulator-enable-ramp-delay = <12000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "ldo3"; + }; + + s2dos05_ldo4: ldo4 { + regulator-active-discharge = <1>; + regulator-enable-ramp-delay = <12000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3775000>; + regulator-name = "ldo4"; + }; + + s2dos05_buck: buck { + regulator-active-discharge = <1>; + regulator-enable-ramp-delay = <12000>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <2100000>; + regulator-name = "buck"; + }; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -561,6 +624,20 @@ &tlmm { gpio-reserved-ranges = <27 4>, /* SPI (eSE - embedded Secure Element) */ <85 4>; /* SPI (fingerprint reader) */ + i2c21_sda_state: i2c21-sda-state { + pins = "gpio127"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c21_scl_state: i2c21-scl-state { + pins = "gpio128"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + motor_pwm_default_state: motor-pwm-active-state { pins = "gpio57"; function = "gcc_gp1"; From 801733b4757ccef4dfce046639cf3ddeae7253b1 Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Tue, 25 Feb 2025 19:39:00 +0300 Subject: [PATCH 102/308] arm64: dts: qcom: sdm845-starqltechn: add touchscreen support Add support for samsung,s6sy761 touchscreen. Reviewed-by: Konrad Dybcio Signed-off-by: Dzmitry Sankouski Link: https://lore.kernel.org/r/20250225-starqltechn_integration_upstream-v9-9-a5d80375cb66@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-samsung-starqltechn.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 77abfadb4cc5..320add4697bf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -578,6 +578,23 @@ &sdhc_2 { status = "okay"; }; +&i2c11 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; + vdd-supply = <&s2dos05_ldo2>; + avdd-supply = <&s2dos05_ldo3>; + + pinctrl-0 = <&touch_irq_state>; + pinctrl-names = "default"; + }; +}; + &usb_1 { status = "okay"; }; @@ -682,4 +699,15 @@ sd_card_det_n_state: sd-card-det-n-state { function = "gpio"; bias-pull-up; }; + + touch_irq_state: touch-irq-state { + pins = "gpio120"; + function = "gpio"; + bias-disable; + }; +}; + +&qup_i2c11_default { + drive-strength = <2>; + bias-disable; }; From dd5c8d7222fbccd7d0accb7523e11657b827cc99 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Jan 2025 13:05:30 +0100 Subject: [PATCH 103/308] arm64: dts: qcom: Use recommended MBN firmware path All Qualcomm firmwares uploaded to linux-firmware are in MBN format, instead of split MDT. Firmware for boards here is not yet in linux-firmware, but if it gets accepted it will be MBN, not MDT. Change might affect users of DTS which rely on manually placed firmware files, not coming from linux-firmware package. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250108120530.156928-1-krzysztof.kozlowski@linaro.org [bjorn: Updated subject] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 4 ++-- .../arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 2 +- .../boot/dts/qcom/sm8150-microsoft-surface-duo.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 12 ++++++------ 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 9e9c7f81096b..4dfd66076629 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -383,12 +383,12 @@ &qupv3_id_1 { &remoteproc_adsp { status = "okay"; - firmware-name = "qcom/sa8155p/adsp.mdt"; + firmware-name = "qcom/sa8155p/adsp.mbn"; }; &remoteproc_cdsp { status = "okay"; - firmware-name = "qcom/sa8155p/cdsp.mdt"; + firmware-name = "qcom/sa8155p/cdsp.mbn"; }; &sdhc_2 { diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index a4b722e0fc1e..40522e237eac 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -157,7 +157,7 @@ extcon_usb: extcon-usb { }; &adsp_pil { - firmware-name = "qcom/sdm630/Sony/nile/adsp.mdt"; + firmware-name = "qcom/sdm630/Sony/nile/adsp.mbn"; }; &blsp_i2c1 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index 9a3d0ac6c423..835ef929ff2d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -453,22 +453,22 @@ &qupv3_id_2 { &remoteproc_adsp { status = "okay"; - firmware-name = "qcom/sm8150/microsoft/adsp.mdt"; + firmware-name = "qcom/sm8150/microsoft/adsp.mbn"; }; &remoteproc_cdsp { status = "okay"; - firmware-name = "qcom/sm8150/microsoft/cdsp.mdt"; + firmware-name = "qcom/sm8150/microsoft/cdsp.mbn"; }; &remoteproc_mpss { status = "okay"; - firmware-name = "qcom/sm8150/microsoft/modem.mdt"; + firmware-name = "qcom/sm8150/microsoft/modem.mbn"; }; &remoteproc_slpi { status = "okay"; - firmware-name = "qcom/sm8150/microsoft/slpi.mdt"; + firmware-name = "qcom/sm8150/microsoft/slpi.mbn"; }; &pon_resin { diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 2e1c7afe0aa7..12e8e1ada6d8 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -379,22 +379,22 @@ &qupv3_id_1 { &remoteproc_adsp { status = "okay"; - firmware-name = "qcom/sm8150/adsp.mdt"; + firmware-name = "qcom/sm8150/adsp.mbn"; }; &remoteproc_cdsp { status = "okay"; - firmware-name = "qcom/sm8150/cdsp.mdt"; + firmware-name = "qcom/sm8150/cdsp.mbn"; }; &remoteproc_mpss { status = "okay"; - firmware-name = "qcom/sm8150/modem.mdt"; + firmware-name = "qcom/sm8150/modem.mbn"; }; &remoteproc_slpi { status = "okay"; - firmware-name = "qcom/sm8150/slpi.mdt"; + firmware-name = "qcom/sm8150/slpi.mbn"; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index e8383faac576..7d29a57a2b54 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -547,20 +547,20 @@ &qupv3_id_0 { }; &remoteproc_adsp { - firmware-name = "qcom/sm8550/adsp.mdt", - "qcom/sm8550/adsp_dtb.mdt"; + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; status = "okay"; }; &remoteproc_cdsp { - firmware-name = "qcom/sm8550/cdsp.mdt", - "qcom/sm8550/cdsp_dtb.mdt"; + firmware-name = "qcom/sm8550/cdsp.mbn", + "qcom/sm8550/cdsp_dtb.mbn"; status = "okay"; }; &remoteproc_mpss { - firmware-name = "qcom/sm8550/modem.mdt", - "qcom/sm8550/modem_dtb.mdt"; + firmware-name = "qcom/sm8550/modem.mbn", + "qcom/sm8550/modem_dtb.mbn"; status = "okay"; }; From eeb0f3e4ea67cb1c2dd7cacfef218bfa0ae56970 Mon Sep 17 00:00:00 2001 From: Gaurav Kashyap Date: Mon, 13 Jan 2025 13:16:22 -0800 Subject: [PATCH 104/308] arm64: dts: qcom: sm8750: Add QCrypto nodes Add the QCE and Crypto BAM DMA nodes. Signed-off-by: Gaurav Kashyap Signed-off-by: Melody Olvera Link: https://lore.kernel.org/r/20250113-sm8750_crypto_master-v1-2-d8e265729848@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 529e4e4e1d0e..c4215c05e8a1 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -1939,6 +1939,36 @@ mmss_noc: interconnect@1780000 { #interconnect-cells = <2>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + + interrupts = ; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8750-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From 9f9dcac2f85e6a0641a4a4f7f3b2c35a984ed4cc Mon Sep 17 00:00:00 2001 From: Gaurav Kashyap Date: Mon, 13 Jan 2025 13:16:24 -0800 Subject: [PATCH 105/308] arm64: dts: qcom: sm8750: Add TRNG nodes Add the SM8750 nodes for the True Random Number Generator (TRNG). Signed-off-by: Gaurav Kashyap Signed-off-by: Melody Olvera Link: https://lore.kernel.org/r/20250113-sm8750_crypto_master-v1-4-d8e265729848@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index c4215c05e8a1..844325d871b8 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -1883,6 +1883,11 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, }; }; + rng: rng@10c3000 { + compatible = "qcom,sm8750-trng", "qcom,trng"; + reg = <0x0 0x010c3000 0x0 0x1000>; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,sm8750-cnoc-main"; reg = <0x0 0x01500000 0x0 0x16080>; From b1dac789c650a20a54d5089b23fbb800fb289b8b Mon Sep 17 00:00:00 2001 From: Gaurav Kashyap Date: Mon, 13 Jan 2025 13:16:26 -0800 Subject: [PATCH 106/308] arm64: dts: qcom: sm8750: Add ICE nodes Add the SM8750 nodes for the UFS Inline Crypto Engine (ICE). Signed-off-by: Gaurav Kashyap Signed-off-by: Melody Olvera Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250113-sm8750_crypto_master-v1-6-d8e265729848@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 844325d871b8..a01ce74eebb3 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -1944,6 +1944,14 @@ mmss_noc: interconnect@1780000 { #interconnect-cells = <2>; }; + ice: crypto@1d88000 { + compatible = "qcom,sm8750-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; From 1f552db1b953b737183fd7c11c4814d3d152d4cd Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 4 Mar 2025 17:04:00 +0530 Subject: [PATCH 107/308] arm64: dts: qcom: ipq5424: Enable MMC Enable MMC and relevant pinctrl entries. Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20250304113400.2806670-1-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 7 +++++++ arch/arm64/boot/dts/qcom/ipq5424.dtsi | 2 ++ 2 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index b6e4bb3328b3..b9752e8d579e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -69,6 +69,13 @@ &qusb_phy_1 { status = "okay"; }; +&sdhc { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + &sleep_clk { clock-frequency = <32000>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 7a7ad700a382..402d0a2c7bcc 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -352,6 +352,8 @@ sdhc: mmc@7804000 { <&xo_board>; clock-names = "iface", "core", "xo"; + supports-cqe; + status = "disabled"; }; From 8744dd90cd6b8ee105f5ade1ca9649451aff416a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Mar 2025 13:44:45 +0100 Subject: [PATCH 108/308] arm64: dts: qcom: sm8750: Add IPCC, SMP2P, AOSS and ADSP Add nodes for IPCC mailbox, SMP2P for ADSP, AOSS and the ADSP remoteproc PAS loader (compatible with SM8550). Reviewed-by: Melody Olvera Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250312-sm8750-audio-v3-1-40fbb3e53f95@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 140 +++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index a01ce74eebb3..f75f0723e393 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -10,8 +10,10 @@ #include #include #include +#include #include #include +#include #include / { @@ -516,6 +518,32 @@ llcc_lpi_mem: llcc-lpi@ff800000 { }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -542,6 +570,17 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + ipcc: mailbox@406000 { + compatible = "qcom,sm8750-ipcc", "qcom,ipcc"; + reg = <0x0 0x00406000 0x0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0x00800000 0x0 0x60000>; @@ -1988,6 +2027,94 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + remoteproc_adsp: remoteproc@6800000 { + compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas"; + reg = <0x0 0x06800000 0x0 0x10000>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <2>; + label = "lpass"; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1041 0x20>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,sm8750-lpass-ag-noc"; reg = <0x0 0x07e40000 0x0 0xe080>; @@ -2021,6 +2148,19 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + aoss_qmp: power-management@c300000 { + compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + sram@c3f0000 { compatible = "qcom,rpmh-stats"; reg = <0x0 0x0c3f0000 0x0 0x400>; From 0fe088574b30588e5fc437be376383b1372da49a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Mar 2025 13:44:46 +0100 Subject: [PATCH 109/308] arm64: dts: qcom: sm8750: Add LPASS macro codecs and pinctrl Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm SM8750 for proper sound support. These are fully compatible with earlier SM8550. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250312-sm8750-audio-v3-2-40fbb3e53f95@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 202 +++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index f75f0723e393..e4670fefff7c 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -2115,6 +2116,74 @@ q6prmcc: clock-controller { }; }; + lpass_wsa2macro: codec@6aa0000 { + compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06aa0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "wsa2-mclk"; + #sound-dai-cells = <1>; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible = "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; + reg = <0x0 0x06ac0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + lpass_txmacro: codec@6ae0000 { + compatible = "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; + reg = <0x0 0x06ae0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06b00000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,sm8750-lpass-ag-noc"; reg = <0x0 0x07e40000 0x0 0xe080>; @@ -2136,6 +2205,139 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells = <2>; }; + lpass_vamacro: codec@7660000 { + compatible = "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; + reg = <0x0 0x07660000 0x0 0x2000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible = "qcom,sm8750-lpass-lpi-pinctrl", + "qcom,sm8650-lpass-lpi-pinctrl"; + reg = <0x0 0x07760000 0x0 0x20000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; From 0c23fa8648871e6e74cb93ab7089c50f9bc20857 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Mar 2025 13:44:47 +0100 Subject: [PATCH 110/308] arm64: dts: qcom: sm8750-mtp: Enable ADSP Enable ADSP on MTP8750 board. Reviewed-by: Melody Olvera Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250312-sm8750-audio-v3-3-40fbb3e53f95@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 9e3aacad7bda..8eeed7f2f776 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -784,6 +784,13 @@ &qupv3_1 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/sm8750/adsp.mbn", + "qcom/sm8750/adsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { /* reserved for secure world */ gpio-reserved-ranges = <36 4>, <74 1>; From 23d8b031f302a43408cf43002b6cb13e88e99a10 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Mar 2025 13:44:48 +0100 Subject: [PATCH 111/308] arm64: dts: qcom: sm8750-qrd: Enable ADSP Enable ADSP on QRD8750 board. Reviewed-by: Melody Olvera Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250312-sm8750-audio-v3-4-40fbb3e53f95@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts index f77efab0aef9..341774bb042f 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -782,6 +782,13 @@ &qupv3_1 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/sm8750/adsp.mbn", + "qcom/sm8750/adsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { /* reserved for secure world */ gpio-reserved-ranges = <36 4>, <74 1>; From 58471055ae76f639ba8cc2df3e1bc12fa4be2c02 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Mar 2025 14:13:57 +0100 Subject: [PATCH 112/308] arm64: dts: qcom: sm8750: Add CDSP Add nodes for the CDSP and its SMP2P. These are compatible with earlier SM8650 with difference in one more interrupt. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250312-b4-sm8750-cdsp-v4-1-4925d607cea6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 194 +++++++++++++++++++++++++++ 1 file changed, 194 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index e4670fefff7c..798e1cf0bc96 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -545,6 +545,32 @@ smp2p_adsp_in: slave-kernel { }; }; + smp2p-cdsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -3284,6 +3310,174 @@ nsp_noc: interconnect@320c0000 { qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,sm8750-cdsp-pas", "qcom,sm8650-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x19c1 0x0>, + <&apps_smmu 0x0c21 0x0>, + <&apps_smmu 0x0c01 0x40>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x0c02 0x20>, + <&apps_smmu 0x0c42 0x0>, + <&apps_smmu 0x19c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x0c23 0x0>, + <&apps_smmu 0x0c03 0x40>, + <&apps_smmu 0x19c3 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x0c24 0x0>, + <&apps_smmu 0x0c04 0x40>, + <&apps_smmu 0x19c4 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x0c25 0x0>, + <&apps_smmu 0x0c05 0x40>, + <&apps_smmu 0x19c5 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x0c06 0x20>, + <&apps_smmu 0x0c46 0x0>, + <&apps_smmu 0x19c6 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x0c27 0x0>, + <&apps_smmu 0x0c07 0x40>, + <&apps_smmu 0x19c7 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x0c08 0x20>, + <&apps_smmu 0x0c48 0x0>, + <&apps_smmu 0x19c8 0x0>; + dma-coherent; + }; + + /* note: secure cb9 in downstream */ + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x0c2c 0x20>, + <&apps_smmu 0x0c0c 0x40>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x0c0d 0x20>, + <&apps_smmu 0x0c2e 0x0>, + <&apps_smmu 0x0c4d 0x0>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + + compute-cb@14 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + iommus = <&apps_smmu 0x196e 0x0>, + <&apps_smmu 0x0c0e 0x20>, + <&apps_smmu 0x19ce 0x0>; + dma-coherent; + }; + }; + }; + }; }; timer { From 070b7e0490b521999b95c9262ab9e1609c8ab4a1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Mar 2025 14:13:58 +0100 Subject: [PATCH 113/308] arm64: dts: qcom: sm8750-mtp: Enable CDSP Enable the CDSP on MPT8750 board. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250312-b4-sm8750-cdsp-v4-2-4925d607cea6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 8eeed7f2f776..5d0decd2aa2d 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -791,6 +791,13 @@ &remoteproc_adsp { status = "okay"; }; +&remoteproc_cdsp { + firmware-name = "qcom/sm8750/cdsp.mbn", + "qcom/sm8750/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { /* reserved for secure world */ gpio-reserved-ranges = <36 4>, <74 1>; From 0bbdfaa204ce673570e41fe71d4f571a82c7b04d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Mar 2025 14:13:59 +0100 Subject: [PATCH 114/308] arm64: dts: qcom: sm8750-qrd: Enable CDSP Enable the CDSP on QRD8750 board. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250312-b4-sm8750-cdsp-v4-3-4925d607cea6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts index 341774bb042f..7f1d5d4e5b28 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -789,6 +789,13 @@ &remoteproc_adsp { status = "okay"; }; +&remoteproc_cdsp { + firmware-name = "qcom/sm8750/cdsp.mbn", + "qcom/sm8750/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { /* reserved for secure world */ gpio-reserved-ranges = <36 4>, <74 1>; From 75eefd474469abf95aa9ef6da8161d69f86b98b4 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 12 Feb 2025 18:03:47 +0100 Subject: [PATCH 115/308] arm64: dts: qcom: sm8350: Reenable crypto & cryptobam When num-channels and qcom,num-ees is not provided in devicetree, the driver will try to read these values from the registers during probe but this fails if the interconnect is not on and then crashes the system. So we can provide these properties in devicetree (queried after patching BAM driver to enable the necessary interconnect) so we can probe cryptobam without reading registers and then also use the QCE as expected. Fixes: 4d29db204361 ("arm64: dts: qcom: sm8350: fix BAM DMA crash and reboot") Fixes: f1040a7fe8f0 ("arm64: dts: qcom: sm8350: Add Crypto Engine support") Signed-off-by: Luca Weiss Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250212-bam-dma-fixes-v1-1-f560889e65d8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 69da30f35baa..5f93cae01b06 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1806,11 +1806,11 @@ cryptobam: dma-controller@1dc4000 { interrupts = ; #dma-cells = <1>; qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <16>; qcom,controlled-remotely; iommus = <&apps_smmu 0x594 0x0011>, <&apps_smmu 0x596 0x0011>; - /* FIXME: Probing BAM DMA causes some abort and system hang */ - status = "fail"; }; crypto: crypto@1dfa000 { @@ -1822,8 +1822,6 @@ crypto: crypto@1dfa000 { <&apps_smmu 0x596 0x0011>; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "memory"; - /* FIXME: dependency BAM DMA is disabled */ - status = "disabled"; }; ipa: ipa@1e40000 { From 0fe6357229cb15a64b6413c62f1c3d4de68ce55f Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 12 Feb 2025 18:03:48 +0100 Subject: [PATCH 116/308] arm64: dts: qcom: sm8450: Add missing properties for cryptobam num-channels and qcom,num-ees are required for BAM nodes without clock, because the driver cannot ensure the hardware is powered on when trying to obtain the information from the hardware registers. Specifying the node without these properties is unsafe and has caused early boot crashes for other SoCs before [1, 2]. Add the missing information from the hardware registers to ensure the driver can probe successfully without causing crashes. [1]: https://lore.kernel.org/r/CY01EKQVWE36.B9X5TDXAREPF@fairphone.com/ [2]: https://lore.kernel.org/r/20230626145959.646747-1-krzysztof.kozlowski@linaro.org/ Cc: stable@vger.kernel.org Fixes: b92b0d2f7582 ("arm64: dts: qcom: sm8450: add crypto nodes") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250212-bam-dma-fixes-v1-2-f560889e65d8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9c809fc5fa45..419df72cd04b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5283,6 +5283,8 @@ cryptobam: dma-controller@1dc4000 { interrupts = ; #dma-cells = <1>; qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <16>; qcom,controlled-remotely; iommus = <&apps_smmu 0x584 0x11>, <&apps_smmu 0x588 0x0>, From 663cd2cad36da23cf1a3db7868fce9f1a19b2d61 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 12 Feb 2025 18:03:49 +0100 Subject: [PATCH 117/308] arm64: dts: qcom: sm8550: Add missing properties for cryptobam num-channels and qcom,num-ees are required for BAM nodes without clock, because the driver cannot ensure the hardware is powered on when trying to obtain the information from the hardware registers. Specifying the node without these properties is unsafe and has caused early boot crashes for other SoCs before [1, 2]. Add the missing information from the hardware registers to ensure the driver can probe successfully without causing crashes. [1]: https://lore.kernel.org/r/CY01EKQVWE36.B9X5TDXAREPF@fairphone.com/ [2]: https://lore.kernel.org/r/20230626145959.646747-1-krzysztof.kozlowski@linaro.org/ Cc: stable@vger.kernel.org Fixes: 433477c3bf0b ("arm64: dts: qcom: sm8550: add QCrypto nodes") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250212-bam-dma-fixes-v1-3-f560889e65d8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 18bcb4ac6bd8..f78d5292c5dd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2282,6 +2282,8 @@ cryptobam: dma-controller@1dc4000 { interrupts = ; #dma-cells = <1>; qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; qcom,controlled-remotely; iommus = <&apps_smmu 0x480 0x0>, <&apps_smmu 0x481 0x0>; From 38b88722bce07b6a5927f45fbf7a9a85e834572c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 12 Feb 2025 18:03:50 +0100 Subject: [PATCH 118/308] arm64: dts: qcom: sm8650: Add missing properties for cryptobam num-channels and qcom,num-ees are required for BAM nodes without clock, because the driver cannot ensure the hardware is powered on when trying to obtain the information from the hardware registers. Specifying the node without these properties is unsafe and has caused early boot crashes for other SoCs before [1, 2]. Add the missing information from the hardware registers to ensure the driver can probe successfully without causing crashes. [1]: https://lore.kernel.org/r/CY01EKQVWE36.B9X5TDXAREPF@fairphone.com/ [2]: https://lore.kernel.org/r/20230626145959.646747-1-krzysztof.kozlowski@linaro.org/ Cc: stable@vger.kernel.org Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250212-bam-dma-fixes-v1-4-f560889e65d8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index d5037cc306c2..8c551e2f58c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3930,6 +3930,8 @@ cryptobam: dma-controller@1dc4000 { <&apps_smmu 0x481 0>; qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; qcom,controlled-remotely; }; From a2517331f11bd22cded60e791a8818cec3e7597a Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 12 Feb 2025 18:03:51 +0100 Subject: [PATCH 119/308] arm64: dts: qcom: sa8775p: Add missing properties for cryptobam num-channels and qcom,num-ees are required for BAM nodes without clock, because the driver cannot ensure the hardware is powered on when trying to obtain the information from the hardware registers. Specifying the node without these properties is unsafe and has caused early boot crashes for other SoCs before [1, 2]. Add the missing information from the hardware registers to ensure the driver can probe successfully without causing crashes. [1]: https://lore.kernel.org/r/CY01EKQVWE36.B9X5TDXAREPF@fairphone.com/ [2]: https://lore.kernel.org/r/20230626145959.646747-1-krzysztof.kozlowski@linaro.org/ Cc: stable@vger.kernel.org Fixes: 7ff3da43ef44 ("arm64: dts: qcom: sa8775p: add QCrypto nodes") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250212-bam-dma-fixes-v1-5-f560889e65d8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23049cc58896..6a2c49047df5 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2413,6 +2413,8 @@ cryptobam: dma-controller@1dc4000 { interrupts = ; #dma-cells = <1>; qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; qcom,controlled-remotely; iommus = <&apps_smmu 0x480 0x00>, <&apps_smmu 0x481 0x00>; From b4cd966edb2deb5c75fe356191422e127445b830 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 12 Feb 2025 18:03:52 +0100 Subject: [PATCH 120/308] arm64: dts: qcom: ipq9574: Add missing properties for cryptobam num-channels and qcom,num-ees are required for BAM nodes without clock, because the driver cannot ensure the hardware is powered on when trying to obtain the information from the hardware registers. Specifying the node without these properties is unsafe and has caused early boot crashes for other SoCs before [1, 2]. Add the missing information from the hardware registers to ensure the driver can probe successfully without causing crashes. [1]: https://lore.kernel.org/r/CY01EKQVWE36.B9X5TDXAREPF@fairphone.com/ [2]: https://lore.kernel.org/r/20230626145959.646747-1-krzysztof.kozlowski@linaro.org/ Cc: stable@vger.kernel.org Tested-by: Md Sadre Alam Fixes: ffadc79ed99f ("arm64: dts: qcom: ipq9574: Enable crypto nodes") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250212-bam-dma-fixes-v1-6-f560889e65d8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index cac58352182e..04bfe1f3fa7a 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -378,6 +378,8 @@ cryptobam: dma-controller@704000 { interrupts = ; #dma-cells = <1>; qcom,ee = <1>; + qcom,num-ees = <4>; + num-channels = <16>; qcom,controlled-remotely; }; From c87d58bc7f831bf3d887e6ec846246cb673c2e50 Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Thu, 13 Mar 2025 12:44:22 +0530 Subject: [PATCH 121/308] arm64: dts: qcom: ipq9574: fix the msi interrupt numbers of pcie3 The MSI interrupt numbers of the PCIe3 controller are incorrect. Due to this, the functional bring up of the QDSP6 processor on the PCIe endpoint has failed. Correct the MSI interrupt numbers to properly bring up the QDSP6 processor on the PCIe endpoint. Fixes: d80c7fbfa908 ("arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes") Signed-off-by: Manikanta Mylavarapu Link: https://lore.kernel.org/r/20250313071422.510-1-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 04bfe1f3fa7a..4c5b8ca4812c 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -974,14 +974,14 @@ pcie3: pcie@18000000 { ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "msi0", "msi1", "msi2", From b18c1aa6404303888ab924f149135835d223f4e8 Mon Sep 17 00:00:00 2001 From: Daniil Titov Date: Thu, 13 Feb 2025 20:54:48 +0100 Subject: [PATCH 122/308] arm64: dts: qcom: pm8937: Add LPG PWM driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add PWM/LPG node to the PM8937 dtsi so devices which use this block can enable them. Signed-off-by: Daniil Titov Signed-off-by: Barnabás Czémán Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250213-pm8937-pwm-v2-2-49ea59801a33@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8937.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8937.dtsi b/arch/arm64/boot/dts/qcom/pm8937.dtsi index 42b3575b36ff..77809c3534a7 100644 --- a/arch/arm64/boot/dts/qcom/pm8937.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8937.dtsi @@ -143,6 +143,14 @@ pmic@1 { #address-cells = <1>; #size-cells = <0>; + pm8937_pwm: pwm { + compatible = "qcom,pm8937-pwm", "qcom,pm8916-pwm"; + + #pwm-cells = <2>; + + status = "disabled"; + }; + pm8937_spmi_regulators: regulators { compatible = "qcom,pm8937-regulators"; }; From 5b74065e6c2482507435cdf7c4d0aab1830b9676 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Thu, 13 Feb 2025 20:54:49 +0100 Subject: [PATCH 123/308] arm64: dts: qcom: msm8917-xiaomi-riva: Add display backlight MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Redmi 5A display uses pwm backlight, add support for it. Signed-off-by: Barnabás Czémán Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250213-pm8937-pwm-v2-3-49ea59801a33@mainlining.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8917-xiaomi-riva.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts index df135f9891a8..9db503e21888 100644 --- a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts +++ b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts @@ -20,6 +20,14 @@ / { qcom,msm-id = ; qcom,board-id = <0x1000b 2>, <0x2000b 2>; + pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pm8937_pwm 0 100000>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <128>; + }; + battery: battery { compatible = "simple-battery"; charge-full-design-microamp-hours = <3000000>; @@ -131,6 +139,23 @@ bq25601@6b { }; }; +&pm8937_gpios { + pwm_enable_default: pwm-enable-default-state { + pins = "gpio8"; + function = "dtest2"; + output-low; + bias-disable; + qcom,drive-strength = <2>; + }; +}; + +&pm8937_pwm { + pinctrl-0 = <&pwm_enable_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + &pm8937_resin { linux,code = ; From 5ee449c75f49c9a6b0cbff7848f922183e7888c1 Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Thu, 13 Feb 2025 22:28:39 -0800 Subject: [PATCH 124/308] ARM: dts: qcom: msm8960: Add BAM Copy bam nodes from qcom-ipq8064.dtsi and change the reg values to match msm8960. Co-developed-by: Sam Day Signed-off-by: Sam Day Reviewed-by: Dmitry Baryshkov Signed-off-by: Rudraksha Gupta Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250213-expressatt-bam-v3-1-0ff338f488b2@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 28 ++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 865fe7cc3951..1a98a4a9a586 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -279,7 +279,7 @@ sdcc3: mmc@12180000 { compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; status = "disabled"; - reg = <0x12180000 0x8000>; + reg = <0x12180000 0x2000>; interrupts = ; clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; clock-names = "mclk", "apb_pclk"; @@ -289,13 +289,25 @@ sdcc3: mmc@12180000 { max-frequency = <192000000>; no-1-8-v; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x4000>; + interrupts = ; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; }; sdcc1: mmc@12400000 { status = "disabled"; compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; + reg = <0x12400000 0x2000>; interrupts = ; clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names = "mclk", "apb_pclk"; @@ -305,6 +317,18 @@ sdcc1: mmc@12400000 { cap-sd-highspeed; cap-mmc-highspeed; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x4000>; + interrupts = ; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; }; tcsr: syscon@1a400000 { From df52f9ab185e91886c8fb0660a0768d29b4cc379 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 18 Feb 2025 12:51:57 +0000 Subject: [PATCH 125/308] arm64: dts: qcom: Drop `tx-sched-sp` property The `tx-sched-sp` property was removed in commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition branch"). Therefore, it can be safely removed from the device tree. Signed-off-by: Lad Prabhakar Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250218125157.412701-1-prabhakar.csengg@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 1 - arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 2 -- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 2 -- 3 files changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 916d4e6da922..2835b81d86ff 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -258,7 +258,6 @@ queue3 { mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <4>; - snps,tx-sched-sp; queue0 { snps,dcb-algorithm; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 177b9dad6ff7..11663cf81e45 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -225,7 +225,6 @@ queue3 { ethernet0_mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <1>; - snps,tx-sched-sp; queue0 { snps,dcb-algorithm; @@ -302,7 +301,6 @@ queue3 { ethernet1_mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <1>; - snps,tx-sched-sp; queue0 { snps,dcb-algorithm; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi index a14564054e94..967913169539 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -411,7 +411,6 @@ queue3 { mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <4>; - snps,tx-sched-sp; queue0 { snps,dcb-algorithm; @@ -480,7 +479,6 @@ queue3 { mtl_tx_setup1: tx-queues-config { snps,tx-queues-to-use = <4>; - snps,tx-sched-sp; queue0 { snps,dcb-algorithm; From 84247db00a5c4f9b6fbf23cc46979508ddd8d855 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 17:52:05 +0200 Subject: [PATCH 126/308] arm64: dts: qcom: sar2130p: add PCIe EP device nodes On the Qualcomm AR2 Gen1 platform the second PCIe host can be used either as an RC or as an EP device. Add device node for the PCIe EP. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20250221-sar2130p-pci-v3-7-61a0fdfb75b4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 61 ++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index dd832e6816be..b45e9e2ae035 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1474,6 +1474,67 @@ pcie@0 { }; }; + pcie1_ep: pcie-ep@1c08000 { + compatible = "qcom,sar2130p-pcie-ep"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40200000 0x0 0x1000000>, + <0x0 0x01c0b000 0x0 0x1000>, + <0x0 0x40002000 0x0 0x2000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio", + "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, + <&gcc GCC_QMIP_PCIE_AHB_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre_noc_axi", + "cnoc_sf_axi", + "qmip_pcie_ahb"; + + interrupts = , + , + ; + interrupt-names = "global", + "doorbell", + "dma"; + + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + iommus = <&apps_smmu 0x1e00 0x1>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + num-lanes = <2>; + + status = "disabled"; + }; + pcie1_phy: phy@1c0e000 { compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; reg = <0x0 0x01c0e000 0x0 0x2000>; From bffe01a9b4bbccd07a1fe2bd78c3795004b56645 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 21 Feb 2025 17:52:06 +0200 Subject: [PATCH 127/308] arm64: dts: qcom: sm8450: add PCIe EP device nodes On the Qualcomm SM8450 platform the second PCIe host can be used either as an RC or as an EP device. Add device node for the PCIe EP. Signed-off-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20250221-sar2130p-pci-v3-8-61a0fdfb75b4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 62 ++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 419df72cd04b..0b36f4cd4497 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2262,6 +2262,68 @@ pcie@0 { }; }; + pcie1_ep: pcie-ep@1c08000 { + compatible = "qcom,sm8450-pcie-ep"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40200000 0x0 0x1000000>, + <0x0 0x01c0b000 0x0 0x1000>, + <0x0 0x40002000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio", + "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "ddrss_sf_tbu", + "aggre_noc_axi"; + + interrupts = , + , + ; + interrupt-names = "global", + "doorbell", + "dma"; + + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + iommus = <&apps_smmu 0x1c80 0x7f>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + num-lanes = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "disabled"; + }; + pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; reg = <0 0x01c0e000 0 0x2000>; From 778dc0f876c70b3d781a49981560ec88e1b7083a Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Wed, 26 Feb 2025 12:21:27 +0530 Subject: [PATCH 128/308] arm64: dts: qcom: sm8750: Fix cluster hierarchy for idle states SM8750 have two different clusters. cluster0 have CPU 0-5 as child and cluster1 have CPU 6-7 as child. Each cluster requires its own idle state and power domain in order to achieve complete domain sleep state. However only single cluster idle state is added mapping CPU 0-7 to the same power domain. Fix this by correctly mapping each CPU to respective cluster power domain and make cluster1 power domain use same domain idle state as cluster0 since both use same idle state parameters. Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi") Signed-off-by: Maulik Shah Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250226-sm8750_cluster_idle-v2-1-ef0ac81e242f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 798e1cf0bc96..735e7628df96 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -236,53 +236,59 @@ psci { cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; - power-domains = <&cluster_pd>; + power-domains = <&cluster0_pd>; domain-idle-states = <&cluster0_c4>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; - power-domains = <&cluster_pd>; + power-domains = <&cluster0_pd>; domain-idle-states = <&cluster0_c4>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; - power-domains = <&cluster_pd>; + power-domains = <&cluster0_pd>; domain-idle-states = <&cluster0_c4>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; - power-domains = <&cluster_pd>; + power-domains = <&cluster0_pd>; domain-idle-states = <&cluster0_c4>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; - power-domains = <&cluster_pd>; + power-domains = <&cluster0_pd>; domain-idle-states = <&cluster0_c4>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; - power-domains = <&cluster_pd>; + power-domains = <&cluster0_pd>; domain-idle-states = <&cluster0_c4>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; - power-domains = <&cluster_pd>; + power-domains = <&cluster1_pd>; domain-idle-states = <&cluster1_c4>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; - power-domains = <&cluster_pd>; + power-domains = <&cluster1_pd>; domain-idle-states = <&cluster1_c4>; }; - cluster_pd: power-domain-cluster { + cluster0_pd: power-domain-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_cl5>; + power-domains = <&system_pd>; + }; + + cluster1_pd: power-domain-cluster1 { #power-domain-cells = <0>; domain-idle-states = <&cluster_cl5>; power-domains = <&system_pd>; From a3daa844ed8104617174bc1ac4554f8b88a9c878 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Fri, 28 Feb 2025 01:45:55 +0530 Subject: [PATCH 129/308] arm64: dts: qcom: qcs615: add TRNG node The qcs615 SoC has a True Random Number Generator, add the node with the correct compatible set. Signed-off-by: Abhinaba Rakshit Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250228-enable-trng-for-qcs615-v2-2-017aa858576e@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index ec427bb84ec8..f9398cf95003 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -459,6 +459,11 @@ qusb2_hstx_trim: hstx-trim@1f8 { }; }; + rng@793000 { + compatible = "qcom,qcs615-trng", "qcom,trng"; + reg = <0x0 0x00793000 0x0 0x1000>; + }; + sdhc_1: mmc@7c4000 { compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0 0x007c4000 0x0 0x1000>, From 4712dbd5fabdd5909b8b3367dfafd61f502b3bb7 Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Thu, 27 Feb 2025 17:16:55 -0800 Subject: [PATCH 130/308] ARM: dts: qcom: msm8960: Add thermal sensor (tsens) Add support for the thermal sensor (tsens) on the MSM8960 by copying and modifying the relevant nodes from the APQ8064 dtsi. These changes enable thermal management. Reviewed-by: Dmitry Baryshkov Signed-off-by: Rudraksha Gupta Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250227-expressatt-tsens-v4-2-d70afa5a1fd0@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 71 +++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 1a98a4a9a586..b476ad895119 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -52,6 +52,48 @@ memory@80000000 { reg = <0x80000000 0>; }; + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 0>; + + trips { + cpu_alert0: trip0 { + temperature = <60000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <10000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 1>; + + trips { + cpu_alert1: trip0 { + temperature = <60000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <95000>; + hysteresis = <10000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = ; @@ -115,6 +157,21 @@ timer@200a000 { cpu-offset = <0x80000>; }; + qfprom: efuse@700000 { + compatible = "qcom,msm8960-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_calib: calib@404 { + reg = <0x404 0x10>; + }; + + tsens_backup: backup-calib@414 { + reg = <0x414 0x10>; + }; + }; + msmgpio: pinctrl@800000 { compatible = "qcom,msm8960-pinctrl"; gpio-controller; @@ -127,7 +184,7 @@ msmgpio: pinctrl@800000 { }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; + compatible = "qcom,gcc-msm8960", "syscon"; #clock-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; @@ -135,6 +192,18 @@ gcc: clock-controller@900000 { <&pxo_board>, <&lcc PLL4>; clock-names = "cxo", "pxo", "pll4"; + + tsens: thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; }; lcc: clock-controller@28000000 { From 9ce52e908bd5c0a93a3f17ef28d19209873b573f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 28 Feb 2025 09:40:25 +0100 Subject: [PATCH 131/308] arm64: dts: qcom: sm8650: switch to interrupt-cells 4 to add PPI partitions The ARM PMUs shares the same per-cpu (PPI) interrupt, so we need to switch to interrupt-cells = <4> in the GIC node to allow adding an interrupt partition map phandle as the 4th cell value for GIC_PPI interrupts. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250228-topic-sm8650-pmu-ppi-partition-v4-1-78cffd35c73d@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 542 +++++++++++++-------------- 1 file changed, 271 insertions(+), 271 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 8c551e2f58c6..7dd8ae0d8fee 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -1576,17 +1576,17 @@ opp-3302400000 { pmu-a520 { compatible = "arm,cortex-a520-pmu"; - interrupts = ; + interrupts = ; }; pmu-a720 { compatible = "arm,cortex-a720-pmu"; - interrupts = ; + interrupts = ; }; pmu-x4 { compatible = "arm,cortex-x4-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -1964,7 +1964,7 @@ ipcc: mailbox@406000 { compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; reg = <0 0x00406000 0 0x1000>; - interrupts = ; + interrupts = ; interrupt-controller; #interrupt-cells = <3>; @@ -1975,18 +1975,18 @@ gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00800000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; dma-channels = <12>; dma-channel-mask = <0x3f>; @@ -2022,7 +2022,7 @@ i2c8: i2c@880000 { compatible = "qcom,geni-i2c"; reg = <0 0x00880000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; @@ -2059,7 +2059,7 @@ spi8: spi@880000 { compatible = "qcom,geni-spi"; reg = <0 0x00880000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; @@ -2096,7 +2096,7 @@ i2c9: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; @@ -2133,7 +2133,7 @@ spi9: spi@884000 { compatible = "qcom,geni-spi"; reg = <0 0x00884000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; @@ -2170,7 +2170,7 @@ i2c10: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; @@ -2207,7 +2207,7 @@ spi10: spi@888000 { compatible = "qcom,geni-spi"; reg = <0 0x00888000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; @@ -2244,7 +2244,7 @@ i2c11: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; @@ -2281,7 +2281,7 @@ spi11: spi@88c000 { compatible = "qcom,geni-spi"; reg = <0 0x0088c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; @@ -2318,7 +2318,7 @@ i2c12: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; @@ -2355,7 +2355,7 @@ spi12: spi@890000 { compatible = "qcom,geni-spi"; reg = <0 0x00890000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; @@ -2392,7 +2392,7 @@ i2c13: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; @@ -2429,7 +2429,7 @@ spi13: spi@894000 { compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; @@ -2466,7 +2466,7 @@ uart14: serial@898000 { compatible = "qcom,geni-uart"; reg = <0 0x00898000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; @@ -2492,7 +2492,7 @@ uart15: serial@89c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x0089c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; clock-names = "se"; @@ -2532,7 +2532,7 @@ i2c_hub_0: i2c@980000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00980000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2563,7 +2563,7 @@ i2c_hub_1: i2c@984000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00984000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2594,7 +2594,7 @@ i2c_hub_2: i2c@988000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00988000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2625,7 +2625,7 @@ i2c_hub_3: i2c@98c000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x0098c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2656,7 +2656,7 @@ i2c_hub_4: i2c@990000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00990000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2687,7 +2687,7 @@ i2c_hub_5: i2c@994000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00994000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2718,7 +2718,7 @@ i2c_hub_6: i2c@998000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00998000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2749,7 +2749,7 @@ i2c_hub_7: i2c@99c000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x0099c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2780,7 +2780,7 @@ i2c_hub_8: i2c@9a0000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x009a0000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2811,7 +2811,7 @@ i2c_hub_9: i2c@9a4000 { compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x009a4000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -2843,18 +2843,18 @@ gpi_dma1: dma-controller@a00000 { compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; dma-channels = <12>; dma-channel-mask = <0xc>; @@ -2893,7 +2893,7 @@ i2c0: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a80000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; @@ -2930,7 +2930,7 @@ spi0: spi@a80000 { compatible = "qcom,geni-spi"; reg = <0 0x00a80000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; @@ -2967,7 +2967,7 @@ i2c1: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; @@ -3004,7 +3004,7 @@ spi1: spi@a84000 { compatible = "qcom,geni-spi"; reg = <0 0x00a84000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; @@ -3041,7 +3041,7 @@ i2c2: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; @@ -3078,7 +3078,7 @@ spi2: spi@a88000 { compatible = "qcom,geni-spi"; reg = <0 0x00a88000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; @@ -3115,7 +3115,7 @@ i2c3: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; @@ -3152,7 +3152,7 @@ spi3: spi@a8c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a8c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; @@ -3189,7 +3189,7 @@ i2c4: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; @@ -3226,7 +3226,7 @@ spi4: spi@a90000 { compatible = "qcom,geni-spi"; reg = <0 0x00a90000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; @@ -3263,7 +3263,7 @@ i2c5: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; @@ -3300,7 +3300,7 @@ spi5: spi@a94000 { compatible = "qcom,geni-spi"; reg = <0 0x00a94000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; @@ -3337,7 +3337,7 @@ i2c6: i2c@a98000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a98000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; @@ -3374,7 +3374,7 @@ spi6: spi@a98000 { compatible = "qcom,geni-spi"; reg = <0 0x00a98000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; @@ -3411,7 +3411,7 @@ i2c7: i2c@a9c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a9c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; @@ -3448,7 +3448,7 @@ spi7: spi@a9c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a9c000 0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; @@ -3568,15 +3568,15 @@ pcie0: pcie@1c00000 { <0 0x60100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; - interrupts = , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -3621,10 +3621,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommu-map = <0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; @@ -3743,15 +3743,15 @@ pcie1: pcie@1c08000 { "atu", "config"; - interrupts = , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -3801,10 +3801,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommu-map = <0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; @@ -3922,7 +3922,7 @@ cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x28000>; - interrupts = ; + interrupts = ; #dma-cells = <1>; @@ -3976,7 +3976,7 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0 0x01d84000 0 0x3000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -4097,7 +4097,7 @@ gpu: gpu@3d00000 { "cx_mem", "cx_dbgc"; - interrupts = ; + interrupts = ; iommus = <&adreno_smmu 0 0x0>, <&adreno_smmu 1 0x0>; @@ -4196,8 +4196,8 @@ gmu: gmu@3d6a000 { <0x0 0x0b280000 0x0 0x10000>; reg-names = "gmu", "rscc", "gmu_pdc"; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_AHB_CLK>, @@ -4260,32 +4260,32 @@ adreno_smmu: iommu@3da0000 { reg = <0x0 0x03da0000 0x0 0x40000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, @@ -4310,8 +4310,8 @@ ipa: ipa@3f40000 { "ipa-shared", "gsi"; - interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", @@ -4343,7 +4343,7 @@ remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8650-mpss-pas"; reg = <0x0 0x04080000 0x0 0x10000>; - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, @@ -4560,7 +4560,7 @@ lpass_wsa2macro: codec@6aa0000 { swr3: soundwire@6ab0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ab0000 0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&lpass_wsa2macro>; clock-names = "iface"; label = "WSA2"; @@ -4607,7 +4607,7 @@ lpass_rxmacro: codec@6ac0000 { swr1: soundwire@6ad0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ad0000 0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&lpass_rxmacro>; clock-names = "iface"; label = "RX"; @@ -4671,7 +4671,7 @@ lpass_wsamacro: codec@6b00000 { swr0: soundwire@6b10000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06b10000 0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&lpass_wsamacro>; clock-names = "iface"; label = "WSA"; @@ -4701,8 +4701,8 @@ swr0: soundwire@6b10000 { swr2: soundwire@6d30000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06d30000 0 0x10000>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "core", "wakeup"; clocks = <&lpass_txmacro>; clock-names = "iface"; @@ -4893,8 +4893,8 @@ sdhc_2: mmc@8804000 { compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; @@ -4968,7 +4968,7 @@ videocc: clock-controller@aaf0000 { cci0: cci@ac15000 { compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; reg = <0 0x0ac15000 0 0x1000>; - interrupts = ; + interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -5001,7 +5001,7 @@ cci0_i2c1: i2c-bus@1 { cci1: cci@ac16000 { compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; reg = <0 0x0ac16000 0 0x1000>; - interrupts = ; + interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -5034,7 +5034,7 @@ cci1_i2c1: i2c-bus@1 { cci2: cci@ac17000 { compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; reg = <0 0x0ac17000 0 0x1000>; - interrupts = ; + interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -5082,7 +5082,7 @@ mdss: display-subsystem@ae00000 { reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; - interrupts = ; + interrupts = ; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, @@ -5554,8 +5554,8 @@ usb_1: usb@a6f8800 { compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&pdc 15 IRQ_TYPE_EDGE_RISING>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; @@ -5604,7 +5604,7 @@ usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; + interrupts = ; iommus = <&apps_smmu 0x40 0>; @@ -5668,8 +5668,8 @@ tsens0: thermal-sensor@c228000 { reg = <0 0x0c228000 0 0x1000>, /* TM */ <0 0x0c222000 0 0x1000>; /* SROT */ - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; @@ -5683,8 +5683,8 @@ tsens1: thermal-sensor@c229000 { reg = <0 0x0c229000 0 0x1000>, /* TM */ <0 0x0c223000 0 0x1000>; /* SROT */ - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; @@ -5698,8 +5698,8 @@ tsens2: thermal-sensor@c22a000 { reg = <0 0x0c22a000 0 0x1000>, /* TM */ <0 0x0c224000 0 0x1000>; /* SROT */ - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; @@ -5757,7 +5757,7 @@ tlmm: pinctrl@f100000 { compatible = "qcom,sm8650-tlmm"; reg = <0 0x0f100000 0 0x300000>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <2>; @@ -6633,103 +6633,103 @@ apps_smmu: iommu@15000000 { compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; #iommu-cells = <2>; #global-interrupts = <1>; @@ -6742,9 +6742,9 @@ intc: interrupt-controller@17100000 { reg = <0 0x17100000 0 0x10000>, /* GICD */ <0 0x17180000 0 0x200000>; /* GICR * 8 */ - interrupts = ; + interrupts = ; - #interrupt-cells = <3>; + #interrupt-cells = <4>; interrupt-controller; #redistributor-regions = <1>; @@ -6775,8 +6775,8 @@ frame@17421000 { reg = <0x17421000 0x1000>, <0x17422000 0x1000>; - interrupts = , - ; + interrupts = , + ; frame-number = <0>; }; @@ -6784,7 +6784,7 @@ frame@17421000 { frame@17423000 { reg = <0x17423000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <1>; @@ -6794,7 +6794,7 @@ frame@17423000 { frame@17425000 { reg = <0x17425000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <2>; @@ -6804,7 +6804,7 @@ frame@17425000 { frame@17427000 { reg = <0x17427000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <3>; @@ -6814,7 +6814,7 @@ frame@17427000 { frame@17429000 { reg = <0x17429000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <4>; @@ -6824,7 +6824,7 @@ frame@17429000 { frame@1742b000 { reg = <0x1742b000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <5>; @@ -6834,7 +6834,7 @@ frame@1742b000 { frame@1742d000 { reg = <0x1742d000 0x1000>; - interrupts = ; + interrupts = ; frame-number = <6>; @@ -6852,9 +6852,9 @@ apps_rsc: rsc@17a00000 { "drv-1", "drv-2"; - interrupts = , - , - ; + interrupts = , + , + ; power-domains = <&cluster_pd>; @@ -6972,10 +6972,10 @@ cpufreq_hw: cpufreq@17d91000 { "freq-domain2", "freq-domain3"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2", @@ -6992,7 +6992,7 @@ pmu@24091000 { compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>; - interrupts = ; + interrupts = ; interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -7044,7 +7044,7 @@ pmu@240b7400 { compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b7400 0 0x600>; - interrupts = ; + interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -7104,7 +7104,7 @@ system-cache-controller@25000000 { "llcc_broadcast_base", "llcc_broadcast_and_base"; - interrupts = ; + interrupts = ; }; nsp_noc: interconnect@320c0000 { @@ -7120,7 +7120,7 @@ remoteproc_cdsp: remoteproc@32300000 { compatible = "qcom,sm8650-cdsp-pas"; reg = <0x0 0x32300000 0x0 0x10000>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -8120,9 +8120,9 @@ modem3-critical { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; From 2c06e0797c32997a2ea9d1458bcdbb97c7090406 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 28 Feb 2025 09:40:26 +0100 Subject: [PATCH 132/308] arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper interrupt partition maps and use the 4th interrupt cell to pass the partition phandle for each ARM PMU node. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250228-topic-sm8650-pmu-ppi-partition-v4-2-78cffd35c73d@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 7dd8ae0d8fee..90917f9f9c5c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -1576,17 +1576,17 @@ opp-3302400000 { pmu-a520 { compatible = "arm,cortex-a520-pmu"; - interrupts = ; + interrupts = ; }; pmu-a720 { compatible = "arm,cortex-a720-pmu"; - interrupts = ; + interrupts = ; }; pmu-x4 { compatible = "arm,cortex-x4-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -6754,6 +6754,20 @@ intc: interrupt-controller@17100000 { #size-cells = <2>; ranges; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; + }; + + ppi_cluster2: interrupt-partition-2 { + affinity = <&cpu7>; + }; + }; + gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; reg = <0 0x17140000 0 0x20000>; From e03ed4ee41c054dcfc3fe8d045e016cc0aa3a22a Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Fri, 28 Feb 2025 16:23:08 +0000 Subject: [PATCH 133/308] arm64: dts: qcom: qrb5165-rb5: add compressed playback support Audio DSP supports compressed playback on this SoC. It is required to add compressed DAI and separate MultimeMedia DAI link to enable this. Fcplay or cplay tools from tinycompress can playback, say, mp3 files: fcplay -c 0 -d 3 test.mp3 Cc: Srinivas Kandagatla Signed-off-by: Alexey Klimov Link: https://lore.kernel.org/r/20250228162308.388818-1-alexey.klimov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 15b187300810..4cc14ab1b9ea 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1018,6 +1018,12 @@ dai@1 { dai@2 { reg = <2>; }; + + dai@3 { + direction = ; + is-compress-dai; + reg = <3>; + }; }; &sdhc_2 { @@ -1050,7 +1056,8 @@ &sound { "VA DMIC1", "vdd-micb", "MM_DL1", "MultiMedia1 Playback", "MM_DL2", "MultiMedia2 Playback", - "MultiMedia3 Capture", "MM_UL3"; + "MultiMedia3 Capture", "MM_UL3", + "MM_DL4", "MultiMedia4 Playback"; mm1-dai-link { link-name = "MultiMedia1"; @@ -1073,6 +1080,14 @@ cpu { }; }; + mm4-dai-link { + link-name = "MultiMedia4"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>; + }; + }; + hdmi-dai-link { link-name = "HDMI Playback"; cpu { From 05ed68070d7a061f62f502d07f883c05dc666990 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 3 Mar 2025 11:29:31 +0800 Subject: [PATCH 134/308] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes Add CTCU and ETR nodes in DT to enable related functionalities. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Acked-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20250303032931.2500935-11-quic_jiegan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 153 ++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 6a2c49047df5..581dac8556ec 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2420,6 +2420,35 @@ cryptobam: dma-controller@1dc4000 { <&apps_smmu 0x481 0x00>; }; + ctcu@4001000 { + compatible = "qcom,sa8775p-ctcu"; + reg = <0x0 0x04001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; + }; + stm: stm@4002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x4002000 0x0 0x1000>, @@ -2624,6 +2653,122 @@ qdss_funnel_in1: endpoint { }; }; + replicator@4046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x04046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc_etr: tmc@4048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x04048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04c0 0x00>; + + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@404e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x0404e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc_etr1: tmc@404f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x0404f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04a0 0x40>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x4b04000 0x0 0x1000>; @@ -2699,6 +2844,14 @@ out-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; swao_rep_out1: endpoint { From 37bd695c16b1b443e357eb37c09ef30b401f8b83 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Mon, 3 Mar 2025 18:07:01 +0530 Subject: [PATCH 135/308] arm64: dts: qcom: sc7280: drop video decoder and encoder nodes Decoder and encoder nodes are already deprecated from bindings. Update the venus node to align with bindings. The nodes were deprecated with commit 459997e8990d9 ("media: dt-bindings: qcom-venus: Deprecate video-decoder and video-encoder where applicable") and is part of v6.14-rc1 and onwards. Signed-off-by: Vikash Garodia Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250303-b4-media-v2-1-893651a4b1c7@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0f2caf36910b..31abb2b9555f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4301,14 +4301,6 @@ venus: video-codec@aa00000 { status = "disabled"; - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - venus_opp_table: opp-table { compatible = "operating-points-v2"; From 4ca8d6f898a85070934490071e429e97bc4e219b Mon Sep 17 00:00:00 2001 From: Gabriel Gonzales Date: Tue, 11 Mar 2025 08:33:47 +0800 Subject: [PATCH 136/308] dt-bindings: arm: qcom: Add Xiaomi Redmi Note 8 Document the Xiaomi Redmi Note 8 (codenamed ginkgo), which is based off the SM6125 SoC. Signed-off-by: Gabriel Gonzales Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250311003353.8250-2-semfault@disroot.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 618a87693ac1..52f7b217bd08 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1020,6 +1020,7 @@ properties: - items: - enum: - sony,pdx201 + - xiaomi,ginkgo - xiaomi,laurel-sprout - const: qcom,sm6125 From 9b1a6c925c88ed9331a2cae64fb3580e05345ded Mon Sep 17 00:00:00 2001 From: Gabriel Gonzales Date: Tue, 11 Mar 2025 08:33:48 +0800 Subject: [PATCH 137/308] arm64: dts: qcom: sm6125: Initial support for xiaomi-ginkgo Add support for the Xiaomi Redmi Note 8 based on the SM6125 SoC. Defined features: - dmesg output to bootloader preconfigured display - USB - eMMC - SD card - SMD RPM regulators - Volume Up, Down and Power buttons Signed-off-by: Gabriel Gonzales Link: https://lore.kernel.org/r/20250311003353.8250-3-semfault@disroot.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm6125-xiaomi-ginkgo.dts | 295 ++++++++++++++++++ 2 files changed, 296 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b54f45b3bec8..c90a927b9978 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -246,6 +246,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-ginkgo.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts new file mode 100644 index 000000000000..68a237215bd1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Gabriel Gonzales + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "sm6125.dtsi" +#include "pm6125.dtsi" + +/ { + model = "Xiaomi Redmi Note 8"; + compatible = "xiaomi,ginkgo", "qcom,sm6125"; + chassis-type = "handset"; + + /* required for bootloader to select correct board */ + qcom,msm-id = ; + qcom,board-id = <22 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@5c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (2340 * 1080 * 4)>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + reserved-memory { + debug_mem: debug@ffb00000 { + reg = <0x0 0xffb00000 0x0 0xc0000>; + no-map; + }; + + last_log_mem: lastlog@ffbc0000 { + reg = <0x0 0xffbc0000 0x0 0x80000>; + no-map; + }; + + pstore_mem: ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc40000 0x0 0xc0000>; + record-size = <0x1000>; + console-size = <0x40000>; + pmsg-size = <0x20000>; + }; + + cmdline_mem: memory@ffd00000 { + reg = <0x0 0xffd40000 0x0 0x1000>; + no-map; + }; + }; + + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm6125_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; +}; + +&pm6125_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&hsusb_phy1 { + vdd-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l10a>; + vdda-phy-dpdm-supply = <&vreg_l15a>; + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + vreg_s6a: s6 { + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <1422000>; + }; + + vreg_l1a: l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + }; + + vreg_l2a: l2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1056000>; + }; + + vreg_l3a: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1064000>; + }; + + vreg_l4a: l4 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + regulator-allow-set-load; + }; + + vreg_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + vreg_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + vreg_l7a: l7 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + }; + + vreg_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + vreg_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + }; + + vreg_l10a: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + regulator-allow-set-load; + }; + + vreg_l11a: l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1952000>; + regulator-allow-set-load; + }; + + vreg_l12a: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1996000>; + }; + + vreg_l13a: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1832000>; + }; + + vreg_l14a: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l15a: l15 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3232000>; + }; + + vreg_l16a: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l17a: l17 { + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a: l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1264000>; + regulator-allow-set-load; + }; + + vreg_l19a: l19 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + }; + + vreg_l20a: l20 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + }; + + vreg_l21a: l21 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2856000>; + }; + + vreg_l22a: l22 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + vreg_l23a: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + vreg_l24a: l24 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + }; +}; + +&sdc2_off_state { + sd-cd-pins { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&sdc2_on_state { + sd-cd-pins { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&sdhc_1 { + vmmc-supply = <&vreg_l24a>; + vqmmc-supply = <&vreg_l11a>; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vreg_l22a>; + vqmmc-supply = <&vreg_l5a>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <22 2>, <28 6>; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + extcon = <&extcon_usb>; +}; From 2eabf101f62a158fb66c2ff4a80ccd1581606568 Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Thu, 6 Mar 2025 17:03:55 +0530 Subject: [PATCH 138/308] arm64: dts: qcom: ipq9574: Add SPI nand support Add SPI NAND support for ipq9574 SoC. Signed-off-by: Md Sadre Alam Link: https://lore.kernel.org/r/20250306113357.126602-2-quic_mdalam@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 4c5b8ca4812c..769705d398c4 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -675,6 +675,33 @@ blsp1_spi4: spi@78b9000 { status = "disabled"; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x07984000 0x1c000>; + interrupts = ; + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible = "qcom,ipq9574-snand"; + reg = <0x079b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", "aon", "iom"; + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + usb_0_qusbphy: phy@7b000 { compatible = "qcom,ipq9574-qusb2-phy"; reg = <0x0007b000 0x180>; From 2f24e13c8f090344482fbff4911240eb3c1d9092 Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Thu, 6 Mar 2025 17:03:56 +0530 Subject: [PATCH 139/308] arm64: dts: qcom: ipq9574: Enable SPI NAND for ipq9574 Enable SPI NAND support for ipq9574 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Md Sadre Alam Link: https://lore.kernel.org/r/20250306113357.126602-3-quic_mdalam@quicinc.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index ae12f069f26f..140e989712b2 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -139,6 +139,50 @@ gpio_leds_default: gpio-leds-default-state { drive-strength = <8>; bias-pull-up; }; + + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins = "gpio5"; + function = "qspi_clk"; + drive-strength = <8>; + bias-disable; + }; + + cs-pins { + pins = "gpio4"; + function = "qspi_cs"; + drive-strength = <8>; + bias-disable; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qspi_data"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + pinctrl-0 = <&qpic_snand_default_state>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; }; &usb_0_dwc3 { From 8140d10568a806864c915613ac03afb98ccd349c Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Thu, 6 Mar 2025 17:03:57 +0530 Subject: [PATCH 140/308] arm64: dts: qcom: ipq9574: Remove eMMC node Remove eMMC node for rdp433, since rdp433 default boot mode is norplusnand Reviewed-by: Konrad Dybcio Signed-off-by: Md Sadre Alam Link: https://lore.kernel.org/r/20250306113357.126602-4-quic_mdalam@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 165ebbb59511..fa7bb521e786 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -55,18 +55,6 @@ &pcie3 { status = "okay"; }; -&sdhc_1 { - pinctrl-0 = <&sdc_default_state>; - pinctrl-names = "default"; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - max-frequency = <384000000>; - bus-width = <8>; - status = "okay"; -}; - &tlmm { pcie1_default: pcie1-default-state { From 6810ecd57eb4ba9e09bac851d5b9d56c5e5acc1a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Mar 2025 19:11:17 +0100 Subject: [PATCH 141/308] arm64: dts: qcom: sdx75: Fix up the USB interrupt description Commit 53c6d854be4e ("dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding") reworked the dt-bindings to accurately represent the hardware. Execute the second half of the cleanup by wiring up the missing pwr_event IRQ and adjusting the entry order. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-5-0c84aceb0ef9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index b0a8a0fe5f39..8da2383861e4 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1008,14 +1008,16 @@ usb: usb@a6f8800 { <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 9 IRQ_TYPE_EDGE_RISING>, - <&pdc 10 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 10 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "dp_hs_phy_irq", + "ss_phy_irq"; power-domains = <&gcc GCC_USB30_GDSC>; From a3715ce8650928e2da7060957a7e9b962d8bb7be Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Mar 2025 19:11:18 +0100 Subject: [PATCH 142/308] arm64: dts: qcom: sdx75: Rename AOSS_QMP to power-management The node is currently named power-controller, which requires the device underneath is a power domain provider. Rename it to align with other SoCs and resolve this sort of warnings: power-controller@c310000: '#power-domain-cells' is a required property Fixes: 91f767eb6938 ("arm64: dts: qcom: sdx75: Add AOSS node") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-6-0c84aceb0ef9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 8da2383861e4..8e63f635a327 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1079,7 +1079,7 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; - aoss_qmp: power-controller@c310000 { + aoss_qmp: power-management@c310000 { compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c310000 0 0x1000>; interrupt-parent = <&ipcc>; From bc09537f4745aae561f56daad0353d1b876bc096 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Mar 2025 19:11:19 +0100 Subject: [PATCH 143/308] arm64: dts: qcom: qcs615: Rename AOSS_QMP to power-management The node is currently named power-controller, which requires the device underneath is a power domain provider. Rename it to align with other SoCs and resolve this sort of warnings: power-controller@c300000: '#power-domain-cells' is a required property Fixes: 0775021783b5 ("arm64: dts: qcom: qcs615: add AOSS_QMP node") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-7-0c84aceb0ef9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index f9398cf95003..1627110bcfc9 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3208,7 +3208,7 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; interrupts = ; From 9ea77c65b7b0357c54899a24ffd37d0430c90913 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Mar 2025 19:11:20 +0100 Subject: [PATCH 144/308] arm64: dts: qcom: sc8180x: Rename AOSS_QMP to power-management The node is currently named power-controller, which requires the device underneath is a power domain provider. Rename it to align with other SoCs and resolve this sort of warnings: power-controller@c310000: '#power-domain-cells' is a required property Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-8-0c84aceb0ef9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 28693a3bfc7f..f142eb63b8d7 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3524,7 +3524,7 @@ tsens1: thermal-sensor@c265000 { #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; interrupts = ; From 6d617082867d4789ea4dcc67fc483460e2ac1d05 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Mar 2025 19:11:21 +0100 Subject: [PATCH 145/308] arm64: dts: qcom: x1e80100-dell-xps13-9345: Drop clock-names from PS8830 The preemptively-merged node contains a property absent from the final bindings. Remove it. Signed-off-by: Konrad Dybcio Fixes: bd2dbbb1f35a ("arm64: dts: qcom: x1e80100-dell-xps13-9345: Introduce retimer support") Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-9-0c84aceb0ef9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 124051334be0..5d807fb34aee 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -612,7 +612,6 @@ typec-mux@8 { reg = <0x08>; clocks = <&rpmhcc RPMH_RF_CLK3>; - clock-names = "xo"; vdd-supply = <&vreg_rtmr0_1p15>; vdd33-supply = <&vreg_rtmr0_3p3>; @@ -676,7 +675,6 @@ typec-mux@8 { reg = <0x8>; clocks = <&rpmhcc RPMH_RF_CLK4>; - clock-names = "xo"; vdd-supply = <&vreg_rtmr1_1p15>; vdd33-supply = <&vreg_rtmr1_3p3>; From 57aac7bd091cd7a1f43c852ce3703ce6c2433b21 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Mar 2025 19:11:22 +0100 Subject: [PATCH 146/308] arm64: dts: qcom: x1e80100-romulus: Drop clock-names from PS8830 The preemptively-merged node contains a property absent from the final bindings. Remove it. Signed-off-by: Konrad Dybcio Fixes: b16ee3d0cda4 ("arm64: dts: qcom: x1e80100-romulus: Set up PS8830s") Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-10-0c84aceb0ef9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 6a883fafe3c7..da8cef62ae73 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -794,7 +794,6 @@ typec-mux@8 { reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; clocks = <&rpmhcc RPMH_RF_CLK3>; - clock-names = "xo"; vdd-supply = <&vreg_rtmr0_1p15>; vdd33-supply = <&vreg_rtmr0_3p3>; @@ -880,7 +879,6 @@ typec-mux@8 { reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; clocks = <&rpmhcc RPMH_RF_CLK4>; - clock-names = "xo"; vdd-supply = <&vreg_rtmr1_1p15>; vdd33-supply = <&vreg_rtmr1_3p3>; From 8cd4b0f6bc71b2bf4f5c3fb8ec2857192182cb23 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Mar 2025 19:11:23 +0100 Subject: [PATCH 147/308] arm64: dts: qcom: x1e001de-devkit: Drop clock-names from PS8830 The preemptively-merged node contains a property absent from the final bindings. Remove it. Signed-off-by: Konrad Dybcio Fixes: 019e1ee32fec ("arm64: dts: qcom: x1e001de-devkit: Enable external DP support") Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-11-0c84aceb0ef9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 602bd793e09c..f87730f4b63f 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -777,7 +777,6 @@ typec-mux@8 { reg = <0x08>; clocks = <&rpmhcc RPMH_RF_CLK5>; - clock-names = "xo"; vdd-supply = <&vreg_rtmr2_1p15>; vdd33-supply = <&vreg_rtmr2_3p3>; @@ -832,7 +831,6 @@ typec-mux@8 { reg = <0x08>; clocks = <&rpmhcc RPMH_RF_CLK3>; - clock-names = "xo"; vdd-supply = <&vreg_rtmr0_1p15>; vdd33-supply = <&vreg_rtmr0_3p3>; @@ -887,7 +885,6 @@ typec-mux@8 { reg = <0x8>; clocks = <&rpmhcc RPMH_RF_CLK4>; - clock-names = "xo"; vdd-supply = <&vreg_rtmr1_1p15>; vdd33-supply = <&vreg_rtmr1_3p3>; From 9eca3fd5c336afc3b90804ec008f54ce59320aee Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 7 Mar 2025 18:12:21 +0100 Subject: [PATCH 148/308] arm64: dts: qcom: x1e80100-crd: add support for volume-up key Add support for the keypad volume-up key on the debug extension board. This is useful to have when testing PMIC interrupt handling, and the key can also be used to wake up from deep suspend states (CX shutdown). Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250307171222.7470-2-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 53f329c32019..f74c576f1c13 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -52,9 +52,16 @@ chosen { gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&hall_int_n_default>; + pinctrl-0 = <&hall_int_n_default>, <&kypd_vol_up_n>; pinctrl-names = "default"; + key-vol-up { + label = "volume_up"; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + switch-lid { gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; linux,input-type = ; @@ -1240,6 +1247,14 @@ &pcie6a_phy { }; &pm8550_gpios { + kypd_vol_up_n: kypd-vol-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; /* 1.8 V */ + bias-pull-up; + input-enable; + }; + rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; function = "normal"; From ee95bcc58890e63f52fdb9ab096c3d7b9cb889cc Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 7 Mar 2025 18:12:22 +0100 Subject: [PATCH 149/308] arm64: dts: qcom: x1e80100-crd: add gpio-keys label for lid switch Add a gpio-keys label for the lid-switch for consistency and to separate it from the volume-up key (e.g. in /proc/interrupts). Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250307171222.7470-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index f74c576f1c13..9e587dc57532 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -63,6 +63,7 @@ key-vol-up { }; switch-lid { + label = "lid"; gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; From 28f997b89967afdc0855d8aa7538b251fb44f654 Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Sat, 8 Mar 2025 18:27:51 +0800 Subject: [PATCH 150/308] arm64: dts: qcom: sm8250: Fix CPU7 opp table There is a typo in cpu7_opp9. Fix it to get rid of the following errors. [ 0.198043] cpu cpu7: Voltage update failed freq=1747200 [ 0.198052] cpu cpu7: failed to update OPP for freq=1747200 Fixes: 8e0e8016cb79 ("arm64: dts: qcom: sm8250: Add CPU opp tables") Signed-off-by: Xilin Wu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250308-fix-sm8250-cpufreq-v1-1-8a0226721399@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c2937b4d9f18..68613ea7146c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -606,7 +606,7 @@ cpu7_opp8: opp-1632000000 { }; cpu7_opp9: opp-1747200000 { - opp-hz = /bits/ 64 <1708800000>; + opp-hz = /bits/ 64 <1747200000>; opp-peak-kBps = <5412000 42393600>; }; From 64f8541e7a2c5e91498f297bce89a88ab9a34fd3 Mon Sep 17 00:00:00 2001 From: Manish Nagar Date: Mon, 10 Mar 2025 16:17:43 +0530 Subject: [PATCH 151/308] arm64: dts: qcom: qcs8300-ride: Enable second USB controller on QCS8300 Ride Enable secondary USB controller on QCS8300 Ride platform. Since it is a Type-A port, the dr_mode has been set to "host". The VBUS to connected peripherals is provided by TPS2559QWDRCTQ1 regulator connected to the port. The regulator has an enable pin controlled by PMM8650. Model it as fixed regulator and keep it Always-On at boot, since the regulator is GPIO controlled regulator. Co-developed-by: Krishna Kurapati Signed-off-by: Krishna Kurapati Signed-off-by: Manish Nagar Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250310104743.976265-1-quic_mnagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 2835b81d86ff..3ff8f398cad3 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -22,6 +22,16 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + regulator-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB2_VBUS"; + gpio = <&pmm8650au_1_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb2_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; }; &apps_rsc { @@ -285,6 +295,15 @@ queue3 { }; }; +&pmm8650au_1_gpios { + usb2_en: usb2-en-state { + pins = "gpio7"; + function = "normal"; + output-enable; + power-source = <0>; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -354,6 +373,14 @@ &usb_1_hsphy { status = "okay"; }; +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + &usb_qmpphy { vdda-phy-supply = <&vreg_l7a>; vdda-pll-supply = <&vreg_l5a>; @@ -368,3 +395,11 @@ &usb_1 { &usb_1_dwc3 { dr_mode = "peripheral"; }; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; From 28ef67df3658365b0a8ae6b54c800e70b0216778 Mon Sep 17 00:00:00 2001 From: Pratyush Brahma Date: Mon, 10 Mar 2025 16:48:35 +0530 Subject: [PATCH 152/308] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu Add the device node for gfx smmu that is required for gpu specific address translations. Signed-off-by: Pratyush Brahma Link: https://lore.kernel.org/r/20250310-b4-branch-gfx-smmu-v6-2-15c60b8abd99@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 39 +++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index cdd412706b5b..72d4f9e382da 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -3909,6 +3909,45 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x3da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + pmu@9091000 { compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0x0 0x9091000 0x0 0x1000>; From 4001b1bffd21d5cdbdc84d6b97213e68fed9c785 Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Wed, 12 Mar 2025 15:19:48 +0530 Subject: [PATCH 153/308] arm64: dts: qcom: ipq5424: add reserved memory region for bootloader In IPQ5424, the bootloader collects the system RAM contents upon a crash for post-morterm analysis. If we don't reserve the memory region used by the bootloader, linux will consume it. Upon the next boot after a crash, the bootloader will be loaded in the same region, which could lead to the loss of some data. sometimes, we may miss out critical information. Therefore, let's reserve the region used by the bootloader. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250312094948.3376126-1-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 402d0a2c7bcc..5d6ed2172b1b 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -132,6 +132,11 @@ reserved-memory { #size-cells = <2>; ranges; + bootloader@8a200000 { + reg = <0x0 0x8a200000 0x0 0x400000>; + no-map; + }; + tz@8a600000 { reg = <0x0 0x8a600000 0x0 0x200000>; no-map; From 7a54680f192f3fc0a6bac8bf6f91ce7bd63b8907 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Wed, 12 Mar 2025 15:35:44 +0530 Subject: [PATCH 154/308] arm64: dts: qcom: qcs6490-rb3gen2: Add orientation gpio Specify orientation GPIO to the PMIC GLINK node. Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/r/20250312100544.1510190-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index fa7c54f882a4..e6811a094332 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -177,6 +177,7 @@ pmic-glink { #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From 515551e65635b988f2afa9e8683a6b57d6cfba36 Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Wed, 12 Mar 2025 16:13:58 +0530 Subject: [PATCH 155/308] arm64: dts: qcom: sm8750: Correct clocks property for uart14 node Correct the clocks property for the uart14 node to fix UART functionality on QUP2_SE6. The current failure is due to an incorrect clocks assignment. Change the clocks property to GCC_QUPV3_WRAP2_S6_CLK to resolve the issue. Signed-off-by: Jyothi Kumar Seerapu Reviewed-by: Konrad Dybcio Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi") Link: https://lore.kernel.org/r/20250312104358.2558-1-quic_jseerapu@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 735e7628df96..612b99dc3c55 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -1059,7 +1059,7 @@ uart14: serial@898000 { interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS From 6c6d55f41c1b54b16d35f16c02fe99cc0ad019e0 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 12 Mar 2025 12:14:59 +0100 Subject: [PATCH 156/308] arm64: dts: qcom: qcm6490-fairphone-fp5: Add touchscreen node Add a node for the GT9897 touchscreen found on this smartphone connected via SPI. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250312-fp5-touchscreen-v2-1-4bed270e0065@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 356cee8aeba9..0f1c83822f66 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -1069,7 +1069,17 @@ &sdhc_2 { &spi13 { status = "okay"; - /* Goodix touchscreen @ 0 */ + touchscreen@0 { + compatible = "goodix,gt9897"; + reg = <0>; + interrupts-extended = <&tlmm 81 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>; + avdd-supply = <&vreg_l3c>; + vddio-supply = <&vreg_l2c>; + spi-max-frequency = <1000000>; + touchscreen-size-x = <1224>; + touchscreen-size-y = <2700>; + }; }; &tlmm { From 26cc0304d1352a4b1db7d2807cd276ab31e4da05 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 14 Mar 2025 16:03:23 +0200 Subject: [PATCH 157/308] dt-bindings: arm: qcom: Document Lenovo ThinkPad T14s Gen 6 LCD and OLED Due to the difference in how the panel backlight is being handled between the OLED variant and LCD one, it is required to have two separate DTBs. So document the compatible string for both the OLED and LCD variants. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20250314140325.4143779-2-abel.vesa@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 52f7b217bd08..08c329b1e919 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1124,7 +1124,9 @@ properties: - items: - enum: - - lenovo,thinkpad-t14s + - lenovo,thinkpad-t14s-lcd + - lenovo,thinkpad-t14s-oled + - const: lenovo,thinkpad-t14s - const: qcom,x1e78100 - const: qcom,x1e80100 From 31eff589d00b1b41376800ff1322dc88d81f6ee1 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 14 Mar 2025 16:03:24 +0200 Subject: [PATCH 158/308] arm64: dts: qcom: x1e78100-t14s: Add LCD variant with backlight support Due to the fact that Lenovo Thinkpad T14s Gen6 is available with both OLED and LCD, the backlight control differs HW-wise. For the LCD variant, the panel's backlight is controlled via one of the PWMs provided by the PMK8550 PMIC. For the OLED variant, the backlight is internal to the panel and therefore it is not described in devicetree. For this reason, create a generic dtsi for the T14s by renaming the existing dts. While at it, add a node name to panel and drop the enable gpio and pinctrl properties from the panel node. Then add the LCD variant dts file with the old name and describe all backlight related nodes. So the existing dts will now be used for LCD variant while for OLED new dts will be added. Tested-by: Sebastian Reichel Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20250314140325.4143779-3-abel.vesa@linaro.org Signed-off-by: Bjorn Andersson --- .../qcom/x1e78100-lenovo-thinkpad-t14s.dts | 1438 +--------------- .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 1442 +++++++++++++++++ 2 files changed, 1468 insertions(+), 1412 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts index 05b2f3bf1fc8..5cc6a63d1ef6 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts @@ -1,1446 +1,60 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. - * Copyright (c) 2024, Linaro Limited + * Copyright (c) 2025, Linaro Limited */ -/dts-v1/; - -#include -#include -#include -#include - -#include "x1e80100.dtsi" -#include "x1e80100-pmics.dtsi" +#include "x1e78100-lenovo-thinkpad-t14s.dtsi" / { - model = "Lenovo ThinkPad T14s Gen 6"; - compatible = "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100"; - chassis-type = "laptop"; + model = "Lenovo ThinkPad T14s Gen 6 (LCD)"; + compatible = "lenovo,thinkpad-t14s-lcd", "lenovo,thinkpad-t14s", + "qcom,x1e78100", "qcom,x1e80100"; - wcd938x: audio-codec { - compatible = "qcom,wcd9385-codec"; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 4266537>; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; - pinctrl-0 = <&wcd_default>; + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; pinctrl-names = "default"; - - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - - reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; - - vdd-buck-supply = <&vreg_l15b_1p8>; - vdd-rxtx-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l15b_1p8>; - vdd-mic-bias-supply = <&vreg_bob1>; - - #sound-dai-cells = <1>; }; - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&hall_int_n_default>; - pinctrl-names = "default"; - - switch-lid { - gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - wakeup-event-action = ; - }; - }; - - pmic-glink { - compatible = "qcom,x1e80100-pmic-glink", - "qcom,sm8550-pmic-glink", - "qcom,pmic-glink"; - orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, - <&tlmm 123 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - /* Display-adjacent port */ - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss0_hs_in: endpoint { - remote-endpoint = <&usb_1_ss0_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&retimer_ss0_ss_out>; - }; - }; - - port@2 { - reg = <2>; - - pmic_glink_ss0_con_sbu_in: endpoint { - remote-endpoint = <&retimer_ss0_con_sbu_out>; - }; - }; - }; - }; - - /* User-adjacent port */ - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss1_hs_in: endpoint { - remote-endpoint = <&usb_1_ss1_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&retimer_ss1_ss_out>; - }; - }; - - port@2 { - reg = <2>; - - pmic_glink_ss1_con_sbu_in: endpoint { - remote-endpoint = <&retimer_ss1_con_sbu_out>; - }; - }; - }; - }; - }; - - reserved-memory { - linux,cma { - compatible = "shared-dma-pool"; - size = <0x0 0x8000000>; - reusable; - linux,cma-default; - }; - }; - - vreg_edp_3p3: regulator-edp-3p3 { + vreg_edp_bl: regulator-edp-bl { compatible = "regulator-fixed"; - regulator-name = "VREG_EDP_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; - gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; enable-active-high; - pinctrl-0 = <&edp_reg_en>; pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; regulator-boot-on; }; - - vreg_nvme: regulator-nvme { - compatible = "regulator-fixed"; - - regulator-name = "VREG_NVME_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&nvme_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_1p15: regulator-rtmr0-1p15 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_1P15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - - gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_pwr_1p15_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_1p8: regulator-rtmr0-1p8 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_1P8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_1p8_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_3p3: regulator-rtmr0-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_3p3_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr1_1p15: regulator-rtmr1-1p15 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR1_1P15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - - gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb1_pwr_1p15_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr1_1p8: regulator-rtmr1-1p8 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR1_1P8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb1_pwr_1p8_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr1_3p3: regulator-rtmr1-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR1_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb1_pwr_3p3_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vph_pwr: regulator-vph-pwr { - compatible = "regulator-fixed"; - - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - - regulator-always-on; - regulator-boot-on; - }; - - sound { - compatible = "qcom,x1e80100-sndcard"; - model = "X1E80100-LENOVO-Thinkpad-T14s"; - audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", - "SpkrRight IN", "WSA WSA_SPK2 OUT", - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "AMIC2", "MIC BIAS2", - "VA DMIC0", "MIC BIAS1", - "VA DMIC1", "MIC BIAS1", - "VA DMIC0", "VA MIC BIAS1", - "VA DMIC1", "VA MIC BIAS1", - "TX SWR_INPUT1", "ADC2_OUTPUT"; - - wcd-playback-dai-link { - link-name = "WCD Playback"; - - cpu { - sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - wcd-capture-dai-link { - link-name = "WCD Capture"; - - cpu { - sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; - }; - - codec { - sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - wsa-dai-link { - link-name = "WSA Playback"; - - cpu { - sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - va-dai-link { - link-name = "VA Capture"; - - cpu { - sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; - }; - - codec { - sound-dai = <&lpass_vamacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - }; }; -&apps_rsc { - regulators-0 { - compatible = "qcom,pm8550-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob1-supply = <&vph_pwr>; - vdd-bob2-supply = <&vph_pwr>; - vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; - vdd-l2-l13-l14-supply = <&vreg_bob1>; - vdd-l5-l16-supply = <&vreg_bob1>; - vdd-l6-l7-supply = <&vreg_bob2>; - vdd-l8-l9-supply = <&vreg_bob1>; - vdd-l12-supply = <&vreg_s5j_1p2>; - vdd-l15-supply = <&vreg_s4c_1p8>; - vdd-l17-supply = <&vreg_bob2>; - - vreg_bob1: bob1 { - regulator-name = "vreg_bob1"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - - vreg_bob2: bob2 { - regulator-name = "vreg_bob2"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l1b_1p8: ldo1 { - regulator-name = "vreg_l1b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2b_3p0: ldo2 { - regulator-name = "vreg_l2b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l4b_1p8: ldo4 { - regulator-name = "vreg_l4b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l6b_1p8: ldo6 { - regulator-name = "vreg_l6b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l8b_3p0: ldo8 { - regulator-name = "vreg_l8b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l9b_2p9: ldo9 { - regulator-name = "vreg_l9b_2p9"; - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l10b_1p8: ldo10 { - regulator-name = "vreg_l10b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l12b_1p2: ldo12 { - regulator-name = "vreg_l12b_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l13b_3p0: ldo13 { - regulator-name = "vreg_l13b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l14b_3p0: ldo14 { - regulator-name = "vreg_l14b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l15b_1p8: ldo15 { - regulator-name = "vreg_l15b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l17b_2p5: ldo17 { - regulator-name = "vreg_l17b_2p5"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2504000>; - regulator-initial-mode = ; - }; - }; - - regulators-1 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s4-supply = <&vph_pwr>; - - vreg_s4c_1p8: smps4 { - regulator-name = "vreg_s4c_1p8"; - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_l1c_1p2: ldo1 { - regulator-name = "vreg_l1c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l2c_0p8: ldo2 { - regulator-name = "vreg_l2c_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l3c_0p8: ldo3 { - regulator-name = "vreg_l3c_0p8"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - }; - - regulators-2 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "d"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s4c_1p8>; - vdd-s1-supply = <&vph_pwr>; - - vreg_l1d_0p8: ldo1 { - regulator-name = "vreg_l1d_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l2d_0p9: ldo2 { - regulator-name = "vreg_l2d_0p9"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - - vreg_l3d_1p8: ldo3 { - regulator-name = "vreg_l3d_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - regulators-3 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "e"; - - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s5j_1p2>; - - vreg_l2e_0p8: ldo2 { - regulator-name = "vreg_l2e_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vreg_l3e_1p2: ldo3 { - regulator-name = "vreg_l3e_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; - - regulators-4 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s5j_1p2>; - vdd-s1-supply = <&vph_pwr>; - - vreg_s1f_0p7: smps1 { - regulator-name = "vreg_s1f_0p7"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = ; - }; - }; - - regulators-6 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "i"; - - vdd-l1-supply = <&vreg_s4c_1p8>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - - vreg_l1i_1p8: ldo1 { - regulator-name = "vreg_l1i_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2i_1p2: ldo2 { - regulator-name = "vreg_l2i_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3i_0p8: ldo3 { - regulator-name = "vreg_l3i_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - }; - - regulators-7 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "j"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s5-supply = <&vph_pwr>; - - vreg_s5j_1p2: smps5 { - regulator-name = "vreg_s5j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l1j_0p8: ldo1 { - regulator-name = "vreg_l1j_0p8"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - - vreg_l2j_1p2: ldo2 { - regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1256000>; - regulator-initial-mode = ; - }; - - vreg_l3j_0p8: ldo3 { - regulator-name = "vreg_l3j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - }; -}; - -&gpu { - status = "okay"; - - zap-shader { - firmware-name = "qcom/x1e80100/LENOVO/21N1/qcdxkmsuc8380.mbn"; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - - pinctrl-0 = <&qup_i2c0_data_clk>, <&tpad_default>; - pinctrl-names = "default"; - - status = "okay"; - - /* ELAN06E2 or ELAN06E3 */ - touchpad@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; - - wakeup-source; - }; - - /* SYNA8022 or SYNA8024 */ - touchpad@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; - - hid-descr-addr = <0x20>; - interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; - - wakeup-source; - }; - - /* ELAN06F1 or SYNA06F2 */ - keyboard@3a { - compatible = "hid-over-i2c"; - reg = <0x3a>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-0 = <&kybd_default>; - pinctrl-names = "default"; - - wakeup-source; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - - status = "okay"; - - typec-mux@8 { - compatible = "parade,ps8830"; - reg = <0x08>; - - clocks = <&rpmhcc RPMH_RF_CLK3>; - - vdd-supply = <&vreg_rtmr0_1p15>; - vdd33-supply = <&vreg_rtmr0_3p3>; - vdd33-cap-supply = <&vreg_rtmr0_3p3>; - vddar-supply = <&vreg_rtmr0_1p15>; - vddat-supply = <&vreg_rtmr0_1p15>; - vddio-supply = <&vreg_rtmr0_1p8>; - - reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&rtmr0_default>; - pinctrl-names = "default"; - - orientation-switch; - retimer-switch; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - retimer_ss0_ss_out: endpoint { - remote-endpoint = <&pmic_glink_ss0_ss_in>; - }; - }; - - port@1 { - reg = <1>; - - retimer_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; - }; - }; - - port@2 { - reg = <2>; - - retimer_ss0_con_sbu_out: endpoint { - remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; - }; - }; - }; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - - status = "okay"; - - eusb5_repeater: redriver@43 { - compatible = "nxp,ptn3222"; - reg = <0x43>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb5_reset_n>; - pinctrl-names = "default"; - }; - - eusb3_repeater: redriver@47 { - compatible = "nxp,ptn3222"; - reg = <0x47>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb3_reset_n>; - pinctrl-names = "default"; - }; - - eusb6_repeater: redriver@4f { - compatible = "nxp,ptn3222"; - reg = <0x4f>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb6_reset_n>; - pinctrl-names = "default"; - }; -}; - -&i2c7 { - clock-frequency = <400000>; - - status = "okay"; - - typec-mux@8 { - compatible = "parade,ps8830"; - reg = <0x8>; - - clocks = <&rpmhcc RPMH_RF_CLK4>; - - vdd-supply = <&vreg_rtmr1_1p15>; - vdd33-supply = <&vreg_rtmr1_3p3>; - vdd33-cap-supply = <&vreg_rtmr1_3p3>; - vddar-supply = <&vreg_rtmr1_1p15>; - vddat-supply = <&vreg_rtmr1_1p15>; - vddio-supply = <&vreg_rtmr1_1p8>; - - reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&rtmr1_default>; - pinctrl-names = "default"; - - retimer-switch; - orientation-switch; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - retimer_ss1_ss_out: endpoint { - remote-endpoint = <&pmic_glink_ss1_ss_in>; - }; - }; - - port@1 { - reg = <1>; - - retimer_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; - }; - }; - - port@2 { - reg = <2>; - - retimer_ss1_con_sbu_out: endpoint { - remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; - }; - }; - }; - }; -}; - -&i2c8 { - clock-frequency = <400000>; - - status = "okay"; - - /* ILIT2911 or GTCH1563 */ - touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-0 = <&ts0_default>; - pinctrl-names = "default"; - }; - - /* TODO: second-sourced touchscreen @ 0x41 */ -}; - -&lpass_tlmm { - spkr_01_sd_n_active: spkr-01-sd-n-active-state { - pins = "gpio12"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-low; - }; -}; - -&lpass_vamacro { - pinctrl-0 = <&dmic01_default>; - pinctrl-names = "default"; - - vdd-micb-supply = <&vreg_l1b_1p8>; - qcom,dmic-sample-rate = <4800000>; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dp0 { - status = "okay"; -}; - -&mdss_dp0_out { - data-lanes = <0 1>; -}; - -&mdss_dp1 { - status = "okay"; -}; - -&mdss_dp1_out { - data-lanes = <0 1>; -}; - -&mdss_dp3 { - compatible = "qcom,x1e80100-dp"; - /delete-property/ #sound-dai-cells; - - status = "okay"; - - aux-bus { - panel { - compatible = "edp-panel"; - enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; - power-supply = <&vreg_edp_3p3>; - - pinctrl-0 = <&edp_bl_en>; - pinctrl-names = "default"; - - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss_dp3_out>; - }; - }; - }; - }; - - ports { - port@1 { - reg = <1>; - - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; - }; - }; - }; -}; - -&mdss_dp3_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&pcie4_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie4_phy { - vdda-phy-supply = <&vreg_l3i_0p8>; - vdda-pll-supply = <&vreg_l3e_1p2>; - - status = "okay"; -}; - -&pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - - vddpe-3v3-supply = <&vreg_nvme>; - - pinctrl-0 = <&pcie6a_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie6a_phy { - vdda-phy-supply = <&vreg_l1d_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pm8550_gpios { - rtmr0_default: rtmr0-reset-n-active-state { - pins = "gpio10"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; - - usb0_3p3_reg_en: usb0-3p3-reg-en-state { - pins = "gpio11"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pm8550ve_9_gpios { - usb0_1p8_reg_en: usb0-1p8-reg-en-state { - pins = "gpio8"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; +&panel { + backlight = <&backlight>; }; &pmc8380_3_gpios { - edp_bl_en: edp-bl-en-state { - pins = "gpio4"; + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; function = "normal"; - power-source = <1>; - input-disable; - output-enable; }; }; -&pmc8380_5_gpios { - usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { - pins = "gpio8"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; }; }; -&qupv3_0 { - status = "okay"; -}; - -&qupv3_1 { - status = "okay"; -}; - -&qupv3_2 { - status = "okay"; -}; - -&remoteproc_adsp { - firmware-name = "qcom/x1e80100/LENOVO/21N1/qcadsp8380.mbn", - "qcom/x1e80100/LENOVO/21N1/adsp_dtbs.elf"; - - status = "okay"; -}; - -&remoteproc_cdsp { - firmware-name = "qcom/x1e80100/LENOVO/21N1/qccdsp8380.mbn", - "qcom/x1e80100/LENOVO/21N1/cdsp_dtbs.elf"; - - status = "okay"; -}; - -&smb2360_0 { - status = "okay"; -}; - -&smb2360_0_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l2b_3p0>; -}; - -&smb2360_1 { - status = "okay"; -}; - -&smb2360_1_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l14b_3p0>; -}; - -&swr0 { - status = "okay"; - - pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; - pinctrl-names = "default"; - - /* WSA8845, Left Speaker */ - left_spkr: speaker@0,0 { - compatible = "sdw20217020400"; - reg = <0 0>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "SpkrLeft"; - vdd-1p8-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l12b_1p2>; - qcom,port-mapping = <1 2 3 7 10 13>; - }; - - /* WSA8845, Right Speaker */ - right_spkr: speaker@0,1 { - compatible = "sdw20217020400"; - reg = <0 1>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "SpkrRight"; - vdd-1p8-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l12b_1p2>; - qcom,port-mapping = <4 5 6 7 11 13>; - }; -}; - -&swr1 { - status = "okay"; - - /* WCD9385 RX */ - wcd_rx: codec@0,4 { - compatible = "sdw20217010d00"; - reg = <0 4>; - qcom,rx-port-mapping = <1 2 3 4 5>; - }; -}; - -&swr2 { - status = "okay"; - - /* WCD9385 TX */ - wcd_tx: codec@0,3 { - compatible = "sdw20217010d00"; - reg = <0 3>; - qcom,tx-port-mapping = <2 2 3 4>; - }; -}; - -&tlmm { - gpio-reserved-ranges = <34 2>, /* Unused */ - <44 4>, /* SPI (TPM) */ - <72 2>, /* Secure EC I2C connection (?) */ - <238 1>; /* UFS Reset */ - - eusb3_reset_n: eusb3-reset-n-state { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - - eusb5_reset_n: eusb5-reset-n-state { - pins = "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - - eusb6_reset_n: eusb6-reset-n-state { - pins = "gpio184"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - - tpad_default: tpad-default-state { - pins = "gpio3"; - function = "gpio"; - bias-pull-up; - }; - - nvme_reg_en: nvme-reg-en-state { - pins = "gpio18"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - ts0_default: ts0-default-state { - reset-n-pins { - pins = "gpio48"; - function = "gpio"; - output-high; - drive-strength = <16>; - }; - - int-n-pins { - pins = "gpio51"; - function = "gpio"; - bias-disable; - }; - }; - - kybd_default: kybd-default-state { - pins = "gpio67"; - function = "gpio"; - bias-disable; - }; - - edp_reg_en: edp-reg-en-state { - pins = "gpio70"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - hall_int_n_default: hall-int-n-state { - pins = "gpio92"; - function = "gpio"; - bias-disable; - }; - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins = "gpio147"; - function = "pcie4_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio146"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio148"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie6a_default: pcie6a-default-state { - clkreq-n-pins { - pins = "gpio153"; - function = "pcie6a_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio152"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio154"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - rtmr1_default: rtmr1-reset-n-active-state { - pins = "gpio176"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { - pins = "gpio188"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { - pins = "gpio175"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { - pins = "gpio186"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wcd_default: wcd-reset-n-active-state { - pins = "gpio191"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-low; - }; -}; - -&usb_1_ss0_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_0_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; - - status = "okay"; -}; - -&usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss0_dwc3_hs { - remote-endpoint = <&pmic_glink_ss0_hs_in>; -}; - -&usb_1_ss0_qmpphy_out { - remote-endpoint = <&retimer_ss0_ss_in>; -}; - -&usb_1_ss1_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_1_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; - - status = "okay"; -}; - -&usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss1_dwc3_hs { - remote-endpoint = <&pmic_glink_ss1_hs_in>; -}; - -&usb_1_ss1_qmpphy_out { - remote-endpoint = <&retimer_ss1_ss_in>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb5_repeater>; - - status = "okay"; -}; - -&usb_mp { - status = "okay"; -}; - -&usb_mp_hsphy0 { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb6_repeater>; - - status = "okay"; -}; - -&usb_mp_hsphy1 { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb3_repeater>; - - status = "okay"; -}; - -&usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; - - status = "okay"; -}; - -&usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; - +&pmk8550_pwm { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi new file mode 100644 index 000000000000..eff0e73640bc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -0,0 +1,1442 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" + +/ { + model = "Lenovo ThinkPad T14s Gen 6"; + compatible = "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100"; + chassis-type = "laptop"; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-Thinkpad-T14s"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/x1e80100/LENOVO/21N1/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + pinctrl-0 = <&qup_i2c0_data_clk>, <&tpad_default>; + pinctrl-names = "default"; + + status = "okay"; + + /* ELAN06E2 or ELAN06E3 */ + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; + + /* SYNA8022 or SYNA8024 */ + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + }; + + /* ELAN06F1 or SYNA06F2 */ + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + /* ILIT2911 or GTCH1563 */ + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; + + /* TODO: second-sourced touchscreen @ 0x41 */ +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/LENOVO/21N1/qcadsp8380.mbn", + "qcom/x1e80100/LENOVO/21N1/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/LENOVO/21N1/qccdsp8380.mbn", + "qcom/x1e80100/LENOVO/21N1/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <72 2>, /* Secure EC I2C connection (?) */ + <238 1>; /* UFS Reset */ + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts0_default: ts0-default-state { + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; From ace6b365cf2a49a3600271186455b1b281babe5c Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 14 Mar 2025 16:03:25 +0200 Subject: [PATCH 159/308] arm64: dts: qcom: x1e78100-t14s: Add OLED variant Since the Lenovo Thinkpad T14s Gen6 is available with an OLED, add dedicated a dedicated dts for it. This is needed because the backlight is handled differently for OLED panels when compared to LCD ones. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20250314140325.4143779-4-abel.vesa@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index c90a927b9978..7c07eb0c0664 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -291,6 +291,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb +dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s-oled.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts new file mode 100644 index 000000000000..be65fafafa73 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Linaro Limited + */ + +#include "x1e78100-lenovo-thinkpad-t14s.dtsi" + +/ { + model = "Lenovo ThinkPad T14s Gen 6 (OLED)"; + compatible = "lenovo,thinkpad-t14s-oled", "lenovo,thinkpad-t14s", + "qcom,x1e78100", "qcom,x1e80100"; +}; From a2e617f4e6981aa514a569e927f90b0d39bb31b2 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 3 Dec 2024 18:44:02 +0100 Subject: [PATCH 160/308] arm64: dts: qcom: sc8280xp-x13s: Drop duplicate DMIC supplies The WCD938x codec provides two controls for each of the MIC_BIASn outputs: - "MIC BIASn" enables an internal regulator to generate the output with a configurable voltage (qcom,micbiasN-microvolt). - "VA MIC BIASn" enables "pull-up mode" that bypasses the internal regulator and directly outputs fixed 1.8V from the VDD_PX pin. This is intended for low-power VA (voice activation) use cases. The audio-routing setup for the ThinkPad X13s currently specifies both as power supplies for the DMICs, but only one of them can be active at the same time. In practice, only the internal regulator is used with the current setup because the driver prefers it over pull-up mode. Make this more clear by dropping the redundant routes to the pull-up "VA MIC BIASn" supply. There is no functional difference except that we skip briefly switching to pull-up mode when shutting down the microphone. Fixes: 2e498f35c385 ("arm64: dts: qcom: sc8280xp-x13s: fix va dmic dai links and routing") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20241203-x1e80100-va-mic-bias-v1-1-0dfd4d9b492c@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 6ddb954a04fd..3053e17731fe 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1202,9 +1202,6 @@ &sound { "VA DMIC0", "MIC BIAS1", "VA DMIC1", "MIC BIAS1", "VA DMIC2", "MIC BIAS3", - "VA DMIC0", "VA MIC BIAS1", - "VA DMIC1", "VA MIC BIAS1", - "VA DMIC2", "VA MIC BIAS3", "TX SWR_ADC1", "ADC2_OUTPUT"; wcd-playback-dai-link { From b49e37de8e70bc433b526a9f4382f72b7ac6492e Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 3 Dec 2024 18:44:03 +0100 Subject: [PATCH 161/308] arm64: dts: qcom: x1e80100-crd: Drop duplicate DMIC supplies The WCD938x codec provides two controls for each of the MIC_BIASn outputs: - "MIC BIASn" enables an internal regulator to generate the output with a configurable voltage (qcom,micbiasN-microvolt). - "VA MIC BIASn" enables "pull-up mode" that bypasses the internal regulator and directly outputs fixed 1.8V from the VDD_PX pin. This is intended for low-power VA (voice activation) use cases. The audio-routing setup for the X1E80100 CRD currently specifies both as power supplies for the DMICs, but only one of them can be active at the same time. In practice, only the internal regulator is used with the current setup because the driver prefers it over pull-up mode. Make this more clear by dropping the redundant routes to the pull-up "VA MIC BIASn" supply. There is no functional difference except that we skip briefly switching to pull-up mode when shutting down the microphone. Fixes: 4442a67eedc1 ("arm64: dts: qcom: x1e80100-crd: add sound card") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20241203-x1e80100-va-mic-bias-v1-2-0dfd4d9b492c@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 9e587dc57532..5ea7b30983d9 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -217,10 +217,6 @@ sound { "VA DMIC1", "MIC BIAS3", "VA DMIC2", "MIC BIAS1", "VA DMIC3", "MIC BIAS1", - "VA DMIC0", "VA MIC BIAS3", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", - "VA DMIC3", "VA MIC BIAS1", "TX SWR_INPUT1", "ADC2_OUTPUT"; wcd-playback-dai-link { From 3529d9536105b78d9756ef81722554a7f9e3c6b0 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 7 Mar 2025 18:10:36 +0100 Subject: [PATCH 162/308] arm64: dts: qcom: sc8280xp-crd: add support for volume-up key Add support for the keypad volume-up key on the debug extension board. This is useful to have when testing PMIC interrupt handling, and the key can also be used to wake up from deep suspend states (CX shutdown). Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250307171036.7276-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index e7251b76d91e..c4a5828be935 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -37,6 +37,20 @@ chosen { stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&kypd_vol_up_n>; + pinctrl-names = "default"; + + key-vol-up { + label = "volume_up"; + gpios = <&pmc8280_1_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + pmic-glink { compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink"; @@ -885,6 +899,14 @@ edp_bl_reg_en: edp-bl-reg-en-state { function = "normal"; }; + kypd_vol_up_n: kypd-vol-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <0>; /* 3.3 V */ + bias-pull-up; + input-enable; + }; + misc_3p3_reg_en: misc-3p3-reg-en-state { pins = "gpio2"; function = "normal"; From abf89bc4bb09c16a53d693b09ea85225cf57ff39 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 14 Mar 2025 15:54:33 +0100 Subject: [PATCH 163/308] arm64: dts: qcom: x1e80100-crd: mark l12b and l15b always-on The l12b and l15b supplies are used by components that are not (fully) described (and some never will be) and must never be disabled. Mark the regulators as always-on to prevent them from being disabled, for example, when consumers probe defer or suspend. Fixes: bd50b1f5b6f3 ("arm64: dts: qcom: x1e80100: Add Compute Reference Device") Cc: stable@vger.kernel.org # 6.8 Cc: Abel Vesa Cc: Rajendra Nayak Cc: Sibi Sankar Reviewed-by: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250314145440.11371-2-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 5ea7b30983d9..f73f053a46a0 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -606,6 +606,7 @@ vreg_l12b_1p2: ldo12 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l13b_3p0: ldo13 { @@ -627,6 +628,7 @@ vreg_l15b_1p8: ldo15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l16b_2p9: ldo16 { From 673fa129e558c5f1196adb27d97ac90ddfe4f19c Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 14 Mar 2025 15:54:34 +0100 Subject: [PATCH 164/308] arm64: dts: qcom: x1e78100-t14s: mark l12b and l15b always-on The l12b and l15b supplies are used by components that are not (fully) described (and some never will be) and must never be disabled. Mark the regulators as always-on to prevent them from being disabled, for example, when consumers probe defer or suspend. Fixes: 7d1cbe2f4985 ("arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6") Cc: stable@vger.kernel.org # 6.12 Reviewed-by: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250314145440.11371-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index eff0e73640bc..160c052db1ec 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -456,6 +456,7 @@ vreg_l12b_1p2: ldo12 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l13b_3p0: ldo13 { @@ -477,6 +478,7 @@ vreg_l15b_1p8: ldo15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l17b_2p5: ldo17 { From 7d328cc134f7db1e062f616a30cffe96fbc43abb Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 14 Mar 2025 15:54:35 +0100 Subject: [PATCH 165/308] arm64: dts: qcom: x1e001de-devkit: mark l12b and l15b always-on The l12b and l15b supplies are used by components that are not (fully) described (and some never will be) and must never be disabled. Mark the regulators as always-on to prevent them from being disabled, for example, when consumers probe defer or suspend. Fixes: 7b8a31e82b87 ("arm64: dts: qcom: Add X1E001DE Snapdragon Devkit for Windows") Cc: stable@vger.kernel.org # 6.14 Cc: Sibi Sankar Reviewed-by: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250314145440.11371-4-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index f87730f4b63f..b133302bf846 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -507,6 +507,7 @@ vreg_l12b_1p2: ldo12 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l13b_3p0: ldo13 { @@ -528,6 +529,7 @@ vreg_l15b_1p8: ldo15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l16b_2p9: ldo16 { From 63169c07d74031c5e10a9f91229dabade880cf0f Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 14 Mar 2025 15:54:36 +0100 Subject: [PATCH 166/308] arm64: dts: qcom: x1e80100-dell-xps13-9345: mark l12b and l15b always-on The l12b and l15b supplies are used by components that are not (fully) described (and some never will be) and must never be disabled. Mark the regulators as always-on to prevent them from being disabled, for example, when consumers probe defer or suspend. Note that these supplies currently have no consumers described in mainline. Fixes: f5b788d0e8cd ("arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345") Cc: stable@vger.kernel.org # 6.13 Reviewed-by: Aleksandrs Vinarskis Tested-by: Aleksandrs Vinarskis Reviewed-by: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250314145440.11371-5-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 5d807fb34aee..967f6dba0878 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -359,6 +359,7 @@ vreg_l12b_1p2: ldo12 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l13b_3p0: ldo13 { @@ -380,6 +381,7 @@ vreg_l15b_1p8: ldo15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l17b_2p5: ldo17 { From 3ab4e212a41c46668adf93c8d10d0d3d6de8f0e4 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 14 Mar 2025 15:54:37 +0100 Subject: [PATCH 167/308] arm64: dts: qcom: x1e80100-hp-x14: mark l12b and l15b always-on The l12b and l15b supplies are used by components that are not (fully) described (and some never will be) and must never be disabled. Mark the regulators as always-on to prevent them from being disabled, for example, when consumers probe defer or suspend. Fixes: 6f18b8d4142c ("arm64: dts: qcom: x1e80100-hp-x14: dt for HP Omnibook X Laptop 14") Cc: stable@vger.kernel.org # 6.14 Cc: Jens Glathe Reviewed-by: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250314145440.11371-6-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index 569748c48200..28298021cc36 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -633,6 +633,7 @@ vreg_l12b_1p2: ldo12 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l13b_3p0: ldo13 { @@ -654,6 +655,7 @@ vreg_l15b_1p8: ldo15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l16b_2p9: ldo16 { From f43a71dc6d8d8378af587675eec77c06e0298c79 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 14 Mar 2025 15:54:38 +0100 Subject: [PATCH 168/308] arm64: dts: qcom: x1e80100-yoga-slim7x: mark l12b and l15b always-on The l12b and l15b supplies are used by components that are not (fully) described (and some never will be) and must never be disabled. Mark the regulators as always-on to prevent them from being disabled, for example, when consumers probe defer or suspend. Fixes: 45247fe17db2 ("arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree") Cc: stable@vger.kernel.org # 6.11 Cc: Srinivas Kandagatla Reviewed-by: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250314145440.11371-7-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 9aff5a1f044d..35d97db9e1f6 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -290,6 +290,7 @@ vreg_l12b_1p2: ldo12 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l14b_3p0: ldo14 { @@ -304,8 +305,8 @@ vreg_l15b_1p8: ldo15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; }; - }; regulators-1 { From ff6ba96378367133b66587bd3ee9f068a39ff3a9 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 14 Mar 2025 15:54:39 +0100 Subject: [PATCH 169/308] arm64: dts: qcom: x1e80100-qcp: mark l12b and l15b always-on The l12b and l15b supplies are used by components that are not (fully) described (and some never will be) and must never be disabled. Mark the regulators as always-on to prevent them from being disabled, for example, when consumers probe defer or suspend. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Cc: stable@vger.kernel.org # 6.8 Cc: Rajendra Nayak Reviewed-by: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250314145440.11371-8-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 28086a2bcf4c..470c4f826d49 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -533,6 +533,7 @@ vreg_l12b_1p2: ldo12 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l13b_3p0: ldo13 { @@ -554,6 +555,7 @@ vreg_l15b_1p8: ldo15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l16b_2p9: ldo16 { From 55e52d055393f11ba0193975d3db87af36f4b273 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 14 Mar 2025 15:54:40 +0100 Subject: [PATCH 170/308] arm64: dts: qcom: x1e78100-t14s: fix missing HID supplies Add the missing HID supplies to avoid relying on other consumers to keep them on. This also avoids the following warnings on boot: i2c_hid_of 0-0010: supply vdd not found, using dummy regulator i2c_hid_of 0-0010: supply vddl not found, using dummy regulator i2c_hid_of 1-0015: supply vdd not found, using dummy regulator i2c_hid_of 1-002c: supply vdd not found, using dummy regulator i2c_hid_of 1-0015: supply vddl not found, using dummy regulator i2c_hid_of 1-002c: supply vddl not found, using dummy regulator i2c_hid_of 1-003a: supply vdd not found, using dummy regulator i2c_hid_of 1-003a: supply vddl not found, using dummy regulator Note that VCC3B is also used for things like the modem which are not yet described so mark the regulator as always-on for now. Fixes: 7d1cbe2f4985 ("arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6") Cc: stable@vger.kernel.org # 6.12 Reviewed-by: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250314145440.11371-9-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 160c052db1ec..962fb050c55c 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "x1e80100.dtsi" @@ -169,6 +170,23 @@ vreg_edp_3p3: regulator-edp-3p3 { regulator-boot-on; }; + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VCC3B"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -692,6 +710,9 @@ touchpad@15 { hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + wakeup-source; }; @@ -703,6 +724,9 @@ touchpad@2c { hid-descr-addr = <0x20>; interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + wakeup-source; }; @@ -714,6 +738,9 @@ keyboard@3a { hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_1p8>; + pinctrl-0 = <&kybd_default>; pinctrl-names = "default"; @@ -896,6 +923,9 @@ touchscreen@10 { hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_1p8>; + pinctrl-0 = <&ts0_default>; pinctrl-names = "default"; }; @@ -1037,6 +1067,19 @@ usb0_3p3_reg_en: usb0-3p3-reg-en-state { }; }; +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + drive-push-pull; + input-disable; + output-enable; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + &pm8550ve_9_gpios { usb0_1p8_reg_en: usb0-1p8-reg-en-state { pins = "gpio8"; From d40da533a701ef9e22f89e5ceee1ab48150daa30 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 6 Feb 2025 15:43:21 +0530 Subject: [PATCH 171/308] arm64: dts: qcom: qcm6490-idp: Update protected clocks list Certain clocks are not accessible on QCM6490-IDP board, thus mark them as protected. Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20250206-protected_clock_qcm6490-v1-1-5923e8c47ab5@quicinc.com [bjorn: Fix node sort order] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index f26c5c2fde6b..4e5176176860 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -507,6 +507,27 @@ vreg_bob_3p296: bob { }; }; +&gcc { + protected-clocks = ,, + , , + , , + , , + , , + , , + ,, + , , + , + , , + , , + , , + , , + , , + , , + , , + , , + , ; +}; + &gpu { status = "okay"; }; From 4f4c905e6a2a4e884f4e9b7326c94fac3500e0f9 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Fri, 7 Feb 2025 13:05:45 +0530 Subject: [PATCH 172/308] arm64: dts: qcom: ipq9574: Fix USB vdd info USB phys in ipq9574 use the 'L5' regulator. The commit ec4f047679d5 ("arm64: dts: qcom: ipq9574: Enable USB") incorrectly specified it as 'L2'. Because of this when the phy module turns off/on its regulators, the wrong regulator is turned off/on resulting in 2 issues, namely the correct regulator related to the USB phy is not turned off/on and the module powered by the incorrect regulator is affected. Fixes: ec4f047679d5 ("arm64: dts: qcom: ipq9574: Enable USB") Signed-off-by: Varadarajan Narayanan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250207073545.1768990-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index 140e989712b2..bdb396afb992 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -111,6 +111,13 @@ mp5496_l2: l2 { regulator-always-on; regulator-boot-on; }; + + mp5496_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; }; }; @@ -190,7 +197,7 @@ &usb_0_dwc3 { }; &usb_0_qmpphy { - vdda-pll-supply = <&mp5496_l2>; + vdda-pll-supply = <&mp5496_l5>; vdda-phy-supply = <®ulator_fixed_0p925>; status = "okay"; @@ -198,7 +205,7 @@ &usb_0_qmpphy { &usb_0_qusbphy { vdd-supply = <®ulator_fixed_0p925>; - vdda-pll-supply = <&mp5496_l2>; + vdda-pll-supply = <&mp5496_l5>; vdda-phy-dpdm-supply = <®ulator_fixed_3p3>; status = "okay"; From d4da3adfc560fcb55578f8564d9f5a972507b118 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Sun, 9 Feb 2025 04:21:42 +0530 Subject: [PATCH 173/308] arm64: dts: qcom: sc7280: Add support for camss Add changes to support the camera subsystem on the SC7280. Signed-off-by: Suresh Vankadara Signed-off-by: Trishansh Bhardwaj Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Vikram Sharma Acked-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250208225143.2868279-2-quic_vikramsa@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 178 +++++++++++++++++++++++++++ 1 file changed, 178 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 31abb2b9555f..ec96c917b56b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4422,6 +4422,184 @@ cci1_i2c1: i2c-bus@1 { }; }; + camss: isp@acb3000 { + compatible = "qcom,sc7280-camss"; + + reg = <0x0 0x0acb3000 0x0 0x1000>, + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc1000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0accf000 0x0 0x1000>, + <0x0 0x0ace0000 0x0 0x2000>, + <0x0 0x0ace2000 0x0 0x2000>, + <0x0 0x0ace4000 0x0 0x2000>, + <0x0 0x0ace6000 0x0 0x2000>, + <0x0 0x0ace8000 0x0 0x2000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acbd000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0accb000 0x0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_axi", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1", + "vfe1_axi", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2", + "vfe2_axi", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe_lite0", + "vfe_lite0_cphy_rx", + "vfe_lite0_csid", + "vfe_lite1", + "vfe_lite1_cphy_rx", + "vfe_lite1_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0"; + + iommus = <&apps_smmu 0x800 0x4e0>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc7280-camcc"; reg = <0 0x0ad00000 0 0x10000>; From 39e6ca14ace9d138e40ddd42313c2649a6f3e69f Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Sun, 9 Feb 2025 04:21:43 +0530 Subject: [PATCH 174/308] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine The Vision Mezzanine for the Qualcomm RB3 Gen 2 ships with an imx577 camera sensor. Enable IMX577 on the vision mezzanine. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -V '"imx577 '17-001a'":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy3":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy3":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0 Signed-off-by: Hariram Purushothaman Signed-off-by: Trishansh Bhardwaj Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Vikram Sharma Acked-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250208225143.2868279-3-quic_vikramsa@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../qcs6490-rb3gen2-vision-mezzanine.dtso | 89 +++++++++++++++++++ 2 files changed, 93 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7c07eb0c0664..adb4d026bcc4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -116,6 +116,10 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb + +qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso new file mode 100644 index 000000000000..b9e4a5214f70 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* + * Camera Sensor overlay on top of rb3gen2 core kit. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* The port index denotes CSIPHY id i.e. csiphy3 */ + port@3 { + reg = <3>; + + csiphy3_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + + reg = <0x1a>; + + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "suspend"; + pinctrl-0 = <&cam2_default>; + pinctrl-1 = <&cam2_suspend>; + + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + + dovdd-supply = <&vreg_l18b_1p8>; + avdd-supply = <&vph_pwr>; + dvdd-supply = <&vph_pwr>; + + port { + imx577_ep: endpoint { + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + +&tlmm { + cam2_default: cam2-default-state { + pins = "gpio67"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam2_suspend: cam2-suspend-state { + pins = "gpio67"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; +}; From 300edf73651b1151b18c0ef4b90cdf71946787f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Mon, 17 Feb 2025 23:05:21 +0100 Subject: [PATCH 175/308] ARM: dts: qcom: msm8226: Add node for TCSR halt regs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a syscon device node for the TCSR halt regs needed by modem and other remoteprocs. Signed-off-by: Matti Lehtimäki Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250217-msm8226-modem-v5-7-2bc74b80e0ae@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 64c8ac94f352..caaeeadf289f 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -851,6 +851,11 @@ tcsr_mutex: hwlock@fd484000 { #hwlock-cells = <1>; }; + tcsr_regs_1: syscon@fd485000 { + compatible = "qcom,tcsr-msm8226", "syscon"; + reg = <0xfd485000 0x1000>; + }; + tlmm: pinctrl@fd510000 { compatible = "qcom,msm8226-pinctrl"; reg = <0xfd510000 0x4000>; From 184cb65984ca164e4adb3abe3ec1549ed358d1bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Mon, 17 Feb 2025 23:05:22 +0100 Subject: [PATCH 176/308] ARM: dts: qcom: msm8226: Add smsm node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add smsm node for remoteproc cores. Reviewed-by: Stephan Gerhold Signed-off-by: Matti Lehtimäki Co-developed-by: Luca Weiss Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250217-msm8226-modem-v5-8-2bc74b80e0ae@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index caaeeadf289f..7e0838af6c2d 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -253,6 +253,40 @@ adsp_smp2p_in: slave-kernel { }; }; + smsm { + compatible = "qcom,smsm"; + #address-cells = <1>; + #size-cells = <0>; + + mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; + }; + + modem_smsm: modem@1 { + reg = <1>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + }; + + adsp_smsm: adsp@2 { + reg = <2>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@7 { + reg = <7>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; From 075555387244b51d9414a35d3b1d9f58a4df0fe3 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 17 Feb 2025 23:05:23 +0100 Subject: [PATCH 177/308] ARM: dts: qcom: msm8226: Add modem remoteproc node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a node for the modem remoteproc found on MSM8226. Co-developed-by: Matti Lehtimäki Signed-off-by: Matti Lehtimäki Reviewed-by: Stephan Gerhold Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250217-msm8226-modem-v5-9-2bc74b80e0ae@lucaweiss.eu Signed-off-by: Bjorn Andersson --- .../qcom/qcom-apq8026-samsung-milletwifi.dts | 2 + .../qcom-msm8226-samsung-matisse-common.dtsi | 6 +- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 90 +++++++++++++++++++ .../boot/dts/qcom/qcom-msm8926-htc-memul.dts | 2 + 4 files changed, 98 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts index 7d519156d91d..a8543ca7b556 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts @@ -12,6 +12,8 @@ #include "pm8226.dtsi" /delete-node/ &adsp_region; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; /delete-node/ &smem_region; / { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi index a15a44fc0181..fbd568c7d6b7 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi @@ -8,6 +8,8 @@ #include "pm8226.dtsi" /delete-node/ &adsp_region; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; /delete-node/ &smem_region; / { @@ -145,12 +147,12 @@ framebuffer@3200000 { no-map; }; - mpss@8400000 { + mpss_region: mpss@8400000 { reg = <0x08400000 0x1f00000>; no-map; }; - mba@a300000 { + mba_region: mba@a300000 { reg = <0x0a300000 0x100000>; no-map; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 7e0838af6c2d..662911f4cf16 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -213,6 +213,18 @@ smem_region: smem@3000000 { no-map; }; + mpss_region: mpss@8000000 { + reg = <0x08000000 0x5100000>; + no-map; + status = "disabled"; + }; + + mba_region: mba@d100000 { + reg = <0x0d100000 0x100000>; + no-map; + status = "disabled"; + }; + adsp_region: adsp@dc00000 { reg = <0x0dc00000 0x1900000>; no-map; @@ -253,6 +265,31 @@ adsp_smp2p_in: slave-kernel { }; }; + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smsm { compatible = "qcom,smsm"; #address-cells = <1>; @@ -879,6 +916,59 @@ spmi_bus: spmi@fc4cf000 { #interrupt-cells = <4>; }; + modem: remoteproc@fc880000 { + compatible = "qcom,msm8226-mss-pil"; + reg = <0xfc880000 0x4040>, + <0xfc820000 0x10000>; + reg-names = "qdsp6", + "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "bus", + "mem", + "xo"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + power-domains = <&rpmpd MSM8226_VDDCX>; + power-domain-names = "cx"; + + qcom,ext-bhs-reg = <&tcsr_regs_1 0x194>; + qcom,halt-regs = <&tcsr_regs_1 0x180 0x200 0x280>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + memory-region = <&mba_region>, <&mpss_region>; + + status = "disabled"; + + smd-edge { + interrupts = ; + + mboxes = <&apcs 12>; + qcom,smd-edge = <0>; + + label = "modem"; + }; + }; + tcsr_mutex: hwlock@fd484000 { compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; reg = <0xfd484000 0x1000>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts index 3037344eb240..18396623a91d 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts @@ -9,6 +9,8 @@ #include "pm8226.dtsi" /delete-node/ &adsp_region; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; /delete-node/ &smem_region; / { From 6b47ce06f22b3ad2921dda442be23abbe93ed251 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 17 Feb 2025 23:05:24 +0100 Subject: [PATCH 178/308] ARM: dts: qcom: msm8226: Add BAM DMUX Ethernet/IP device BAM DMUX is used as the network interface to the modem. Reviewed-by: Stephan Gerhold Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250217-msm8226-modem-v5-10-2bc74b80e0ae@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 662911f4cf16..32defb08b909 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -916,6 +916,18 @@ spmi_bus: spmi@fc4cf000 { #interrupt-cells = <4>; }; + bam_dmux_dma: dma-controller@fc834000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xfc834000 0x7000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + }; + modem: remoteproc@fc880000 { compatible = "qcom,msm8226-mss-pil"; reg = <0xfc880000 0x4040>, @@ -959,6 +971,20 @@ modem: remoteproc@fc880000 { status = "disabled"; + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupt-parent = <&modem_smsm>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + }; + smd-edge { interrupts = ; From fc532eb25c0aeca1d20e7d3c8d8a24b3ff39e3a9 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 17 Feb 2025 23:05:25 +0100 Subject: [PATCH 179/308] ARM: dts: qcom: Introduce dtsi for LTE-capable MSM8926 MSM8926, while being 'just' an LTE-capable variant of MSM8226, the dts needs to slightly change since the modem doesn't use the ext-bhs-reg and needs mss-supply, therefore it gets a new compatible. Since we already have two -common.dtsi files which are used on both APQ8026/MSM8226 and MSM8926 devices, change the setup a bit by removing the SoC include from those and requiring the device dts to pick the correct one. Reviewed-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250217-msm8226-modem-v5-11-2bc74b80e0ae@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/msm8926.dtsi | 11 +++++++++++ .../dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts | 1 + .../boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi | 6 +++++- .../boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts | 1 + .../dts/qcom/qcom-msm8226-microsoft-makepeace.dts | 1 + .../dts/qcom/qcom-msm8226-microsoft-moneypenny.dts | 1 + .../dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi | 6 +++++- arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts | 2 +- .../dts/qcom/qcom-msm8926-microsoft-superman-lte.dts | 1 + .../boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts | 1 + .../boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts | 2 +- .../boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts | 1 + 12 files changed, 30 insertions(+), 4 deletions(-) create mode 100644 arch/arm/boot/dts/qcom/msm8926.dtsi diff --git a/arch/arm/boot/dts/qcom/msm8926.dtsi b/arch/arm/boot/dts/qcom/msm8926.dtsi new file mode 100644 index 000000000000..629654c525b4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8926.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +#include "qcom-msm8226.dtsi" + +&modem { + compatible = "qcom,msm8926-mss-pil"; + /delete-property/ qcom,ext-bhs-reg; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts index da3be658e822..4546fa8beba4 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-samsung-matisse-common.dtsi" / { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi index ca76bf8af75e..d4a32af0ef8f 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi @@ -8,7 +8,11 @@ * Copyright (c) 2023, Rayyan Ansari */ -#include "qcom-msm8226.dtsi" +/* + * The .dts should first include qcom-msm8226.dtsi or msm8926.dtsi depending on + * the SoC on the given device. + */ + #include "pm8226.dtsi" #include diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts index 2c664b5934ec..f448c9088416 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" / { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts index 731c5c375678..94bf3b1ad1bd 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" / { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts index a28a83cb5340..d8cdb75dfbb8 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" /* This device has no magnetometer */ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi index fbd568c7d6b7..0a3147656f36 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi @@ -3,8 +3,12 @@ * Copyright (c) 2022, Matti Lehtimäki */ +/* + * The .dts should first include qcom-msm8226.dtsi or msm8926.dtsi depending on + * the SoC on the given device. + */ + #include -#include "qcom-msm8226.dtsi" #include "pm8226.dtsi" /delete-node/ &adsp_region; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts index 18396623a91d..d6eaa82cee4d 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts @@ -5,7 +5,7 @@ /dts-v1/; -#include "qcom-msm8226.dtsi" +#include "msm8926.dtsi" #include "pm8226.dtsi" /delete-node/ &adsp_region; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts index 9b48661d69c5..eea4fd8cd972 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "msm8926.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" /* This device has touchscreen on i2c3 instead */ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts index 55077a5f2e34..f23bbb94cc5e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "msm8926.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" /* This device has touchscreen on i2c1 instead */ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts index 376a33125941..db3273c755c2 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "qcom-msm8226.dtsi" +#include "msm8926.dtsi" #include "pm8226.dtsi" /delete-node/ &smem_region; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts index d0e1bc39f8ef..772827cad972 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include "msm8926.dtsi" #include "qcom-msm8226-samsung-matisse-common.dtsi" / { From 36663812eeb5e57f1d167c33bcb1dc970333bef1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 17 Feb 2025 23:05:26 +0100 Subject: [PATCH 180/308] ARM: dts: qcom: msm8926-htc-memul: Enable modem Enable the modem found on the MSM8926 HTC One Mini 2. Reviewed-by: Stephan Gerhold Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250217-msm8226-modem-v5-12-2bc74b80e0ae@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts index d6eaa82cee4d..cb571aa13c11 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts @@ -195,6 +195,16 @@ &blsp1_i2c6 { /* TPS61310 Flash/Torch @ 33 */ }; +&modem { + mx-supply = <&pm8226_l3>; + pll-supply = <&pm8226_l8>; + mss-supply = <&pm8226_s5>; + + firmware-name = "qcom/msm8926/memul/mba.b00", "qcom/msm8926/memul/modem.mdt"; + + status = "okay"; +}; + &pm8226_vib { status = "okay"; }; From 32768db9cfc56554d1570ac71aa204f0751bd12e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matti=20Lehtim=C3=A4ki?= Date: Mon, 17 Feb 2025 23:05:27 +0100 Subject: [PATCH 181/308] ARM: dts: qcom: msm8226-samsung-matisse-common: Enable modem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable modem remoteproc on samsung,matisse-wifi & matisselte. The mattisselte - being msm8926 - requires an extra mss-supply, so add that as well. Signed-off-by: Matti Lehtimäki Reviewed-by: Stephan Gerhold Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250217-msm8226-modem-v5-13-2bc74b80e0ae@lucaweiss.eu Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi | 7 +++++++ arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi index 0a3147656f36..f1544a7e8369 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi @@ -229,6 +229,13 @@ &blsp1_uart3 { status = "okay"; }; +&modem { + mx-supply = <&pm8226_l3>; + pll-supply = <&pm8226_l8>; + + status = "okay"; +}; + &rpm_requests { regulators { compatible = "qcom,rpm-pm8226-regulators"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts index 772827cad972..73e19176eb97 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts @@ -28,6 +28,10 @@ reg_tsp_3p3v: regulator-tsp-3p3v { }; }; +&modem { + mss-supply = <&pm8226_s5>; +}; + &tlmm { tsp_en1_default_state: tsp-en1-default-state { pins = "gpio32"; From 27b85be287f96180de2499b981eec83850df0da9 Mon Sep 17 00:00:00 2001 From: Eugene Lepshy Date: Tue, 18 Feb 2025 01:24:31 +0300 Subject: [PATCH 182/308] arm64: dts: qcom: sm7325-nothing-spacewar: Enable panel and GPU Enable the Adreno GPU and configure the Visionox RM692E5 panel. Signed-off-by: Eugene Lepshy Co-developed-by: Danila Tikhonov Signed-off-by: Danila Tikhonov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250217222431.82522-5-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm7325-nothing-spacewar.dts | 51 ++++++++++++++++++- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts index 0c89f7726865..85a928f98077 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -908,6 +908,10 @@ &gpi_dma1 { status = "okay"; }; +&gpu { + status = "okay"; +}; + &gpu_zap_shader { firmware-name = "qcom/sm7325/nothing/spacewar/a660_zap.mbn"; }; @@ -974,15 +978,44 @@ &ipa { status = "okay"; }; -/* MDSS remains disabled until the panel driver is present. */ +&mdss { + status = "okay"; +}; + &mdss_dsi { vdda-supply = <&vdd_a_dsi_0_1p2>; + status = "okay"; - /* Visionox RM692E5 panel */ + panel: panel@0 { + compatible = "nothing,rm692e5-spacewar", + "visionox,rm692e5"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; + + vdd-supply = <&vdd_oled>; + vddio-supply = <&vdd_io_oled>; + + pinctrl-0 = <&lcd_reset_n>, + <&mdp_vsync_p>; + pinctrl-names = "default"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; }; &mdss_dsi_phy { vdds-supply = <&vdd_a_dsi_0_0p9>; + status = "okay"; }; &pm7325_gpios { @@ -1298,6 +1331,20 @@ nfc_int_req: nfc-int-req-state { bias-pull-down; }; + lcd_reset_n: lcd-reset-n-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mdp_vsync_p: mdp-vsync-p-state { + pins = "gpio80"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + hst_bt_en: hst-bt-en-state { pins = "gpio85"; function = "gpio"; From 4bf9fac3a85b90002de373b2f067864d837bac31 Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Mon, 20 Jan 2025 12:15:08 +0530 Subject: [PATCH 183/308] arm64: dts: qcom: ipq5424: enable GPIO based LEDs and Buttons Add support for wlan-2g LED on GPIO 42 and wps buttons on GPIO 19. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250120064508.2722341-1-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 43 +++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index b9752e8d579e..0fd0ebe0251d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include +#include #include "ipq5424.dtsi" / { @@ -17,6 +19,33 @@ aliases { serial0 = &uart1; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&tlmm 19 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&gpio_leds_default>; + pinctrl-names = "default"; + + led-0 { + color = ; + function = LED_FUNCTION_WLAN; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; + vreg_misc_3p3: regulator-usb-3p3 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; @@ -102,6 +131,20 @@ &ssphy_0 { }; &tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio19"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + gpio_leds_default: gpio-leds-default-state { + pins = "gpio42"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + spi0_default_state: spi0-default-state { clk-pins { pins = "gpio6"; From c0c46eea2444dcd78400bfa6b264f59dd55aaf42 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Sun, 19 Jan 2025 15:50:51 +0100 Subject: [PATCH 184/308] arm64: dts: qcom: x1e80100-vivobook-s15: Enable USB-A ports The asus vivobook has 2 USB type A ports on the right side, enable them Signed-off-by: Maud Spierings Link: https://lore.kernel.org/r/20250119-usb_a_micro_sd-v1-1-01eb7502ae05@hotmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/x1e80100-asus-vivobook-s15.dts | 103 +++++++++++++++++- 1 file changed, 102 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index 53781f9b13af..b66d03ee3ff3 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -192,6 +192,20 @@ vreg_l2b_3p0: ldo2 { regulator-initial-mode = ; }; + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + vreg_l14b_3p0: ldo14 { regulator-name = "vreg_l14b_3p0"; regulator-min-microvolt = <3072000>; @@ -209,6 +223,13 @@ regulators-1 { vdd-l3-supply = <&vreg_s1f_0p7>; vdd-s4-supply = <&vph_pwr>; + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + vreg_s4c_1p8: smps4 { regulator-name = "vreg_s4c_1p8"; regulator-min-microvolt = <1856000>; @@ -401,7 +422,35 @@ keyboard@3a { wakeup-source; }; - /* EC? @ 0x5b, 0x76 */ + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; + + /* EC @ 0x76 */ }; &i2c7 { @@ -563,6 +612,22 @@ edp_reg_en: edp-reg-en-state { bias-disable; }; + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + hall_int_n_default: hall-int-n-state { pins = "gpio92"; function = "gpio"; @@ -698,3 +763,39 @@ &usb_1_ss1_dwc3_hs { &usb_1_ss1_qmpphy_out { remote-endpoint = <&pmic_glink_ss1_ss_in>; }; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; From 1fcbbdc0806219153dd0761999ca4bf47d164787 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Sun, 19 Jan 2025 15:50:52 +0100 Subject: [PATCH 185/308] arm64: dts: qcom: x1e80100-vivobook-s15: Enable micro-sd card reader The asus vivobook s15 has a micro-sd card reader attached to usb_2. Enable usb_2 to enable this reader. Signed-off-by: Maud Spierings Link: https://lore.kernel.org/r/20250119-usb_a_micro_sd-v1-2-01eb7502ae05@hotmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/x1e80100-asus-vivobook-s15.dts | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index b66d03ee3ff3..fb9567817be6 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -422,6 +422,20 @@ keyboard@3a { wakeup-source; }; + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + eusb3_repeater: redriver@47 { compatible = "nxp,ptn3222"; reg = <0x47>; @@ -620,6 +634,14 @@ eusb3_reset_n: eusb3-reset-n-state { output-low; }; + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + eusb6_reset_n: eusb6-reset-n-state { pins = "gpio184"; function = "gpio"; @@ -764,6 +786,23 @@ &usb_1_ss1_qmpphy_out { remote-endpoint = <&pmic_glink_ss1_ss_in>; }; +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + &usb_mp { status = "okay"; }; From 54040a3e3da67ef0e014e5f04f9f3fe680fc4b55 Mon Sep 17 00:00:00 2001 From: Tingguo Cheng Date: Fri, 17 Jan 2025 11:24:31 +0800 Subject: [PATCH 186/308] arm64: dts: qcom: qcs615: remove disallowed property in spmi bus node Remove the unevaluated 'cell-index' property from qcs615-ride.dtb spmi@c440000 to fix the Devicetree validation error reported by the kernel test robot. Reported-by: kernel test robot Closes: https://lore.kernel.org/r/202412272210.GpGmqcPC-lkp@intel.com/ Fixes: 27554e2bef4d ("arm64: dts: qcom: qcs615: Adds SPMI support") Signed-off-by: Tingguo Cheng Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250117-fix-kernel-test-robot-unexpected-property-issue-v2-1-0b68cf481249@quicinc.com [bjorn: Fixes commit message wording about LKP] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 1627110bcfc9..edfb796d8dd3 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3315,7 +3315,6 @@ spmi_bus: spmi@c440000 { #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <0>; - cell-index = <0>; qcom,channel = <0>; qcom,ee = <0>; }; From cc13a858a79d8c5798a99e8cde677ea36272a5a0 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 17 Jan 2025 16:35:54 +0530 Subject: [PATCH 187/308] arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node Add LMH interrupts for cpufreq_hw node to indicate if there is any thermal throttle. Signed-off-by: Jagadeesh Kona Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250117-sa8775p-lmh-interrupts-v1-1-bae549f0bfe8@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 581dac8556ec..a904960359d7 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4804,6 +4804,10 @@ cpufreq_hw: cpufreq@18591000 { <0x0 0x18593000 0x0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; From f5b7564fedcfd32df68d56781b9d7698343f8fbf Mon Sep 17 00:00:00 2001 From: Ivan Belokobylskiy Date: Sun, 16 Mar 2025 23:16:55 +0100 Subject: [PATCH 188/308] ARM: dts: qcom: Initial dts for LG Nexus 4 Add initial support for LG Nexus 4 (mako). Features currently working: regulators, eMMC, and volume keys. Signed-off-by: Ivan Belokobylskiy Co-developed-by: David Heidelberg Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250316-lg-nexus4-mako-v5-1-79feae815a85@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + .../dts/qcom/qcom-apq8064-lg-nexus4-mako.dts | 341 ++++++++++++++++++ 2 files changed, 342 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index f06c6d425e91..0c1d116f6e84 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8064-ifc6410.dtb \ qcom-apq8064-sony-xperia-lagan-yuga.dtb \ qcom-apq8064-asus-nexus7-flo.dtb \ + qcom-apq8064-lg-nexus4-mako.dtb \ qcom-apq8074-dragonboard.dtb \ qcom-apq8084-ifc6540.dtb \ qcom-apq8084-mtp.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts new file mode 100644 index 000000000000..5710450faabf --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include + +#include "qcom-apq8064-v2.0.dtsi" +#include "pm8821.dtsi" +#include "pm8921.dtsi" + +/ { + model = "LG Nexus 4 (mako)"; + compatible = "lg,nexus4-mako", "qcom,apq8064"; + chassis-type = "handset"; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi6_serial; + serial2 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + battery_cell: battery-cell { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <900000>; + operating-range-celsius = <0 45>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@88d00000{ + compatible = "ramoops"; + reg = <0x88d00000 0x100000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + }; + }; +}; + +&gsbi1 { + qcom,mode = ; + + status = "okay"; +}; + +&gsbi1_i2c { + clock-frequency = <200000>; + + status = "okay"; +}; + +&gsbi4 { + qcom,mode = ; + + status = "okay"; +}; + +&gsbi4_serial { + status = "okay"; +}; + +&pm8821 { + interrupts-extended = <&tlmm_pinmux 76 IRQ_TYPE_LEVEL_LOW>; +}; + +&pm8921 { + interrupts-extended = <&tlmm_pinmux 74 IRQ_TYPE_LEVEL_LOW>; +}; + +&pm8921_keypad { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 1, KEY_VOLUMEUP) + >; + + keypad,num-rows = <1>; + keypad,num-columns = <5>; + + status = "okay"; +}; + +&rpm { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + pm8921_l1: l1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + bias-pull-down; + }; + + /* mipi_dsi.1-dsi1_pll_vdda */ + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + /* msm_otg-HSUSB_3p3 */ + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3500000>; + bias-pull-down; + }; + + /* msm_otg-HSUSB_1p8 */ + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* msm_sdcc.1-sdc_vdd */ + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + /* earjack_debug */ + pm8921_l6: l6 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + /* mipi_dsi.1-dsi_vci */ + pm8921_l8: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + /* wcnss_wlan.0-iris_vddpa */ + pm8921_l10: l10 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + bias-pull-down; + }; + + /* mipi_dsi.1-dsi1_avdd */ + pm8921_l11: l11 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + /* touch_vdd */ + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + /* slimport_dvdd */ + pm8921_l18: l18 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + bias-pull-down; + }; + + /* touch_io */ + pm8921_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + /* + * mipi_dsi.1-dsi_vddio + * pil_qdsp6v4.1-pll_vdd + * pil_qdsp6v4.2-pll_vdd + * msm_ehci_host.0-HSUSB_1p8 + * msm_ehci_host.1-HSUSB_1p8 + */ + pm8921_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + /* + * tabla2x-slim-CDC_VDDA_A_1P2V + * tabla2x-slim-VDDD_CDC_D + */ + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + bias-pull-down; + }; + + pm8921_l26: l26 { + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + bias-pull-down; + }; + + pm8921_l27: l27 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + pm8921_l28: l28 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + /* wcnss_wlan.0-iris_vddio */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + /* wcnss_wlan.0-iris_vdddig */ + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + /* mipi_dsi.1-dsi_iovcc */ + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + /* + * pil_riva-pll_vdd + * lvds.0-lvds_vdda + * mipi_dsi.1-dsi1_vddio + * hdmi_msm.0-hdmi_vdda + */ + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* msm otg HSUSB_VDDCX */ + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + /* + * msm_sdcc.1-sdc-vdd_io + * tabla2x-slim-CDC_VDDA_RX + * tabla2x-slim-CDC_VDDA_TX + * tabla2x-slim-CDC_VDD_CP + * tabla2x-slim-VDDIO_CDC + */ + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = ; + }; + + /* + * supply vdd_l26, vdd_l27, vdd_l28 + */ + pm8921_s7: s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_s8: s8 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +/* eMMC */ +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + + status = "okay"; +}; From 9bb5ca464100e7c8f2d740148088f60e04fed8ed Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 14 Mar 2025 09:21:16 +0100 Subject: [PATCH 189/308] arm64: dts: qcom: sm8650: Fix domain-idle-state for CPU2 On SM8650 the CPUs 0-1 are "silver" (Cortex-A520), CPU 2-6 are "gold" (Cortex-A720) and CPU 7 is "gold-plus" (Cortex-X4). So reference the correct "gold" idle-state for CPU core 2. Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250314-sm8650-cpu2-sleep-v1-1-31d5c7c87a5d@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 90917f9f9c5c..818db6ba3b3b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -1608,7 +1608,7 @@ cpu_pd1: power-domain-cpu1 { cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; - domain-idle-states = <&silver_cpu_sleep_0>; + domain-idle-states = <&gold_cpu_sleep_0>; }; cpu_pd3: power-domain-cpu3 { From 409803681a55e061f5ea6be82f05f14c0b9c707e Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 19 Feb 2025 14:41:17 +0100 Subject: [PATCH 190/308] arm64: dts: qcom: sc8280xp-x13s: switch to uefi rtc offset On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which a driver can take into account. Switch to using the Qualcomm specific UEFI variable that is used by the UEFI firmware (and Windows) to store the RTC offset. This specifically means that the RTC time will be synchronised between the UEFI firmware setup (or UEFI shell), Windows and Linux. Note however that Windows stores the RTC time in local time by default, while Linux typically uses UTC (i.e. as on X86). Tested-by: Jens Glathe Tested-by: Steev Klimaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250219134118.31017-6-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 3053e17731fe..d36fc1ebe50e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1090,20 +1090,9 @@ &pmk8280_pon_resin { }; &pmk8280_rtc { - nvmem-cells = <&rtc_offset>; - nvmem-cell-names = "offset"; - status = "okay"; }; -&pmk8280_sdam_6 { - status = "okay"; - - rtc_offset: rtc-offset@bc { - reg = <0xbc 0x4>; - }; -}; - &pmk8280_vadc { channel@144 { reg = ; From b53c2c23d3c2e50473c0be17a392d4b03a296b52 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 19 Feb 2025 14:41:18 +0100 Subject: [PATCH 191/308] arm64: dts: qcom: x1e80100: enable rtc On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which a driver can take into account. On X1E based Windows on Arm machines the offset is stored in a Qualcomm specific UEFI variable. Unlike on previous platforms the alarm registers are also unaccessible on X1E as they are owned by the ADSP. Assume all X1E machines use similar firmware and enable the RTC in the PMIC dtsi for now. Based on a patch by Jonathan Marek. [1] Link: https://lore.kernel.org/r/20241015004945.3676-4-jonathan@marek.ca # [1] Tested-by: Jens Glathe Tested-by: Joel Stanley Tested-by: Sebastian Reichel # Lenovo T14s Gen6 Reviewed-by: Konrad Dybcio Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250219134118.31017-7-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi index bf6cdede156b..c02fd4d15c96 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -223,8 +223,7 @@ pmk8550_rtc: rtc@6100 { reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; - /* Not yet sure what blocks access */ - status = "reserved"; + qcom,no-alarm; /* alarm owned by ADSP */ }; pmk8550_sdam_2: nvram@7100 { From 6464510651e8402cfb2dfa1ff9c30a6a1b11219a Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Thu, 13 Mar 2025 16:33:58 +0530 Subject: [PATCH 192/308] arm64: dts: qcom: ipq9574: Add nsscc node Add a node for the nss clock controller found on ipq9574 based devices. Reviewed-by: Konrad Dybcio Signed-off-by: Devi Priya Signed-off-by: Manikanta Mylavarapu Link: https://lore.kernel.org/r/20250313110359.242491-6-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 769705d398c4..db69bff41afa 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -1222,6 +1222,35 @@ pcie0: pci@28000000 { status = "disabled"; }; + nsscc: clock-controller@39b00000 { + compatible = "qcom,ipq9574-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&xo_board_clk>, + <&cmn_pll NSS_1200MHZ_CLK>, + <&cmn_pll PPE_353MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_NSSCC_CLK>; + clock-names = "xo", + "nss_1200", + "ppe_353", + "gpll0_out", + "uniphy0_rx", + "uniphy0_tx", + "uniphy1_rx", + "uniphy1_tx", + "uniphy2_rx", + "uniphy2_tx", + "bus"; + #clock-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; }; thermal-zones { From bba4e13c0f337df4cab3d65ccdb5524eb81a00bf Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Mon, 17 Mar 2025 18:08:41 +0530 Subject: [PATCH 193/308] arm64: dts: qcom: qcs8300: Add RPMh sleep stats Add RPMh stats to read low power statistics for various subsystem and SoC sleep modes. Signed-off-by: Maulik Shah Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250317-add_qcom_stats-v1-1-016ae05ac4b0@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 72d4f9e382da..037cd366a09b 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -4301,6 +4301,11 @@ IPCC_MPROC_SIGNAL_GLINK_QMP #clock-cells = <0>; }; + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c3f0000 0x0 0x400>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x1100>, From 1a7646d784513dcf0e8b16c1d9124ef54b4ec5e0 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 18 Mar 2025 08:49:07 +0100 Subject: [PATCH 194/308] arm64: dts: qcom: x1e001de-devkit: fix USB retimer reset polarity The ps8830 retimer reset is active low. Fix up the retimer nodes which were based on an early version of the driver which inverted the polarity. Fixes: 019e1ee32fec ("arm64: dts: qcom: x1e001de-devkit: Enable external DP support") Cc: Sibi Sankar Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20250318074907.13903-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index b133302bf846..74911861a3bf 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -787,7 +787,7 @@ typec-mux@8 { vddat-supply = <&vreg_rtmr2_1p15>; vddio-supply = <&vreg_rtmr2_1p8>; - reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>; orientation-switch; retimer-switch; @@ -841,7 +841,7 @@ typec-mux@8 { vddat-supply = <&vreg_rtmr0_1p15>; vddio-supply = <&vreg_rtmr0_1p8>; - reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; retimer-switch; orientation-switch; @@ -895,7 +895,7 @@ typec-mux@8 { vddat-supply = <&vreg_rtmr1_1p15>; vddio-supply = <&vreg_rtmr1_1p8>; - reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; retimer-switch; orientation-switch; From 651af46f33ab284400e0fc307e5a81de54c75945 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:00 +0200 Subject: [PATCH 195/308] arm64: dts: qcom: msm8916: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-3-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8f35c9af1878..c89f9e92e832 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -1497,8 +1498,8 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; clocks = <&xo_board>, <&sleep_clk>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <0>, <0>, <0>; @@ -1590,8 +1591,8 @@ mdss_dsi0: dsi@1a98000 { assigned-clocks = <&gcc BYTE0_CLK_SRC>, <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AHB_CLK>, From 7c92da246e1a6933f25fa015d6c43a6bcfb2c7b3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:01 +0200 Subject: [PATCH 196/308] arm64: dts: qcom: msm8917: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-4-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8917.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qcom/msm8917.dtsi index 9d8358745c91..8a642fce2e40 100644 --- a/arch/arm64/boot/dts/qcom/msm8917.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only +#include #include #include #include @@ -961,8 +962,8 @@ gcc: clock-controller@1800000 { #power-domain-cells = <1>; clocks = <&xo_board>, <&sleep_clk>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>; + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; clock-names = "xo", "sleep_clk", "dsi0pll", @@ -1051,8 +1052,8 @@ mdss_dsi0: dsi@1a94000 { assigned-clocks = <&gcc BYTE0_CLK_SRC>, <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AHB_CLK>, From 011e7f2c26dcb42c255ab54207f548d68c3b8e38 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:02 +0200 Subject: [PATCH 197/308] arm64: dts: qcom: msm8939: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-5-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 7cd5660de1b3..5e8c3ac39de8 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2020-2023, Linaro Limited */ +#include #include #include #include @@ -1172,8 +1173,8 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <0>, <0>, <0>; @@ -1291,8 +1292,8 @@ mdss_dsi0: dsi@1a98000 { "core"; assigned-clocks = <&gcc BYTE0_CLK_SRC>, <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; phys = <&mdss_dsi0_phy>; status = "disabled"; @@ -1360,8 +1361,8 @@ mdss_dsi1: dsi@1aa0000 { "core"; assigned-clocks = <&gcc BYTE1_CLK_SRC>, <&gcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; phys = <&mdss_dsi1_phy>; status = "disabled"; From 8e35fab460cce97e387a2c975db45b762b551521 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:03 +0200 Subject: [PATCH 198/308] arm64: dts: qcom: msm8953: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-6-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index af4c341e2533..4793a60fa946 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -807,10 +808,10 @@ gcc: clock-controller@1800000 { #power-domain-cells = <1>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>; + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; clock-names = "xo", "sleep", "dsi0pll", @@ -917,8 +918,8 @@ mdss_dsi0: dsi@1a94000 { assigned-clocks = <&gcc BYTE0_CLK_SRC>, <&gcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AHB_CLK>, @@ -987,8 +988,8 @@ mdss_dsi1: dsi@1a96000 { assigned-clocks = <&gcc BYTE1_CLK_SRC>, <&gcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; clocks = <&gcc GCC_MDSS_MDP_CLK>, <&gcc GCC_MDSS_AHB_CLK>, From b06f27d09ed455f153d2523f96bbd94ecf6a69d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:04 +0200 Subject: [PATCH 199/308] arm64: dts: qcom: msm8976: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-7-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index d036f31dfdca..e2ac2fd6882f 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2022, Marijn Suijten */ +#include #include #include #include @@ -824,10 +825,10 @@ gcc: clock-controller@1800000 { clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>; + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; clock-names = "xo", "xo_a", "dsi0pll", @@ -970,8 +971,8 @@ mdss_dsi0: dsi@1a94000 { assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>, <&gcc GCC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; phys = <&mdss_dsi0_phy>; @@ -1046,8 +1047,8 @@ mdss_dsi1: dsi@1a96000 { assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>, <&gcc GCC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; phys = <&mdss_dsi1_phy>; From 4b32499da71716e075ea2dba115e3fe8b6f8ed2f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:05 +0200 Subject: [PATCH 200/308] arm64: dts: qcom: msm8996: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-8-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4719e1fc70d2..ede851fbf628 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -937,10 +938,10 @@ mmcc: clock-controller@8c0000 { clocks = <&xo_board>, <&gcc GPLL0>, <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, <&mdss_hdmi_phy>; clock-names = "xo", "gpll0", @@ -1071,8 +1072,10 @@ mdss_dsi0: dsi@994000 { "core_mmss", "pixel", "core"; - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; phys = <&mdss_dsi0_phy>; status = "disabled"; @@ -1139,8 +1142,10 @@ mdss_dsi1: dsi@996000 { "core_mmss", "pixel", "core"; - assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; phys = <&mdss_dsi1_phy>; status = "disabled"; From f4220c41decc1944ef319c859840aa5405eee6fa Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:06 +0200 Subject: [PATCH 201/308] arm64: dts: qcom: msm8998: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-9-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index c2caad85c668..7eca38440cd7 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2,6 +2,7 @@ /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ #include +#include #include #include #include @@ -2790,10 +2791,10 @@ mmcc: clock-controller@c8c0000 { "gpll0_div"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, <&mdss_hdmi_phy 0>, <0>, <0>, @@ -2932,8 +2933,8 @@ mdss_dsi0: dsi@c994000 { "bus"; assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmpd MSM8998_VDDCX>; @@ -3008,8 +3009,8 @@ mdss_dsi1: dsi@c996000 { "bus"; assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmpd MSM8998_VDDCX>; From 48478f726f3793a9d1cf9b10d6487a81ea7e3c73 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:07 +0200 Subject: [PATCH 202/308] arm64: dts: qcom: qcm2290: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-10-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 496e493c5845..e4741342e14c 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -1726,8 +1727,8 @@ mdss_dsi0: dsi@5e94000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmpd QCM2290_VDDCX>; @@ -1809,8 +1810,8 @@ dispcc: clock-controller@5f00000 { <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "gcc_disp_gpll0_clk_src", From adaa876233c102e53fb2bafe4f502474613f4ed2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:08 +0200 Subject: [PATCH 203/308] arm64: dts: qcom: sc7180: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-11-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 87c432c12a24..d157863dbc4a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -3284,8 +3285,10 @@ mdss_dsi0: dsi@ae94000 { "iface", "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7180_CX>; @@ -3433,8 +3436,8 @@ dispcc: clock-controller@af00000 { reg = <0 0x0af00000 0 0x200000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", From 4390fc773154ea25c0aeb4e75d0425cfa8de431f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:09 +0200 Subject: [PATCH 204/308] arm64: dts: qcom: sc8180x: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-12-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index f142eb63b8d7..30b8a666561d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -3465,10 +3466,10 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sc8180x-dispcc"; reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&edp_phy 0>, From 3c1ae3b255555406c5ff030190649437e399dde9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:10 +0200 Subject: [PATCH 205/308] arm64: dts: qcom: sdm630: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-13-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 9 +++++---- arch/arm64/boot/dts/qcom/sdm660.dtsi | 12 ++++++------ 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 3722e405a97c..2d3820536ddf 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2020, AngeloGioacchino Del Regno */ +#include #include #include #include @@ -1541,8 +1542,8 @@ mmcc: clock-controller@c8c0000 { <&sleep_clk>, <&gcc GCC_MMSS_GPLL0_CLK>, <&gcc GCC_MMSS_GPLL0_DIV_CLK>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <0>, <0>, <0>, @@ -1664,8 +1665,8 @@ mdss_dsi0: dsi@c994000 { assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_BYTE0_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index 3164a4817e32..ef4a563c0feb 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -170,8 +170,8 @@ mdss_dsi1: dsi@c996000 { assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_BYTE1_CLK>, @@ -239,10 +239,10 @@ &mmcc { <&sleep_clk>, <&gcc GCC_MMSS_GPLL0_CLK>, <&gcc GCC_MMSS_GPLL0_DIV_CLK>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, <0>, <0>; }; From dc489ba0dea37e3655d265f5889ade0d173229d5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:11 +0200 Subject: [PATCH 206/308] arm64: dts: qcom: sdm670: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-14-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 279e62ec5433..a68ef6741f8d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -1720,8 +1721,8 @@ mdss_dsi0: dsi@ae94000 { "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM670_CX>; @@ -1794,7 +1795,8 @@ mdss_dsi1: dsi@ae96000 { "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM670_CX>; @@ -1851,10 +1853,10 @@ dispcc: clock-controller@af00000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <0>, <0>; clock-names = "bi_tcxo", From 77764620c1888e8c8dc169f7c2f693fc4db96964 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:12 +0200 Subject: [PATCH 207/308] arm64: dts: qcom: sdm845: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-15-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 3 ++- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 3 ++- arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 +++++++++++++-------- 3 files changed, 17 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index a5932a61893b..2b2ef4dbad2f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -555,7 +555,8 @@ &mdss_dsi1 { qcom,dual-dsi-mode; /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index cd5172ad2490..a98756e8b965 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -495,7 +495,8 @@ &mdss_dsi1 { qcom,dual-dsi-mode; /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; ports { port@1 { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2968a5c541dc..5808129e2dde 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -4708,8 +4709,10 @@ mdss_dsi0: dsi@ae94000 { "core", "iface", "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; @@ -4780,8 +4783,10 @@ mdss_dsi1: dsi@ae96000 { "core", "iface", "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SDM845_CX>; @@ -4973,10 +4978,10 @@ dispcc: clock-controller@af00000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", From b44bf3bc74912649b2495894e82f5384e24e2060 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:13 +0200 Subject: [PATCH 208/308] arm64: dts: qcom: sm6115: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-16-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 94c081bf7a89..55a0db0ed9cb 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Iskren Chernev */ +#include #include #include #include @@ -1960,7 +1961,8 @@ mdss_dsi0: dsi@5e94000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmpd SM6115_VDDCX>; @@ -2034,8 +2036,8 @@ dispcc: clock-controller@5f00000 { reg = <0x0 0x05f00000 0 0x20000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; #clock-cells = <1>; #reset-cells = <1>; From 4f40ebbebcd9a7a03b72aac478c7df7c7b44c635 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:14 +0200 Subject: [PATCH 209/308] arm64: dts: qcom: sm6125: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-17-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 350d807a622f..091dbdd171b4 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -1340,7 +1341,8 @@ mdss_dsi0: dsi@5e94000 { "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmpd SM6125_VDDCX>; @@ -1415,8 +1417,8 @@ dispcc: clock-controller@5f00000 { reg = <0x05f00000 0x20000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, <0>, <0>, From ab7cd7f3968f14171d50ba0b0655186c3857d258 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:15 +0200 Subject: [PATCH 210/308] arm64: dts: qcom: sm6350: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-18-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 00ad1d09a195..1f2ac20e537e 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -2269,7 +2270,8 @@ mdss_dsi0: dsi@ae94000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; power-domains = <&rpmhpd SM6350_MX>; @@ -2347,8 +2349,8 @@ dispcc: clock-controller@af00000 { reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", From 35ed99d7f589f310688fa0d088913e5c8927da43 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:16 +0200 Subject: [PATCH 211/308] arm64: dts: qcom: sm8150: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-19-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 3 ++- arch/arm64/boot/dts/qcom/sm8150.dtsi | 17 +++++++++-------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 9ac9854b35fd..e1e294f0f462 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -500,7 +500,8 @@ &mdss_dsi1 { qcom,dual-dsi-mode; /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 4dbda54b47a5..2aca3fdae47c 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -3981,8 +3982,8 @@ mdss_dsi0: dsi@ae94000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8150_MMCX>; @@ -4074,8 +4075,8 @@ mdss_dsi1: dsi@ae96000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SM8150_MMCX>; @@ -4130,10 +4131,10 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sm8150-dispcc"; reg = <0 0x0af00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", From 855ff06098b7f3a2aca21b79d32d212fd096a98e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:17 +0200 Subject: [PATCH 212/308] arm64: dts: qcom: sm8250: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-20-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm8250-xiaomi-elish-common.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8250.dtsi | 21 ++++++++++++------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 01a321d801af..465fd6e954a3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -659,7 +659,8 @@ &mdss_dsi1 { qcom,dual-dsi-mode; qcom,sync-dual-dsi; /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 68613ea7146c..0425e14840c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -4861,8 +4862,10 @@ mdss_dsi0: dsi@ae94000 { "iface", "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -4953,8 +4956,10 @@ mdss_dsi1: dsi@ae96000 { "iface", "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -5011,10 +5016,10 @@ dispcc: clock-controller@af00000 { power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", From ee4bb3169263bad99d68e0039e944ae53e77691a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:18 +0200 Subject: [PATCH 213/308] arm64: dts: qcom: sm8350: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-21-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 5f93cae01b06..5676420bd5cc 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -2958,8 +2959,8 @@ mdss_dsi0: dsi@ae94000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi0_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -3057,8 +3058,8 @@ mdss_dsi1: dsi@ae96000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi1_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -3138,8 +3139,10 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sm8350-dispcc"; reg = <0 0x0af00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", From 0d18a031499d4ea2b86cdc8120c22bdcf22bcac0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:19 +0200 Subject: [PATCH 214/308] arm64: dts: qcom: sm8450: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-22-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 0b36f4cd4497..edfde85a2d0c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -3518,8 +3519,10 @@ mdss_dsi0: dsi@ae94000 { "iface", "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -3610,8 +3613,10 @@ mdss_dsi1: dsi@ae96000 { "iface", "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -3670,10 +3675,10 @@ dispcc: clock-controller@af00000 { <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ From 0d046b7ad7d3c7f2dfc53fc5ad48e2fe2c3f2186 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:20 +0200 Subject: [PATCH 215/308] arm64: dts: qcom: sm8550: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-23-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index f78d5292c5dd..a2732e04896e 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2022, Linaro Limited */ +#include #include #include #include @@ -3554,8 +3555,8 @@ mdss_dsi0: dsi@ae94000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -3649,8 +3650,8 @@ mdss_dsi1: dsi@ae96000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -3708,10 +3709,10 @@ dispcc: clock-controller@af00000 { <&bi_tcxo_ao_div2>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ From 314ffec606514cdf6d4bbedaaeeba0c826b6afc2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 8 Apr 2025 11:32:21 +0200 Subject: [PATCH 216/308] arm64: dts: qcom: sm8650: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250408-dts-qcom-dsi-phy-clocks-v2-24-73b482a6dd02@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 818db6ba3b3b..437daccca1bb 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2023, Linaro Limited */ +#include #include #include #include @@ -5213,8 +5214,8 @@ mdss_dsi0: dsi@ae94000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -5310,8 +5311,8 @@ mdss_dsi1: dsi@ae96000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -5458,10 +5459,10 @@ dispcc: clock-controller@af00000 { <&bi_tcxo_ao_div2>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ From 0d5da04d23c3b398595727a274887cb8ff1c06a3 Mon Sep 17 00:00:00 2001 From: "Russell King (Oracle)" Date: Sat, 12 Apr 2025 15:22:40 +0100 Subject: [PATCH 217/308] arm64: dts: qcom: remove max-speed = 1G for RGMII for ethernet The RGMII interface is designed for speeds up to 1G. Phylink already imposes the design limits for MII interfaces, and additional specification is unnecessary. Therefore, we can remove this property without any effect. Signed-off-by: Russell King (Oracle) Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/E1u3bkm-000Epw-QU@rmk-PC.armlinux.org.uk Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 1 - arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 2 -- 2 files changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 4dfd66076629..388d5ecee949 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -326,7 +326,6 @@ ðernet { phy-handle = <&rgmii_phy>; phy-mode = "rgmii"; - max-speed = <1000>; mdio { compatible = "snps,dwmac-mdio"; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 11663cf81e45..44177e9b64b5 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -155,7 +155,6 @@ ðernet0 { snps,mtl-rx-config = <ðernet0_mtl_rx_setup>; snps,mtl-tx-config = <ðernet0_mtl_tx_setup>; - max-speed = <1000>; phy-handle = <&rgmii_phy>; phy-mode = "rgmii-txid"; @@ -256,7 +255,6 @@ ðernet1 { snps,mtl-rx-config = <ðernet1_mtl_rx_setup>; snps,mtl-tx-config = <ðernet1_mtl_tx_setup>; - max-speed = <1000>; phy-mode = "rgmii-txid"; pinctrl-names = "default"; From 337921764e31907ea46df02c1d8dd1ae8f2802f5 Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Sat, 12 Apr 2025 14:49:18 +0200 Subject: [PATCH 218/308] arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: enable MICs LDO Particular device comes without headset combo jack, hence does not feature wcd codec IC. In such cases, DMICs are powered from vreg_l1b. Describe all 4 microphones in the audio routing. vdd-micb is defined for lpass-macro already. Signed-off-by: Aleksandrs Vinarskis Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250412124956.20562-1-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 35d97db9e1f6..445d97d67d32 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -152,7 +152,11 @@ sound { audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", "TweeterLeft IN", "WSA WSA_SPK2 OUT", "WooferRight IN", "WSA2 WSA_SPK2 OUT", - "TweeterRight IN", "WSA2 WSA_SPK2 OUT"; + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb"; wsa-dai-link { link-name = "WSA Playback"; From e8acfc1bbcda6978d952d0c18b0b5cebd6dcc3cf Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 11 Apr 2025 10:33:29 +0200 Subject: [PATCH 219/308] arm64: dts: qcom: Remove unnecessary MM_[UD]L audio routes Since commit 6fd8d2d275f7 ("ASoC: qcom: qdsp6: Move frontend AIFs to q6asm-dai") from over 4 years ago the audio routes beween MM_DL* + MultiMedia* Playback and MultiMedia* Capture + MM_UL* are not necessary anymore and can be removed from the dts files. It also helps to stop anyone copying these into new dts files. Signed-off-by: Luca Weiss Reviewed-by: Stephan Gerhold Reviewed-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20250411-cleanup-mm-routes-v1-1-ba98f653aa69@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 5 +---- arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 5 +---- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 2 -- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 6 +----- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 6 +----- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 5 +---- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 5 +---- 7 files changed, 6 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index e8148b3d6c50..1089964e6c0d 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -1012,10 +1012,7 @@ wcd9335: codec@1,0 { &sound { compatible = "qcom,apq8096-sndcard"; model = "DB820c"; - audio-routing = "RX_BIAS", "MCLK", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL2", "MultiMedia2 Playback", - "MultiMedia3 Capture", "MM_UL3"; + audio-routing = "RX_BIAS", "MCLK"; mm1-dai-link { link-name = "MultiMedia1"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index dbad8f57f2fa..d7fa56808747 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -156,10 +156,7 @@ &slpi_pil { &sound { compatible = "qcom,apq8096-sndcard"; model = "gemini"; - audio-routing = "RX_BIAS", "MCLK", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL2", "MultiMedia2 Playback", - "MultiMedia3 Capture", "MM_UL3"; + audio-routing = "RX_BIAS", "MCLK"; mm1-dai-link { link-name = "MultiMedia1"; diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index d485249bcda4..a37860175d27 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -110,8 +110,6 @@ sound { pinctrl-0 = <&lpi_i2s2_active>; pinctrl-names = "default"; model = "Qualcomm-RB2-WSA8815-Speakers-DMIC0"; - audio-routing = "MM_DL1", "MultiMedia1 Playback", - "MM_DL2", "MultiMedia2 Playback"; mm1-dai-link { link-name = "MultiMedia1"; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 4cc14ab1b9ea..dcb998b8b054 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1053,11 +1053,7 @@ &sound { "SpkrLeft IN", "WSA_SPK1 OUT", "SpkrRight IN", "WSA_SPK2 OUT", "VA DMIC0", "vdd-micb", - "VA DMIC1", "vdd-micb", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL2", "MultiMedia2 Playback", - "MultiMedia3 Capture", "MM_UL3", - "MM_DL4", "MultiMedia4 Playback"; + "VA DMIC1", "vdd-micb"; mm1-dai-link { link-name = "MultiMedia1"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 2b2ef4dbad2f..adfd91627005 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -777,11 +777,7 @@ &quat_mi2s_sd2_active "DMIC2", "MIC BIAS3", "DMIC3", "MIC BIAS3", "SpkrLeft IN", "SPK1 OUT", - "SpkrRight IN", "SPK2 OUT", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL2", "MultiMedia2 Playback", - "MM_DL4", "MultiMedia4 Playback", - "MultiMedia3 Capture", "MM_UL3"; + "SpkrRight IN", "SPK2 OUT"; mm1-dai-link { link-name = "MultiMedia1"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index e8012205954e..7677acd08e2d 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -632,10 +632,7 @@ &sound { "RX_BIAS", "MCLK", "AMIC2", "MIC BIAS2", "SpkrLeft IN", "SPK1 OUT", - "SpkrRight IN", "SPK2 OUT", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL3", "MultiMedia3 Playback", - "MultiMedia2 Capture", "MM_UL2"; + "SpkrRight IN", "SPK2 OUT"; mm1-dai-link { link-name = "MultiMedia1"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index 26217836c270..d6d4e7184c56 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -445,10 +445,7 @@ &sound { "RX_BIAS", "MCLK", "AMIC2", "MIC BIAS2", "SpkrLeft IN", "SPK1 OUT", - "SpkrRight IN", "SPK2 OUT", - "MM_DL1", "MultiMedia1 Playback", - "MM_DL3", "MultiMedia3 Playback", - "MultiMedia2 Capture", "MM_UL2"; + "SpkrRight IN", "SPK2 OUT"; mm1-dai-link { link-name = "MultiMedia1"; From 738dde31b5dca9c2be9a4639adcd34fb9fb5d019 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:25 -0500 Subject: [PATCH 220/308] arm64: dts: qcom: qdu1000: Fix qcom,freq-domain The correct property name is 'qcom,freq-domain', not 'qcom,freq-domains'. Signed-off-by: Rob Herring (Arm) Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250410-dt-cpu-schema-v2-4-63d7dc9ddd0a@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index f973aa8f7477..7c8d78fd7ebf 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -47,7 +47,7 @@ cpu0: cpu@0 { enable-method = "psci"; power-domains = <&cpu_pd0>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_0>; l2_0: l2-cache { compatible = "cache"; @@ -70,7 +70,7 @@ cpu1: cpu@100 { enable-method = "psci"; power-domains = <&cpu_pd1>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_100>; l2_100: l2-cache { compatible = "cache"; @@ -88,7 +88,7 @@ cpu2: cpu@200 { enable-method = "psci"; power-domains = <&cpu_pd2>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_200>; l2_200: l2-cache { compatible = "cache"; @@ -106,7 +106,7 @@ cpu3: cpu@300 { enable-method = "psci"; power-domains = <&cpu_pd3>; power-domain-names = "psci"; - qcom,freq-domains = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_300>; l2_300: l2-cache { compatible = "cache"; From 9100b9063767c8ee6906ed4dc18d1a8b1e7e7dd2 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:26 -0500 Subject: [PATCH 221/308] arm64: dts: qcom: msm8939: Fix CPU node "enable-method" property dependencies The "spin-table" enable-method requires "cpu-release-addr" property, so add a dummy entry. It is assumed the bootloader will fill in the correct values. Signed-off-by: Rob Herring (Arm) Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250410-dt-cpu-schema-v2-5-63d7dc9ddd0a@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 5e8c3ac39de8..ca478db63be4 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -47,6 +47,7 @@ cpu0: cpu@100 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x100>; next-level-cache = <&l2_1>; qcom,acc = <&acc0>; @@ -65,6 +66,7 @@ cpu1: cpu@101 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x101>; next-level-cache = <&l2_1>; qcom,acc = <&acc1>; @@ -78,6 +80,7 @@ cpu2: cpu@102 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x102>; next-level-cache = <&l2_1>; qcom,acc = <&acc2>; @@ -91,6 +94,7 @@ cpu3: cpu@103 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x103>; next-level-cache = <&l2_1>; qcom,acc = <&acc3>; @@ -104,6 +108,7 @@ cpu4: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x0>; qcom,acc = <&acc4>; qcom,saw = <&saw4>; @@ -122,6 +127,7 @@ cpu5: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x1>; next-level-cache = <&l2_0>; qcom,acc = <&acc5>; @@ -135,6 +141,7 @@ cpu6: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x2>; next-level-cache = <&l2_0>; qcom,acc = <&acc6>; @@ -148,6 +155,7 @@ cpu7: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; reg = <0x3>; next-level-cache = <&l2_0>; qcom,acc = <&acc7>; From b8e10d2f5afb89957a1b45052ae3b8b061209690 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:27 -0500 Subject: [PATCH 222/308] arm64: dts: qcom: msm8992-lg-h815: Fix CPU node "enable-method" property dependencies The "spin-table" enable-method requires "cpu-release-addr" property, so add a dummy entry. It is assumed the bootloader will fill in the correct values. Signed-off-by: Rob Herring (Arm) Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250410-dt-cpu-schema-v2-6-63d7dc9ddd0a@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts index 4520d5d51a29..6a231afad85d 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-h815.dts @@ -93,26 +93,32 @@ key-vol-up { &cpu0 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu1 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu2 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu3 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu4 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &cpu5 { enable-method = "spin-table"; + cpu-release-addr = /bits/ 64 <0>; }; &pm8994_resin { From 2eca6af66709de0d1ba14cdf8b6d200a1337a3a2 Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Tue, 15 Apr 2025 16:01:01 +0300 Subject: [PATCH 223/308] arm64: dts: qcom: sdm660-xiaomi-lavender: Add missing SD card detect GPIO During initial porting these cd-gpios were missed. Having card detect is beneficial because driver does not need to do polling every second and it can just use IRQ. SD card detection in U-Boot is also fixed by this. Fixes: cf85e9aee210 ("arm64: dts: qcom: sdm660-xiaomi-lavender: Add eMMC and SD") Signed-off-by: Alexey Minnekhanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250415130101.1429281-1-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 7167f75bced3..0b4d71c14a77 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -404,6 +404,8 @@ &sdhc_1 { &sdhc_2 { status = "okay"; + cd-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vreg_l5b_2p95>; vqmmc-supply = <&vreg_l2b_2p95>; }; From 33e020b942cb4bcf2f3870b573470973e6464bd5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:25:59 +0300 Subject: [PATCH 224/308] arm64: dts: qcom: sc7280: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-1-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ec96c917b56b..d780b5a18cf6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -6,6 +6,7 @@ */ #include #include +#include #include #include #include @@ -4617,8 +4618,8 @@ dispcc: clock-controller@af00000 { reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <&mdss_dsi_phy 0>, - <&mdss_dsi_phy 1>, + <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&mdss_edp_phy 0>, @@ -4775,8 +4776,10 @@ mdss_dsi: dsi@ae94000 { "iface", "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7280_CX>; From 8725fb400542a6c88c1cc918d96064eedc8c94c4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:00 +0300 Subject: [PATCH 225/308] arm64: dts: qcom: sa8775p: mark MDP interconnects as ALWAYS on Change the tag for MDP interconnects to QCOM_ICC_TAG_ALWAYS, so that if CPUSS collapses, the display may stay on. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-2-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index a904960359d7..4da50c5ec612 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3959,10 +3959,10 @@ mdss0: display-subsystem@ae00000 { reg-names = "mdss"; /* same path used twice */ - interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "mdp0-mem", From 31e18ebef09a596ea87277c24411e1a86eb56470 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:01 +0300 Subject: [PATCH 226/308] arm64: dts: qcom: msm8998: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-3-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 7eca38440cd7..cb7055446741 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2830,8 +2830,8 @@ mdss_mdp: display-controller@c901000 { compatible = "qcom,msm8998-dpu"; reg = <0x0c901000 0x8f000>, <0x0c9a8e00 0xf0>, - <0x0c9b0000 0x2008>, - <0x0c9b8000 0x1040>; + <0x0c9b0000 0x3000>, + <0x0c9b8000 0x3000>; reg-names = "mdp", "regdma", "vbif", From bacf203baa1ef896ac2bb4f9bf43b19f15a6ae26 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:02 +0300 Subject: [PATCH 227/308] arm64: dts: qcom: qcm2290: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-4-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index e4741342e14c..6a7ce2c6b88e 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1641,7 +1641,7 @@ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, mdp: display-controller@5e01000 { compatible = "qcom,qcm2290-dpu"; reg = <0x0 0x05e01000 0x0 0x8f000>, - <0x0 0x05eb0000 0x0 0x2008>; + <0x0 0x05eb0000 0x0 0x3000>; reg-names = "mdp", "vbif"; From 180f990ed061cefdac620d02f34b03387210a2b7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:03 +0300 Subject: [PATCH 228/308] arm64: dts: qcom: sa8775p: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-5-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 4da50c5ec612..2e5f2ad8b92c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3992,7 +3992,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, mdss0_mdp: display-controller@ae01000 { compatible = "qcom,sa8775p-dpu"; reg = <0x0 0x0ae01000 0x0 0x8f000>, - <0x0 0x0aeb0000 0x0 0x2008>; + <0x0 0x0aeb0000 0x0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, From 74e18dc4aef0e8e2989815856e48c737820ebca8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:04 +0300 Subject: [PATCH 229/308] arm64: dts: qcom: sc7180: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-6-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index d157863dbc4a..bb1880a9458b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3196,7 +3196,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, mdp: display-controller@ae01000 { compatible = "qcom,sc7180-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, From 545b26b926ae20640a7d464e1b830ce4ce021fd5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:05 +0300 Subject: [PATCH 230/308] arm64: dts: qcom: sc7280: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-7-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d780b5a18cf6..8e86d75cc6b4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4673,7 +4673,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, mdss_mdp: display-controller@ae01000 { compatible = "qcom,sc7280-dpu"; reg = <0 0x0ae01000 0 0x8f030>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, From a24e1cb954a6915983280e757c36d04fd5e6ce34 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:06 +0300 Subject: [PATCH 231/308] arm64: dts: qcom: sc8180x: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-8-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 30b8a666561d..b84e47a461a0 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2977,7 +2977,7 @@ &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, mdss_mdp: mdp@ae01000 { compatible = "qcom,sc8180x-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, From 7b5160ce90a3c6c8e6202f727c3e6cd2c0911cbd Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:07 +0300 Subject: [PATCH 232/308] arm64: dts: qcom: sc8280xp: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-9-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index f57c23c244b6..35ef31d4ecf2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4141,7 +4141,7 @@ mdss0: display-subsystem@ae00000 { mdss0_mdp: display-controller@ae01000 { compatible = "qcom,sc8280xp-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, @@ -5459,7 +5459,7 @@ mdss1: display-subsystem@22000000 { mdss1_mdp: display-controller@22001000 { compatible = "qcom,sc8280xp-dpu"; reg = <0 0x22001000 0 0x8f000>, - <0 0x220b0000 0 0x2008>; + <0 0x220b0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, From acc206fed3698554a16cf70e5a2fc0e4f1e1a5fc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:08 +0300 Subject: [PATCH 233/308] arm64: dts: qcom: sdm670: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-10-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index a68ef6741f8d..3ecf41cf2b87 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1636,7 +1636,7 @@ mdss: display-subsystem@ae00000 { mdss_mdp: display-controller@ae01000 { compatible = "qcom,sdm670-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_AXI_CLK>, From e50450aae01ea23e17e10f59cdbdc7aa59108250 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:09 +0300 Subject: [PATCH 234/308] arm64: dts: qcom: sdm845: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-11-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5808129e2dde..19ece2daedbc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4546,7 +4546,7 @@ mdss: display-subsystem@ae00000 { mdss_mdp: display-controller@ae01000 { compatible = "qcom,sdm845-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_AXI_CLK>, From c7f4216765891939e6d2dfa8809883bae978582f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:10 +0300 Subject: [PATCH 235/308] arm64: dts: qcom: sm6115: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-12-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 55a0db0ed9cb..c8865779173e 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1874,7 +1874,7 @@ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, mdp: display-controller@5e01000 { compatible = "qcom,sm6115-dpu"; reg = <0x0 0x05e01000 0x0 0x8f000>, - <0x0 0x05eb0000 0x0 0x2008>; + <0x0 0x05eb0000 0x0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, From e24c7cb72b9b1286deee43fecf87d0248fa430cc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:11 +0300 Subject: [PATCH 236/308] arm64: dts: qcom: sm6125: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-13-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 091dbdd171b4..8f2d65543373 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1251,7 +1251,7 @@ mdss: display-subsystem@5e00000 { mdss_mdp: display-controller@5e01000 { compatible = "qcom,sm6125-dpu"; reg = <0x05e01000 0x83208>, - <0x05eb0000 0x2008>; + <0x05eb0000 0x3000>; reg-names = "mdp", "vbif"; interrupt-parent = <&mdss>; From 7cfcd1a3c519d0aff10af2db06aa6d2291393bd8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:12 +0300 Subject: [PATCH 237/308] arm64: dts: qcom: sm6350: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-14-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 1f2ac20e537e..a77cf57fcfb1 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2086,7 +2086,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm6350-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; interrupt-parent = <&mdss>; From 130e9aacc40176b5fa2954e7861d9b5f28f373ae Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:13 +0300 Subject: [PATCH 238/308] arm64: dts: qcom: sm8150: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-15-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 2aca3fdae47c..e364cd07193a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3809,7 +3809,7 @@ mdss: display-subsystem@ae00000 { mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8150-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, From 4e851ff6a3a12ce616e3cc902af0ae2efb2e8137 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:14 +0300 Subject: [PATCH 239/308] arm64: dts: qcom: sm8250: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-16-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 0425e14840c6..f0d18fd37aaf 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4691,7 +4691,7 @@ mdss: display-subsystem@ae00000 { mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8250-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, From d55fe5da78836835f9a88c29dd2fb3086b4a3720 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:15 +0300 Subject: [PATCH 240/308] arm64: dts: qcom: sm8350: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-17-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 5676420bd5cc..279a68a7146e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2775,7 +2775,7 @@ mdss: display-subsystem@ae00000 { mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8350-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, From 62acfd77a5783948ba3593fb169720ab7495c380 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:16 +0300 Subject: [PATCH 241/308] arm64: dts: qcom: sm8450: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-18-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index edfde85a2d0c..a94188ecf384 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3337,7 +3337,7 @@ mdss: display-subsystem@ae00000 { mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8450-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, From 9e9d8349e76252d5b7e060cc0ca4823a3f062052 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:17 +0300 Subject: [PATCH 242/308] arm64: dts: qcom: sm8550: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-19-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index a2732e04896e..82cabf777cd2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3374,7 +3374,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8550-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; interrupt-parent = <&mdss>; From d8203fff4e6849cc5799fcf51105f7622e13c46d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 13:26:18 +0300 Subject: [PATCH 243/308] arm64: dts: qcom: sm8650: use correct size for VBIF regions Use allocated region size for VBIF regions as defined by the docs (0x3000) instead of just using the last register address. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-20-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 437daccca1bb..c2937f721794 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5114,7 +5114,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8650-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; From eb73f500548a3205741330cbd7d0e209a7a6a9af Mon Sep 17 00:00:00 2001 From: Ling Xu Date: Tue, 11 Feb 2025 13:44:14 +0530 Subject: [PATCH 244/308] arm64: dts: qcom: sa8775p: Remove extra entries from the iommus property There are some items come out to be same value if we do SID & ~MASK. Remove extra entries from the iommus property for sa8775p to simplify. Fixes: f7b01bfb4b47 ("arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodes") Cc: stable@kernel.org Reviewed-by: Dmitry Baryshkov Signed-off-by: Ling Xu Link: https://lore.kernel.org/r/49f463415c8fa2b08fbc2317e31493362056f403.1739260973.git.quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 240 +++----------------------- 1 file changed, 24 insertions(+), 216 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 2e5f2ad8b92c..0d3dcb2e3903 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -5051,15 +5051,7 @@ compute-cb@1 { compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x2141 0x04a0>, - <&apps_smmu 0x2161 0x04a0>, - <&apps_smmu 0x2181 0x0400>, - <&apps_smmu 0x21c1 0x04a0>, - <&apps_smmu 0x21e1 0x04a0>, - <&apps_smmu 0x2541 0x04a0>, - <&apps_smmu 0x2561 0x04a0>, - <&apps_smmu 0x2581 0x0400>, - <&apps_smmu 0x25c1 0x04a0>, - <&apps_smmu 0x25e1 0x04a0>; + <&apps_smmu 0x2181 0x0400>; dma-coherent; }; @@ -5067,15 +5059,7 @@ compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x2142 0x04a0>, - <&apps_smmu 0x2162 0x04a0>, - <&apps_smmu 0x2182 0x0400>, - <&apps_smmu 0x21c2 0x04a0>, - <&apps_smmu 0x21e2 0x04a0>, - <&apps_smmu 0x2542 0x04a0>, - <&apps_smmu 0x2562 0x04a0>, - <&apps_smmu 0x2582 0x0400>, - <&apps_smmu 0x25c2 0x04a0>, - <&apps_smmu 0x25e2 0x04a0>; + <&apps_smmu 0x2182 0x0400>; dma-coherent; }; @@ -5083,15 +5067,7 @@ compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x2143 0x04a0>, - <&apps_smmu 0x2163 0x04a0>, - <&apps_smmu 0x2183 0x0400>, - <&apps_smmu 0x21c3 0x04a0>, - <&apps_smmu 0x21e3 0x04a0>, - <&apps_smmu 0x2543 0x04a0>, - <&apps_smmu 0x2563 0x04a0>, - <&apps_smmu 0x2583 0x0400>, - <&apps_smmu 0x25c3 0x04a0>, - <&apps_smmu 0x25e3 0x04a0>; + <&apps_smmu 0x2183 0x0400>; dma-coherent; }; @@ -5099,15 +5075,7 @@ compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x2144 0x04a0>, - <&apps_smmu 0x2164 0x04a0>, - <&apps_smmu 0x2184 0x0400>, - <&apps_smmu 0x21c4 0x04a0>, - <&apps_smmu 0x21e4 0x04a0>, - <&apps_smmu 0x2544 0x04a0>, - <&apps_smmu 0x2564 0x04a0>, - <&apps_smmu 0x2584 0x0400>, - <&apps_smmu 0x25c4 0x04a0>, - <&apps_smmu 0x25e4 0x04a0>; + <&apps_smmu 0x2184 0x0400>; dma-coherent; }; @@ -5115,15 +5083,7 @@ compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x2145 0x04a0>, - <&apps_smmu 0x2165 0x04a0>, - <&apps_smmu 0x2185 0x0400>, - <&apps_smmu 0x21c5 0x04a0>, - <&apps_smmu 0x21e5 0x04a0>, - <&apps_smmu 0x2545 0x04a0>, - <&apps_smmu 0x2565 0x04a0>, - <&apps_smmu 0x2585 0x0400>, - <&apps_smmu 0x25c5 0x04a0>, - <&apps_smmu 0x25e5 0x04a0>; + <&apps_smmu 0x2185 0x0400>; dma-coherent; }; @@ -5131,15 +5091,7 @@ compute-cb@6 { compatible = "qcom,fastrpc-compute-cb"; reg = <6>; iommus = <&apps_smmu 0x2146 0x04a0>, - <&apps_smmu 0x2166 0x04a0>, - <&apps_smmu 0x2186 0x0400>, - <&apps_smmu 0x21c6 0x04a0>, - <&apps_smmu 0x21e6 0x04a0>, - <&apps_smmu 0x2546 0x04a0>, - <&apps_smmu 0x2566 0x04a0>, - <&apps_smmu 0x2586 0x0400>, - <&apps_smmu 0x25c6 0x04a0>, - <&apps_smmu 0x25e6 0x04a0>; + <&apps_smmu 0x2186 0x0400>; dma-coherent; }; @@ -5147,15 +5099,7 @@ compute-cb@7 { compatible = "qcom,fastrpc-compute-cb"; reg = <7>; iommus = <&apps_smmu 0x2147 0x04a0>, - <&apps_smmu 0x2167 0x04a0>, - <&apps_smmu 0x2187 0x0400>, - <&apps_smmu 0x21c7 0x04a0>, - <&apps_smmu 0x21e7 0x04a0>, - <&apps_smmu 0x2547 0x04a0>, - <&apps_smmu 0x2567 0x04a0>, - <&apps_smmu 0x2587 0x0400>, - <&apps_smmu 0x25c7 0x04a0>, - <&apps_smmu 0x25e7 0x04a0>; + <&apps_smmu 0x2187 0x0400>; dma-coherent; }; @@ -5163,15 +5107,7 @@ compute-cb@8 { compatible = "qcom,fastrpc-compute-cb"; reg = <8>; iommus = <&apps_smmu 0x2148 0x04a0>, - <&apps_smmu 0x2168 0x04a0>, - <&apps_smmu 0x2188 0x0400>, - <&apps_smmu 0x21c8 0x04a0>, - <&apps_smmu 0x21e8 0x04a0>, - <&apps_smmu 0x2548 0x04a0>, - <&apps_smmu 0x2568 0x04a0>, - <&apps_smmu 0x2588 0x0400>, - <&apps_smmu 0x25c8 0x04a0>, - <&apps_smmu 0x25e8 0x04a0>; + <&apps_smmu 0x2188 0x0400>; dma-coherent; }; @@ -5179,15 +5115,7 @@ compute-cb@9 { compatible = "qcom,fastrpc-compute-cb"; reg = <9>; iommus = <&apps_smmu 0x2149 0x04a0>, - <&apps_smmu 0x2169 0x04a0>, - <&apps_smmu 0x2189 0x0400>, - <&apps_smmu 0x21c9 0x04a0>, - <&apps_smmu 0x21e9 0x04a0>, - <&apps_smmu 0x2549 0x04a0>, - <&apps_smmu 0x2569 0x04a0>, - <&apps_smmu 0x2589 0x0400>, - <&apps_smmu 0x25c9 0x04a0>, - <&apps_smmu 0x25e9 0x04a0>; + <&apps_smmu 0x2189 0x0400>; dma-coherent; }; @@ -5195,15 +5123,7 @@ compute-cb@10 { compatible = "qcom,fastrpc-compute-cb"; reg = <10>; iommus = <&apps_smmu 0x214a 0x04a0>, - <&apps_smmu 0x216a 0x04a0>, - <&apps_smmu 0x218a 0x0400>, - <&apps_smmu 0x21ca 0x04a0>, - <&apps_smmu 0x21ea 0x04a0>, - <&apps_smmu 0x254a 0x04a0>, - <&apps_smmu 0x256a 0x04a0>, - <&apps_smmu 0x258a 0x0400>, - <&apps_smmu 0x25ca 0x04a0>, - <&apps_smmu 0x25ea 0x04a0>; + <&apps_smmu 0x218a 0x0400>; dma-coherent; }; @@ -5211,15 +5131,7 @@ compute-cb@11 { compatible = "qcom,fastrpc-compute-cb"; reg = <11>; iommus = <&apps_smmu 0x214b 0x04a0>, - <&apps_smmu 0x216b 0x04a0>, - <&apps_smmu 0x218b 0x0400>, - <&apps_smmu 0x21cb 0x04a0>, - <&apps_smmu 0x21eb 0x04a0>, - <&apps_smmu 0x254b 0x04a0>, - <&apps_smmu 0x256b 0x04a0>, - <&apps_smmu 0x258b 0x0400>, - <&apps_smmu 0x25cb 0x04a0>, - <&apps_smmu 0x25eb 0x04a0>; + <&apps_smmu 0x218b 0x0400>; dma-coherent; }; }; @@ -5279,15 +5191,7 @@ compute-cb@1 { compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x2941 0x04a0>, - <&apps_smmu 0x2961 0x04a0>, - <&apps_smmu 0x2981 0x0400>, - <&apps_smmu 0x29c1 0x04a0>, - <&apps_smmu 0x29e1 0x04a0>, - <&apps_smmu 0x2d41 0x04a0>, - <&apps_smmu 0x2d61 0x04a0>, - <&apps_smmu 0x2d81 0x0400>, - <&apps_smmu 0x2dc1 0x04a0>, - <&apps_smmu 0x2de1 0x04a0>; + <&apps_smmu 0x2981 0x0400>; dma-coherent; }; @@ -5295,15 +5199,7 @@ compute-cb@2 { compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x2942 0x04a0>, - <&apps_smmu 0x2962 0x04a0>, - <&apps_smmu 0x2982 0x0400>, - <&apps_smmu 0x29c2 0x04a0>, - <&apps_smmu 0x29e2 0x04a0>, - <&apps_smmu 0x2d42 0x04a0>, - <&apps_smmu 0x2d62 0x04a0>, - <&apps_smmu 0x2d82 0x0400>, - <&apps_smmu 0x2dc2 0x04a0>, - <&apps_smmu 0x2de2 0x04a0>; + <&apps_smmu 0x2982 0x0400>; dma-coherent; }; @@ -5311,15 +5207,7 @@ compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x2943 0x04a0>, - <&apps_smmu 0x2963 0x04a0>, - <&apps_smmu 0x2983 0x0400>, - <&apps_smmu 0x29c3 0x04a0>, - <&apps_smmu 0x29e3 0x04a0>, - <&apps_smmu 0x2d43 0x04a0>, - <&apps_smmu 0x2d63 0x04a0>, - <&apps_smmu 0x2d83 0x0400>, - <&apps_smmu 0x2dc3 0x04a0>, - <&apps_smmu 0x2de3 0x04a0>; + <&apps_smmu 0x2983 0x0400>; dma-coherent; }; @@ -5327,15 +5215,7 @@ compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x2944 0x04a0>, - <&apps_smmu 0x2964 0x04a0>, - <&apps_smmu 0x2984 0x0400>, - <&apps_smmu 0x29c4 0x04a0>, - <&apps_smmu 0x29e4 0x04a0>, - <&apps_smmu 0x2d44 0x04a0>, - <&apps_smmu 0x2d64 0x04a0>, - <&apps_smmu 0x2d84 0x0400>, - <&apps_smmu 0x2dc4 0x04a0>, - <&apps_smmu 0x2de4 0x04a0>; + <&apps_smmu 0x2984 0x0400>; dma-coherent; }; @@ -5343,15 +5223,7 @@ compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x2945 0x04a0>, - <&apps_smmu 0x2965 0x04a0>, - <&apps_smmu 0x2985 0x0400>, - <&apps_smmu 0x29c5 0x04a0>, - <&apps_smmu 0x29e5 0x04a0>, - <&apps_smmu 0x2d45 0x04a0>, - <&apps_smmu 0x2d65 0x04a0>, - <&apps_smmu 0x2d85 0x0400>, - <&apps_smmu 0x2dc5 0x04a0>, - <&apps_smmu 0x2de5 0x04a0>; + <&apps_smmu 0x2985 0x0400>; dma-coherent; }; @@ -5359,15 +5231,7 @@ compute-cb@6 { compatible = "qcom,fastrpc-compute-cb"; reg = <6>; iommus = <&apps_smmu 0x2946 0x04a0>, - <&apps_smmu 0x2966 0x04a0>, - <&apps_smmu 0x2986 0x0400>, - <&apps_smmu 0x29c6 0x04a0>, - <&apps_smmu 0x29e6 0x04a0>, - <&apps_smmu 0x2d46 0x04a0>, - <&apps_smmu 0x2d66 0x04a0>, - <&apps_smmu 0x2d86 0x0400>, - <&apps_smmu 0x2dc6 0x04a0>, - <&apps_smmu 0x2de6 0x04a0>; + <&apps_smmu 0x2986 0x0400>; dma-coherent; }; @@ -5375,15 +5239,7 @@ compute-cb@7 { compatible = "qcom,fastrpc-compute-cb"; reg = <7>; iommus = <&apps_smmu 0x2947 0x04a0>, - <&apps_smmu 0x2967 0x04a0>, - <&apps_smmu 0x2987 0x0400>, - <&apps_smmu 0x29c7 0x04a0>, - <&apps_smmu 0x29e7 0x04a0>, - <&apps_smmu 0x2d47 0x04a0>, - <&apps_smmu 0x2d67 0x04a0>, - <&apps_smmu 0x2d87 0x0400>, - <&apps_smmu 0x2dc7 0x04a0>, - <&apps_smmu 0x2de7 0x04a0>; + <&apps_smmu 0x2987 0x0400>; dma-coherent; }; @@ -5391,15 +5247,7 @@ compute-cb@8 { compatible = "qcom,fastrpc-compute-cb"; reg = <8>; iommus = <&apps_smmu 0x2948 0x04a0>, - <&apps_smmu 0x2968 0x04a0>, - <&apps_smmu 0x2988 0x0400>, - <&apps_smmu 0x29c8 0x04a0>, - <&apps_smmu 0x29e8 0x04a0>, - <&apps_smmu 0x2d48 0x04a0>, - <&apps_smmu 0x2d68 0x04a0>, - <&apps_smmu 0x2d88 0x0400>, - <&apps_smmu 0x2dc8 0x04a0>, - <&apps_smmu 0x2de8 0x04a0>; + <&apps_smmu 0x2988 0x0400>; dma-coherent; }; @@ -5407,15 +5255,7 @@ compute-cb@9 { compatible = "qcom,fastrpc-compute-cb"; reg = <9>; iommus = <&apps_smmu 0x2949 0x04a0>, - <&apps_smmu 0x2969 0x04a0>, - <&apps_smmu 0x2989 0x0400>, - <&apps_smmu 0x29c9 0x04a0>, - <&apps_smmu 0x29e9 0x04a0>, - <&apps_smmu 0x2d49 0x04a0>, - <&apps_smmu 0x2d69 0x04a0>, - <&apps_smmu 0x2d89 0x0400>, - <&apps_smmu 0x2dc9 0x04a0>, - <&apps_smmu 0x2de9 0x04a0>; + <&apps_smmu 0x2989 0x0400>; dma-coherent; }; @@ -5423,15 +5263,7 @@ compute-cb@10 { compatible = "qcom,fastrpc-compute-cb"; reg = <10>; iommus = <&apps_smmu 0x294a 0x04a0>, - <&apps_smmu 0x296a 0x04a0>, - <&apps_smmu 0x298a 0x0400>, - <&apps_smmu 0x29ca 0x04a0>, - <&apps_smmu 0x29ea 0x04a0>, - <&apps_smmu 0x2d4a 0x04a0>, - <&apps_smmu 0x2d6a 0x04a0>, - <&apps_smmu 0x2d8a 0x0400>, - <&apps_smmu 0x2dca 0x04a0>, - <&apps_smmu 0x2dea 0x04a0>; + <&apps_smmu 0x298a 0x0400>; dma-coherent; }; @@ -5439,15 +5271,7 @@ compute-cb@11 { compatible = "qcom,fastrpc-compute-cb"; reg = <11>; iommus = <&apps_smmu 0x294b 0x04a0>, - <&apps_smmu 0x296b 0x04a0>, - <&apps_smmu 0x298b 0x0400>, - <&apps_smmu 0x29cb 0x04a0>, - <&apps_smmu 0x29eb 0x04a0>, - <&apps_smmu 0x2d4b 0x04a0>, - <&apps_smmu 0x2d6b 0x04a0>, - <&apps_smmu 0x2d8b 0x0400>, - <&apps_smmu 0x2dcb 0x04a0>, - <&apps_smmu 0x2deb 0x04a0>; + <&apps_smmu 0x298b 0x0400>; dma-coherent; }; @@ -5455,15 +5279,7 @@ compute-cb@12 { compatible = "qcom,fastrpc-compute-cb"; reg = <12>; iommus = <&apps_smmu 0x294c 0x04a0>, - <&apps_smmu 0x296c 0x04a0>, - <&apps_smmu 0x298c 0x0400>, - <&apps_smmu 0x29cc 0x04a0>, - <&apps_smmu 0x29ec 0x04a0>, - <&apps_smmu 0x2d4c 0x04a0>, - <&apps_smmu 0x2d6c 0x04a0>, - <&apps_smmu 0x2d8c 0x0400>, - <&apps_smmu 0x2dcc 0x04a0>, - <&apps_smmu 0x2dec 0x04a0>; + <&apps_smmu 0x298c 0x0400>; dma-coherent; }; @@ -5471,15 +5287,7 @@ compute-cb@13 { compatible = "qcom,fastrpc-compute-cb"; reg = <13>; iommus = <&apps_smmu 0x294d 0x04a0>, - <&apps_smmu 0x296d 0x04a0>, - <&apps_smmu 0x298d 0x0400>, - <&apps_smmu 0x29Cd 0x04a0>, - <&apps_smmu 0x29ed 0x04a0>, - <&apps_smmu 0x2d4d 0x04a0>, - <&apps_smmu 0x2d6d 0x04a0>, - <&apps_smmu 0x2d8d 0x0400>, - <&apps_smmu 0x2dcd 0x04a0>, - <&apps_smmu 0x2ded 0x04a0>; + <&apps_smmu 0x298d 0x0400>; dma-coherent; }; }; From d180c2bd3b43d55f30c9b99de68bc6bb8420d1c1 Mon Sep 17 00:00:00 2001 From: Karthik Sanagavarapu Date: Tue, 11 Feb 2025 13:44:15 +0530 Subject: [PATCH 245/308] arm64: dts: qcom: sa8775p: Remove cdsp compute-cb@10 Remove the context bank compute-cb@10 because these SMMU ids are S2-only which is not used for S1 transaction. Fixes: f7b01bfb4b47 ("arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodes") Cc: stable@kernel.org Signed-off-by: Karthik Sanagavarapu Signed-off-by: Ling Xu Link: https://lore.kernel.org/r/4c9de858fda7848b77ea8c528c9b9d53600ad21a.1739260973.git.quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 0d3dcb2e3903..5bd0c03476b1 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -5119,14 +5119,6 @@ compute-cb@9 { dma-coherent; }; - compute-cb@10 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <10>; - iommus = <&apps_smmu 0x214a 0x04a0>, - <&apps_smmu 0x218a 0x0400>; - dma-coherent; - }; - compute-cb@11 { compatible = "qcom,fastrpc-compute-cb"; reg = <11>; From 9361ee93ac9d1b6730a65fc690e64cffaa41335e Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 21 Feb 2025 15:04:56 +0530 Subject: [PATCH 246/308] arm64: dts: qcom: qcm6490-idp: Update the LPASS audio node Update the lpassaudio node to support the new compatible as the lpassaudio needs to support the reset functionality on the QCM6490 IDP board and the rest of the Audio functionality would be provided from the LPASS firmware. Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20250221-lpass_qcm6490_resets-v5-3-6be0c0949a83@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 4e5176176860..7a155ef6492e 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -780,3 +780,8 @@ &wifi { status = "okay"; }; + +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; From f716f5dcf5cc40a0e883513b93dfaf35c50e7ead Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 21 Feb 2025 15:04:57 +0530 Subject: [PATCH 247/308] arm64: dts: qcom: qcs6490-rb3gen2: Update the LPASS audio node Update the lpassaudio node to support the new compatible as the lpassaudio needs to support the reset functionality on the QCS6490 RB3Gen2 board and the rest of the Audio functionality would be provided from the LPASS firmware. Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20250221-lpass_qcm6490_resets-v5-4-6be0c0949a83@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index e6811a094332..5fbcd48f2e2d 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1264,3 +1264,8 @@ sd_cd: sd-cd-state { bias-pull-up; }; }; + +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; From 104790b0699462dcf208a7d0290fc7a7fe44cc54 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 17:33:05 +0100 Subject: [PATCH 248/308] arm64: dts: qcom: sm8750: Add Modem / MPSS Add nodes for the MPSS and its SMP2P. These are compatible with earlier SM8650 with difference in lack of fifth memory region for Qlink Logging. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250221-b4-sm8750-modem-v3-1-462dae7303c7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 92 ++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 612b99dc3c55..149d2ed17641 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -577,6 +577,45 @@ smp2p_cdsp_in: slave-kernel { }; }; + smp2p-modem { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <435>, <428>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* TODO: smem mailbox in and out */ + }; + soc: soc@0 { compatible = "simple-bus"; @@ -2060,6 +2099,59 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sm8750-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; + power-domain-names = "cx", + "mss"; + + memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, + <&dsm_partition_1_mem>, + <&dsm_partition_2_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <1>; + + label = "mpss"; + }; + }; + remoteproc_adsp: remoteproc@6800000 { compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas"; reg = <0x0 0x06800000 0x0 0x10000>; From 9facd1c15b9362f280dd2c27e08cc1942eacd1cf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 17:33:06 +0100 Subject: [PATCH 249/308] arm64: dts: qcom: sm8750-mtp: Enable modem Enable the modem (MPSS) on MPT8750 board. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250221-b4-sm8750-modem-v3-2-462dae7303c7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 5d0decd2aa2d..72f081a890df 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -798,6 +798,14 @@ &remoteproc_cdsp { status = "okay"; }; +&remoteproc_mpss { + firmware-name = "qcom/sm8750/modem.mbn", + "qcom/sm8750/modem_dtb.mbn"; + + /* Modem crashes after some time with "DOG detects stalled initialization" */ + status = "fail"; +}; + &tlmm { /* reserved for secure world */ gpio-reserved-ranges = <36 4>, <74 1>; From ddf4c3840a3cfea3a037f778ad9223b9337e0bc5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Feb 2025 17:33:07 +0100 Subject: [PATCH 250/308] arm64: dts: qcom: sm8750-qrd: Enable modem Enable the modem (MPSS) on QRD8750 board. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250221-b4-sm8750-modem-v3-3-462dae7303c7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts index 7f1d5d4e5b28..840a6d8f8a24 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -796,6 +796,13 @@ &remoteproc_cdsp { status = "okay"; }; +&remoteproc_mpss { + firmware-name = "qcom/sm8750/modem.mbn", + "qcom/sm8750/modem_dtb.mbn"; + + status = "okay"; +}; + &tlmm { /* reserved for secure world */ gpio-reserved-ranges = <36 4>, <74 1>; From 441ef8588c4608d9742dc73f8ba2102c0db68a34 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 4 Feb 2025 22:50:17 -0500 Subject: [PATCH 251/308] arm64: dts: qcom: sdm670: add camss and cci Add the camera subsystem and CCI used to interface with cameras on the Snapdragon 670. Signed-off-by: Richard Acayan Reviewed-by: Bryan O'Donoghue Reviewed-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250205035013.206890-8-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 197 +++++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 3ecf41cf2b87..c33f3de779f6 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2022, Richard Acayan. All rights reserved. */ +#include #include #include #include @@ -1189,6 +1190,34 @@ tlmm: pinctrl@3400000 { gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc>; + cci0_default: cci0-default-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + qup_i2c0_default: qup-i2c0-default-state { pins = "gpio0", "gpio1"; function = "qup0"; @@ -1595,6 +1624,174 @@ spmi_bus: spmi@c440000 { #interrupt-cells = <4>; }; + cci: cci@ac4a000 { + compatible = "qcom,sdm670-cci", "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x4000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_CLK>; + clock-names = "camnoc_axi", + "soc_ahb", + "cpas_ahb", + "cci"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camss: isp@acb3000 { + compatible = "qcom,sdm670-camss"; + reg = <0 0x0acb3000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acc4000 0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0", + "vfe0_axi", + "vfe0_cphy_rx", + "vfe1", + "vfe1_axi", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + iommus = <&apps_smmu 0x808 0x0>, + <&apps_smmu 0x810 0x8>, + <&apps_smmu 0xc08 0x0>, + <&apps_smmu 0xc10 0x8>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + camss_endpoint0: endpoint { + status = "disabled"; + }; + }; + + port@1 { + reg = <1>; + + camss_endpoint1: endpoint { + status = "disabled"; + }; + }; + + port@2 { + reg = <2>; + + camss_endpoint2: endpoint { + status = "disabled"; + }; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc"; reg = <0 0x0ad00000 0 0x10000>; From c9e3129720104ce9f8fa556db9d83cb05e527bbb Mon Sep 17 00:00:00 2001 From: Juerg Haefliger Date: Wed, 16 Apr 2025 11:13:35 +0200 Subject: [PATCH 252/308] arm64: dts: qcom: x1e80100-hp-omnibook-x14: Remove invalid bt-en-sleep node Remove the invalid bt-en-sleep node. Not sure how it came into existence but it seems the functionality is covered by the wcn-wlan-bt-en-state node: wcn_wlan_bt_en: wcn-wlan-bt-en-state { pins = "gpio116", "gpio117"; function = "gpio"; drive-strength = <2>; bias-disable; }; This fixes the following warning: arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dtb: pinctrl@f100000: Unevaluated properties are not allowed ('bt-en-sleep' was unexpected) from schema $id: http://devicetree.org/schemas/pinctrl/qcom,x1e80100-tlmm.yaml# Signed-off-by: Juerg Haefliger Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250416-fix-omnibook-dts-v1-1-2409220a7c6f@canonical.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index 28298021cc36..1a187dc3684a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -1429,14 +1429,6 @@ &tlmm { <72 2>, /* Secure EC I2C connection (?) */ <238 1>; /* UFS Reset */ - bt_en_default: bt-en-sleep { - pins = "gpio116"; - function = "gpio"; - output-low; - bias-disable; - drive-strength = <16>; - }; - edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; From 9bdbd5286ea597db6131c197ae9ee8614cce1890 Mon Sep 17 00:00:00 2001 From: Prashanth K Date: Tue, 25 Mar 2025 18:00:15 +0530 Subject: [PATCH 253/308] arm64: dts: qcom: sm8150: Add snps,dis_u3_susphy_quirk During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250325123019.597976-2-prashanth.k@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index e364cd07193a..cdb47359c4c8 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3658,6 +3658,7 @@ usb_1_dwc3: usb@a600000 { interrupts = ; iommus = <&apps_smmu 0x140 0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; @@ -3737,6 +3738,7 @@ usb_2_dwc3: usb@a800000 { interrupts = ; iommus = <&apps_smmu 0x160 0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; From a7dac91e56ae58e1479002e5b94fab73039f2e29 Mon Sep 17 00:00:00 2001 From: Prashanth K Date: Tue, 25 Mar 2025 18:00:16 +0530 Subject: [PATCH 254/308] arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250325123019.597976-3-prashanth.k@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 279a68a7146e..04a30df4362b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2652,6 +2652,7 @@ usb_1_dwc3: usb@a600000 { interrupts = ; iommus = <&apps_smmu 0x0 0x0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; @@ -2730,6 +2731,7 @@ usb_2_dwc3: usb@a800000 { interrupts = ; iommus = <&apps_smmu 0x20 0x0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; From 9588f10adb5b67bea7eeebed2490c20dfbe82e77 Mon Sep 17 00:00:00 2001 From: Prashanth K Date: Tue, 25 Mar 2025 18:00:17 +0530 Subject: [PATCH 255/308] arm64: dts: qcom: sm8450: Add snps,dis_u3_susphy_quirk During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250325123019.597976-4-prashanth.k@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index a94188ecf384..54c6d0fdb2af 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5466,6 +5466,7 @@ usb_1_dwc3: usb@a600000 { interrupts = ; iommus = <&apps_smmu 0x0 0x0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; From ad2011e02dab5ccc9f38848a3d909855a4ae7c8f Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Tue, 25 Mar 2025 18:00:18 +0530 Subject: [PATCH 256/308] arm64: dts: qcom: qcs615: Add snps,dis_u3_susphy_quirk During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Pratham Pratap Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250325123019.597976-5-prashanth.k@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index edfb796d8dd3..7c377f3402c1 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -3600,6 +3600,7 @@ usb_1_dwc3: usb@a600000 { snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; @@ -3661,6 +3662,7 @@ usb_2_dwc3: usb@a800000 { phy-names = "usb2-phy"; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; From 25eee6c64376fcdc375b97c7e1f105e132654563 Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Tue, 25 Mar 2025 18:00:19 +0530 Subject: [PATCH 257/308] arm64: dts: qcom: qdu1000: Add snps,dis_u3_susphy_quirk During device mode initialization on certain QC targets, before the runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} register write fails. As a result, GEVTADDR registers are still 0x0. Upon setting runstop bit, DWC3 controller attempts to write the new events to address 0x0, causing an SMMU fault and system crash. This was initially observed on SM8450 and later reported on few other targets as well. As suggested by Qualcomm HW team, clearing the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register write failures. Address this by setting the snps,dis_u3_susphy_quirk to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year and hasn't exhibited any side effects. Signed-off-by: Pratham Pratap Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250325123019.597976-6-prashanth.k@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 7c8d78fd7ebf..846e5e5899aa 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1022,6 +1022,7 @@ usb_1_dwc3: usb@a600000 { iommus = <&apps_smmu 0xc0 0x0>; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; snps,dis_enblslpm_quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; From d8b462c44a0399e220a44c81cf562b909448bada Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Tue, 6 May 2025 15:37:47 +0200 Subject: [PATCH 258/308] arm64: dts: ipq6018: drop standalone 'smem' node Since commit b5af64fceb04 ("soc: qcom: smem: Support reserved-memory description") the SMEM device can be instantiated directly from a reserved-memory node. The 'smem' node is defined in this way for each modern IPQ SoCs except for IPQ6018. In order to make it inline with the others, move the 'compatible' and the 'hwlock' properties into the respective reserved-memory node, and drop the standalone 'smem' node. Signed-off-by: Gabor Juhos Reviewed-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20250506-ipq6018-drop-smem-v1-1-af99d177be2f@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index a02aa641cb90..7f0faf26b707 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -210,8 +210,11 @@ tz: memory@4a600000 { }; smem_region: memory@4aa00000 { + compatible = "qcom,smem"; reg = <0x0 0x4aa00000 0x0 0x100000>; no-map; + + hwlocks = <&tcsr_mutex 3>; }; q6_region: memory@4ab00000 { @@ -220,12 +223,6 @@ q6_region: memory@4ab00000 { }; }; - smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - hwlocks = <&tcsr_mutex 3>; - }; - soc: soc@0 { #address-cells = <2>; #size-cells = <2>; From 02a8b9894b9cbf4ffcd8661813826494cf49d3a2 Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Sun, 4 May 2025 14:51:18 +0300 Subject: [PATCH 259/308] arm64: dts: qcom: sdm630: Add modem metadata mem Similarly to MSM8998, add and use modem metadata memory region. This does not seemingly affect device functionality. But it fixes DTBs check warning: remoteproc@4080000: memory-region: [[45], [46]] is too short Signed-off-by: Alexey Minnekhanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250504115120.1432282-2-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 2d3820536ddf..8b1a45a4e56e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -509,6 +509,12 @@ zap_shader_region: gpu@fed00000 { reg = <0x0 0xfed00000 0x0 0xa00000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; smem: smem { @@ -1056,7 +1062,7 @@ remoteproc_mss: remoteproc@4080000 { <&rpmpd SDM660_VDDMX>; power-domain-names = "cx", "mx"; - memory-region = <&mba_region>, <&mpss_region>; + memory-region = <&mba_region>, <&mpss_region>, <&mdata_mem>; status = "disabled"; From dbf62a117a1b7f605a98dd1fd1fd6c85ec324ea0 Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Sun, 4 May 2025 14:51:19 +0300 Subject: [PATCH 260/308] arm64: dts: qcom: sdm660-lavender: Add missing USB phy supply Fixes the following dtbs check error: phy@c012000: 'vdda-pll-supply' is a required property Fixes: e5d3e752b050e ("arm64: dts: qcom: sdm660-xiaomi-lavender: Add USB") Signed-off-by: Alexey Minnekhanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250504115120.1432282-3-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 0b4d71c14a77..a9926ad6c6f9 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -107,6 +107,7 @@ &qusb2phy0 { status = "okay"; vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; }; From f5110806b41eaa0eb0ab1bf2787876a580c6246c Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Sun, 4 May 2025 14:51:20 +0300 Subject: [PATCH 261/308] arm64: dts: qcom: sda660-ifc6560: Fix dt-validate warning If you remove clocks property, you should remove clock-names, too. Fixes warning with dtbs check: 'clocks' is a dependency of 'clock-names' Fixes: 34279d6e3f32c ("arm64: dts: qcom: sdm660: Add initial Inforce IFC6560 board support") Signed-off-by: Alexey Minnekhanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250504115120.1432282-4-alexeymin@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 4a5107689069..74cb29cb7f1a 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -175,6 +175,7 @@ &blsp1_dma { * BAM DMA interconnects support is in place. */ /delete-property/ clocks; + /delete-property/ clock-names; }; &blsp1_uart2 { @@ -187,6 +188,7 @@ &blsp2_dma { * BAM DMA interconnects support is in place. */ /delete-property/ clocks; + /delete-property/ clock-names; }; &blsp2_uart1 { From 2ed8ee662660577a701e92917dbc65ca3553507c Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Wed, 30 Apr 2025 10:29:12 +0530 Subject: [PATCH 262/308] arm64: dts: qcom: qcs8300: Add cpufreq scaling node Add cpufreq-hw node to support cpufreq scaling on QCS8300. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250430-qcs8300-cpufreq-scaling-v2-1-ee41566b8c56@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 037cd366a09b..9bc6cf9a3495 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -52,6 +52,7 @@ cpu0: cpu@0 { power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_0: l2-cache { compatible = "cache"; @@ -71,6 +72,7 @@ cpu1: cpu@100 { power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_1: l2-cache { compatible = "cache"; @@ -90,6 +92,7 @@ cpu2: cpu@200 { power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <507>; + qcom,freq-domain = <&cpufreq_hw 2>; l2_2: l2-cache { compatible = "cache"; @@ -109,6 +112,7 @@ cpu3: cpu@300 { power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <507>; + qcom,freq-domain = <&cpufreq_hw 2>; l2_3: l2-cache { compatible = "cache"; @@ -128,6 +132,7 @@ cpu4: cpu@10000 { power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_4: l2-cache { compatible = "cache"; @@ -147,6 +152,7 @@ cpu5: cpu@10100 { power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_5: l2-cache { compatible = "cache"; @@ -166,6 +172,7 @@ cpu6: cpu@10200 { power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_6: l2-cache { compatible = "cache"; @@ -185,6 +192,7 @@ cpu7: cpu@10300 { power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_7: l2-cache { compatible = "cache"; @@ -5279,6 +5287,28 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>, + <0x0 0x18594000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + remoteproc_gpdsp: remoteproc@20c00000 { compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; reg = <0x0 0x20c00000 0x0 0x10000>; From 9f2ae52acd5e6c95ddc55d1cc67f44860940a21b Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Sat, 26 Apr 2025 14:57:58 +0200 Subject: [PATCH 263/308] dt-bindings: arm: qcom: Add Asus Zenbook A14 Document the X1E-78-100 and X1P-42-100/X1-26-100 variants. Acked-by: Krzysztof Kozlowski Signed-off-by: Aleksandrs Vinarskis Link: https://lore.kernel.org/r/20250426130203.37659-3-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 08c329b1e919..bb589021a97a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1133,6 +1133,7 @@ properties: - items: - enum: - asus,vivobook-s15 + - asus,zenbook-a14-ux3407ra - dell,xps13-9345 - hp,omnibook-x14 - lenovo,yoga-slim7x @@ -1144,6 +1145,7 @@ properties: - items: - enum: + - asus,zenbook-a14-ux3407qa - qcom,x1p42100-crd - const: qcom,x1p42100 From 099f3401dc3b7f4b63f9fa8b2f44f244c5ab3e62 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 24 Apr 2025 18:31:14 +0200 Subject: [PATCH 264/308] arm64: dts: qcom: sc7280: add UFS operating points Replace the deprecated freq-table-hz property with an operating points table with all supported frequencies and power levels. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250424-topic-sc7280-upstream-ufs-opps-v1-1-e63494d65f45@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 52 +++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 8e86d75cc6b4..911e104a219d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2364,18 +2364,52 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; + + operating-points-v2 = <&ufs_opp_table>; + qcom,ice = <&ice>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ufs_mem_phy: phy@1d87000 { From 5ce920e6a8db40e4b094c0d863cbd19fdcfbbb7a Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:07 +0200 Subject: [PATCH 265/308] arm64: dts: qcom: x1-crd: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: bd50b1f5b6f3 ("arm64: dts: qcom: x1e80100: Add Compute Reference Device") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-1-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index f73f053a46a0..dbdf542c7ce5 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -846,8 +846,8 @@ vreg_l1j_0p8: ldo1 { vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; From 3ed2a9e03abfeece9e30ebc746f935536f661414 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:08 +0200 Subject: [PATCH 266/308] arm64: dts: qcom: x1e001de-devkit: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: 7b8a31e82b87 ("arm64: dts: qcom: Add X1E001DE Snapdragon Devkit for Windows") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-2-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 74911861a3bf..4693e4c9986a 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -747,8 +747,8 @@ vreg_l1j_0p8: ldo1 { vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; From 0fb9ecf8713a7a458f7378c86e0703467db2ad22 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:09 +0200 Subject: [PATCH 267/308] arm64: dts: qcom: x1e80100-asus-vivobook-s15: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: d0e2f8f62dff ("arm64: dts: qcom: Add device tree for ASUS Vivobook S 15") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-3-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index fb9567817be6..c94ddba5fbf1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -351,8 +351,8 @@ vreg_l1j_0p8: ldo1 { vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; From 4a09dad9d437a13e9cd4383ff7791a816a6e1652 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:10 +0200 Subject: [PATCH 268/308] arm64: dts: qcom: x1e80100-hp-omnibook-x14: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: 6f18b8d4142c ("arm64: dts: qcom: x1e80100-hp-x14: dt for HP Omnibook X Laptop 14") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-4-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index 1a187dc3684a..199e25674352 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -873,8 +873,8 @@ vreg_l1j_0p8: ldo1 { vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; From 4f27ede34ca3369cdcde80c5a4ca84cdb28edbbb Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:11 +0200 Subject: [PATCH 269/308] arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: 45247fe17db2 ("arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-5-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 445d97d67d32..9fb306456e33 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -513,8 +513,8 @@ vreg_l1j_0p8: ldo1 { vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; From efdbeae860bf0278b050c6c9ad5921afba4596d0 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 23 Apr 2025 09:30:12 +0200 Subject: [PATCH 270/308] arm64: dts: qcom: x1e80100-qcp: Fix vreg_l2j_1p2 voltage In the ACPI DSDT table, PPP_RESOURCE_ID_LDO2_J is configured with 1256000 uV instead of the 1200000 uV we have currently in the device tree. Use the same for consistency and correctness. Cc: stable@vger.kernel.org Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250423-x1e-vreg-l2j-voltage-v1-6-24b6a2043025@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 470c4f826d49..c0c8ecb666e1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -773,8 +773,8 @@ vreg_l1j_0p8: ldo1 { vreg_l2j_1p2: ldo2 { regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; regulator-initial-mode = ; }; From f76fdcd2550991c854a698a9f881b1579455fc0a Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 22 Apr 2025 14:25:22 +0300 Subject: [PATCH 271/308] arm64: dts: qcom: x1e001de-devkit: Describe USB retimers resets pin configs Currently, on the X Elite Devkit, the pin configuration of the reset gpios for all three PS8830 USB retimers are left configured by the bootloader. Fix that by describing their pin configuration. Fixes: 019e1ee32fec ("arm64: dts: qcom: x1e001de-devkit: Enable external DP support") Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20250422-x1e001de-devkit-dts-fix-retimer-gpios-v2-1-0129c4f2b6d7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 32 ++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 4693e4c9986a..e17e5fd66f7e 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -789,6 +789,9 @@ typec-mux@8 { reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&rtmr2_default>; + pinctrl-names = "default"; + orientation-switch; retimer-switch; @@ -843,6 +846,9 @@ typec-mux@8 { reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + retimer-switch; orientation-switch; @@ -897,6 +903,9 @@ typec-mux@8 { reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + retimer-switch; orientation-switch; @@ -1018,6 +1027,15 @@ &pcie6a_phy { }; &pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8 V */ + bias-disable; + input-disable; + output-enable; + }; + usb0_3p3_reg_en: usb0-3p3-reg-en-state { pins = "gpio11"; function = "normal"; @@ -1205,6 +1223,20 @@ wake-n-pins { }; }; + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_default: rtmr2-reset-n-active-state { + pins = "gpio185"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { pins = "gpio188"; function = "gpio"; From 635d0c8edf26994dc1dcbc09add9423aa61869b0 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 22 Apr 2025 14:25:23 +0300 Subject: [PATCH 272/308] arm64: dts: qcom: x1e001de-devkit: Fix pin config for USB0 retimer vregs Describe the missing power source, bias and direction for each of the USB0 retimer gpio-controlled voltage regulators related pin configuration. Fixes: 019e1ee32fec ("arm64: dts: qcom: x1e001de-devkit: Enable external DP support") Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20250422-x1e001de-devkit-dts-fix-retimer-gpios-v2-2-0129c4f2b6d7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index e17e5fd66f7e..86b2129600ed 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -1039,6 +1039,10 @@ rtmr0_default: rtmr0-reset-n-active-state { usb0_3p3_reg_en: usb0-3p3-reg-en-state { pins = "gpio11"; function = "normal"; + power-source = <1>; /* 1.8 V */ + bias-disable; + input-disable; + output-enable; }; }; @@ -1046,6 +1050,10 @@ &pmc8380_5_gpios { usb0_pwr_1p15_en: usb0-pwr-1p15-en-state { pins = "gpio8"; function = "normal"; + power-source = <1>; /* 1.8 V */ + bias-disable; + input-disable; + output-enable; }; }; @@ -1053,6 +1061,10 @@ &pm8550ve_9_gpios { usb0_1p8_reg_en: usb0-1p8-reg-en-state { pins = "gpio8"; function = "normal"; + power-source = <1>; /* 1.8 V */ + bias-disable; + input-disable; + output-enable; }; }; From 0d95f64be4176fc98bcc2b4558239800ee93bf32 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sat, 3 May 2025 15:39:28 +0500 Subject: [PATCH 273/308] arm64: dts: qcom: sc7180: Add EL2 overlay for WoA devices WoA devices using sc7180 use android firmware to boot, which notably includes QHEE hypervisor. This means that, so far, Linux-based OS could only boot in EL1 on those devices. However Windows can replace QHEE upon boot with it's own hypervisor, and with the use of tools such as "slbounce", it's possible to do the same for Linux-based OS, in which case some modifications to the DT are necessary to facilitate the absence of QHEE services. Add a EL2-specific DT overlay and apply it to sc7180 WoA devices to create -el2.dtb for each of them alongside "normal" dtb. Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20250503-sc-el2-overlays-v2-1-24e9b4572e15@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 3 ++- arch/arm64/boot/dts/qcom/sc7180-el2.dtso | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index adb4d026bcc4..06da6f6791d6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -138,7 +138,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb +sc7180-acer-aspire1-el2-dtbs := sc7180-acer-aspire1.dtb sc7180-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb sc7180-acer-aspire1-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-el2.dtso b/arch/arm64/boot/dts/qcom/sc7180-el2.dtso new file mode 100644 index 000000000000..49a98676ca4d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-el2.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * sc7180 specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +/* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ +&gpu { + zap-shader { + status = "disabled"; + }; +}; + +/* Venus can be used in EL2 if booted similarly to ChromeOS devices. */ +&venus { + video-firmware { + iommus = <&apps_smmu 0x0c42 0x0>; + }; +}; From 8a401135001c65203f3fd210d482bc7eae1bfc56 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sat, 3 May 2025 15:39:29 +0500 Subject: [PATCH 274/308] arm64: dts: qcom: sc8280xp: Add PCIe IOMMU sc8280xp has an SMMUv3 connected to PCIe which is normally controlled by QHEE and is thus transparent to the OS. However if we boot Linux in EL2, without QHEE, we need to manage this IOMMU ourselves. To make that easier, and since the hardware actually exists, just not "usually" managed by Linux, describe it in the dts as "reserved". Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20250503-sc-el2-overlays-v2-2-24e9b4572e15@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 35ef31d4ecf2..27d21e1a2d50 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4927,6 +4927,20 @@ rx-pins { }; }; + pcie_smmu: iommu@14f80000 { + compatible = "arm,smmu-v3"; + reg = <0 0x14f80000 0 0x80000>; + #iommu-cells = <1>; + interrupts = , + , + ; + interrupt-names = "eventq", + "gerror", + "cmdq-sync"; + dma-coherent; + status = "reserved"; /* Controlled by QHEE. */ + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; From 263780f3189730f2efa511181c3970384e54afde Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sat, 3 May 2025 15:39:30 +0500 Subject: [PATCH 275/308] arm64: dts: qcom: sc8280xp: Add EL2 overlay for WoA devices WoA devices using sc8280xp use android firmware to boot, which notably includes QHEE hypervisor. This means that, so far, Linux-based OS could only boot in EL1 on those devices. However Windows can replace QHEE upon boot with it's own hypervisor, and with the use of tools such as "slbounce", it's possible to do the same for Linux-based OS, in which case some modifications to the DT are necessary to facilitate the absence of QHEE services. Add a EL2-specific DT overlay and apply it to sc8280xp WoA devices to create -el2.dtb for each of them alongside "normal" dtb. Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20250503-sc-el2-overlays-v2-3-24e9b4572e15@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 15 +++++--- arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso | 44 ++++++++++++++++++++++ 2 files changed, 54 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 06da6f6791d6..12d9ed1129b4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -205,11 +205,16 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8180x-lenovo-flex-5g.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-huawei-gaokun3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-arcata.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-blackrock.dtb +sc8280xp-crd-el2-dtbs := sc8280xp-crd.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb sc8280xp-crd-el2.dtb +sc8280xp-huawei-gaokun3-el2-dtbs := sc8280xp-huawei-gaokun3.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-huawei-gaokun3.dtb sc8280xp-huawei-gaokun3-el2.dtb +sc8280xp-lenovo-thinkpad-x13s-el2-dtbs := sc8280xp-lenovo-thinkpad-x13s.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb sc8280xp-lenovo-thinkpad-x13s-el2.dtb +sc8280xp-microsoft-arcata-el2-dtbs := sc8280xp-microsoft-arcata.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-arcata.dtb sc8280xp-microsoft-arcata-el2.dtb +sc8280xp-microsoft-blackrock-el2-dtbs := sc8280xp-microsoft-blackrock.dtb sc8280xp-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-microsoft-blackrock.dtb sc8280xp-microsoft-blackrock-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm450-lenovo-tbx605f.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso b/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso new file mode 100644 index 000000000000..25d1fa4bc205 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc8280xp-el2.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * sc8280xp specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +/* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ +&gpu { + zap-shader { + status = "disabled"; + }; +}; + +/* + * When running under QHEE, this IOMMU is controlled by the firmware, + * however when we take ownership of it in EL2, we need to configure + * it properly to use PCIe. + */ +&pcie2a { + iommu-map = <0 &pcie_smmu 0x20000 0x10000>; +}; + +&pcie2b { + iommu-map = <0 &pcie_smmu 0x30000 0x10000>; +}; + +&pcie3a { + iommu-map = <0 &pcie_smmu 0x40000 0x10000>; +}; + +&pcie3b { + iommu-map = <0 &pcie_smmu 0x50000 0x10000>; +}; + +&pcie4 { + iommu-map = <0 &pcie_smmu 0x60000 0x10000>; +}; + +&pcie_smmu { + status = "okay"; +}; From 428f95f41f3024a8378bb4c4803fe269fcacaa85 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sat, 3 May 2025 15:39:31 +0500 Subject: [PATCH 276/308] arm64: dts: qcom: x1e80100: Add PCIe IOMMU x1e80100 has an SMMUv3 connected to PCIe which is normally controlled by Gunyah and is thus transparent to the OS. However if we boot Linux in EL2, without Gunyah, we need to manage this IOMMU ourselves. To make that easier, and since the hardware actually exists, just not "usually" managed by Linux, describe it in the dts as "reserved". Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20250503-sc-el2-overlays-v2-4-24e9b4572e15@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 46b79fce92c9..7a3e75294be5 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -7940,6 +7940,20 @@ apps_smmu: iommu@15000000 { dma-coherent; }; + pcie_smmu: iommu@15400000 { + compatible = "arm,smmu-v3"; + reg = <0 0x15400000 0 0x80000>; + #iommu-cells = <1>; + interrupts = , + , + ; + interrupt-names = "eventq", + "gerror", + "cmdq-sync"; + dma-coherent; + status = "reserved"; /* Controlled by Gunyah. */ + }; + intc: interrupt-controller@17000000 { compatible = "arm,gic-v3"; reg = <0 0x17000000 0 0x10000>, /* GICD */ From e01acd8f3cc1364b9147d3eb8913fdb935851ecd Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Sat, 3 May 2025 15:39:32 +0500 Subject: [PATCH 277/308] arm64: dts: qcom: x1e/x1p: Add EL2 overlay for WoA devices WoA devices using x1e/x1p use android firmware to boot, which notably includes Gunyah hypervisor. This means that, so far, Linux-based OS could only boot in EL1 on those devices. However Windows can replace Gunyah upon boot with it's own hypervisor, and with the use of tools such as "slbounce", it's possible to do the same for Linux-based OS, in which case some modifications to the DT are necessary to facilitate the absence of Gunyah services. Add a EL2-specific DT overlay and apply it to x1e/x1p WoA devices to create -el2.dtb for each of them alongside "normal" dtb. Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20250503-sc-el2-overlays-v2-5-24e9b4572e15@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 36 ++++++++++++------ arch/arm64/boot/dts/qcom/x1-el2.dtso | 52 ++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 3 files changed, 77 insertions(+), 13 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/x1-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 12d9ed1129b4..4300b29397c6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -299,15 +299,27 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s-oled.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb -dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb +x1e001de-devkit-el2-dtbs := x1e001de-devkit.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb x1e001de-devkit-el2.dtb +x1e78100-lenovo-thinkpad-t14s-el2-dtbs := x1e78100-lenovo-thinkpad-t14s.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb x1e78100-lenovo-thinkpad-t14s-el2.dtb +x1e78100-lenovo-thinkpad-t14s-oled-el2-dtbs := x1e78100-lenovo-thinkpad-t14s-oled.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s-oled.dtb x1e78100-lenovo-thinkpad-t14s-oled-el2.dtb +x1e80100-asus-vivobook-s15-el2-dtbs := x1e80100-asus-vivobook-s15.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb x1e80100-asus-vivobook-s15-el2.dtb +x1e80100-crd-el2-dtbs := x1e80100-crd.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb x1e80100-crd-el2.dtb +x1e80100-dell-xps13-9345-el2-dtbs := x1e80100-dell-xps13-9345.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb x1e80100-dell-xps13-9345-el2.dtb +x1e80100-hp-omnibook-x14-el2-dtbs := x1e80100-hp-omnibook-x14.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omnibook-x14-el2.dtb +x1e80100-lenovo-yoga-slim7x-el2-dtbs := x1e80100-lenovo-yoga-slim7x.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb +x1e80100-microsoft-romulus13-el2-dtbs := x1e80100-microsoft-romulus13.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb x1e80100-microsoft-romulus13-el2.dtb +x1e80100-microsoft-romulus15-el2-dtbs := x1e80100-microsoft-romulus15.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb x1e80100-microsoft-romulus15-el2.dtb +x1e80100-qcp-el2-dtbs := x1e80100-qcp.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb x1e80100-qcp-el2.dtb +x1p42100-crd-el2-dtbs := x1p42100-crd.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb x1p42100-crd-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso new file mode 100644 index 000000000000..380441deca65 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * x1 specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +/* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ +&gpu_zap_shader { + status = "disabled"; +}; + +/* + * When running under Gunyah, this IOMMU is controlled by the firmware, + * however when we take ownership of it in EL2, we need to configure + * it properly to use PCIe. + * + * Additionally, it seems like ITS emulation in Gunyah is broken so we + * can't use MSI on some PCIe controllers in EL1. But we can add them + * here for EL2. + */ +&pcie3 { + iommu-map = <0 &pcie_smmu 0x30000 0x10000>; + msi-map = <0 &gic_its 0xb0000 0x10000>; +}; + +&pcie4 { + iommu-map = <0 &pcie_smmu 0x40000 0x10000>; +}; + +&pcie5 { + iommu-map = <0 &pcie_smmu 0x50000 0x10000>; + msi-map = <0 &gic_its 0xd0000 0x10000>; +}; + +&pcie6a { + iommu-map = <0 &pcie_smmu 0x60000 0x10000>; +}; + +&pcie_smmu { + status = "okay"; +}; + +/* + * The "SBSA watchdog" is implemented in software in Gunyah + * and can't be used when running in EL2. + */ +&sbsa_watchdog { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 7a3e75294be5..c04a2615ca77 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -8163,7 +8163,7 @@ frame@1780d000 { }; }; - watchdog@1c840000 { + sbsa_watchdog: watchdog@1c840000 { compatible = "arm,sbsa-gwdt"; reg = <0 0x1c840000 0 0x1000>, <0 0x1c850000 0 0x1000>; From 181faec4cc9d90dad0ec7f7c8124269c0ba2e107 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 22 Apr 2025 14:03:16 +0300 Subject: [PATCH 278/308] arm64: dts: qcom: x1e80100: Fix PCIe 3rd controller DBI size According to documentation, the DBI range size is 0xf20. So fix it. Cc: stable@vger.kernel.org # 6.14 Fixes: f8af195beeb0 ("arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100") Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250422-x1e80100-dts-fix-pcie3-dbi-size-v1-1-c197701fd7e4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index c04a2615ca77..06175b33bd92 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3126,7 +3126,7 @@ pcie3: pcie@1bd0000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0x0 0x01bd0000 0x0 0x3000>, - <0x0 0x78000000 0x0 0xf1d>, + <0x0 0x78000000 0x0 0xf20>, <0x0 0x78000f40 0x0 0xa8>, <0x0 0x78001000 0x0 0x1000>, <0x0 0x78100000 0x0 0x100000>, From 8d88f6c9c5e774420673a37510b22015b1edd569 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 22 Apr 2025 13:03:48 +0200 Subject: [PATCH 279/308] arm64: dts: qcom: msm8916/39: Move UART pinctrl to board files In preparation of adding a new console UART specific pinctrl template, move the pinctrl reference to the board DT part. This forces people porting new boards to consider what exactly they need for their board. No functional change for the boards upstream. Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250422-msm8916-console-pinctrl-v2-1-f345b7a53c91@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 6 ++++++ arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts | 6 ++++++ arch/arm64/boot/dts/qcom/apq8039-t2.dts | 6 ++++++ arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi | 3 +++ arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 3 +++ .../arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi | 3 +++ arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi | 3 +++ arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi | 3 +++ arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 3 +++ arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi | 3 +++ arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 ------ arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts | 3 +++ arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi | 3 +++ arch/arm64/boot/dts/qcom/msm8939.dtsi | 6 ------ 28 files changed, 87 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index aba08424aa38..6175b1b9d7c6 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -222,11 +222,17 @@ &blsp_spi5 { &blsp_uart1 { status = "okay"; label = "LS-UART0"; + pinctrl-0 = <&blsp_uart1_default>; + pinctrl-1 = <&blsp_uart1_sleep>; + pinctrl-names = "default", "sleep"; }; &blsp_uart2 { status = "okay"; label = "LS-UART1"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; }; &camss { diff --git a/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts b/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts index 75c6137e5a11..7a03893530c7 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts @@ -190,11 +190,17 @@ tpm@0 { }; &blsp_uart1 { + pinctrl-0 = <&blsp_uart1_default>; + pinctrl-1 = <&blsp_uart1_sleep>; + pinctrl-names = "default", "sleep"; label = "UART0"; status = "okay"; }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; label = "UART1"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index 4f82bb668616..f656eca59ee2 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -116,6 +116,9 @@ &blsp_i2c5 { }; &blsp_uart1 { + pinctrl-0 = <&blsp_uart1_default>; + pinctrl-1 = <&blsp_uart1_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; @@ -128,6 +131,9 @@ &blsp_uart1_sleep { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index b4ce14a79370..9b82468ace3e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -133,6 +133,9 @@ touchscreen@38 { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 3459145516a1..1c2f8e8f9b26 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -214,6 +214,9 @@ led@1 { &blsp_uart2 { status = "okay"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; }; &mpss_mem { diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index 77618c7374df..f7a9ee0dba09 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -130,6 +130,9 @@ touchscreen@38 { &blsp_uart2 { status = "okay"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; }; &mpss_mem { diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index f7be7e371820..e5ca1ca0d997 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -131,6 +131,9 @@ touchscreen@38 { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index bf7fc89dd106..f75e60b5d1b3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -214,6 +214,9 @@ nfc@28 { &blsp_uart2 { status = "okay"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; }; &lpass { diff --git a/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts b/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts index a823a1c40208..7c49b4cb27cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts @@ -59,6 +59,9 @@ reg_sd_vmmc: regulator-sdcard-vmmc { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts b/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts index 07345e694f6f..6e55d37f588c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts @@ -112,6 +112,9 @@ touchscreen@34 { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 7f0c2c1b8a94..4576178cc9b0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -254,6 +254,9 @@ rmi4-f12@12 { &blsp_uart2 { status = "okay"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; }; &pm8916_bms { diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 2cc54eaf7202..e0dacdf55245 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -178,6 +178,9 @@ imu@68 { &blsp_uart2 { status = "okay"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; }; &mpss_mem { diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi index 6a27d0ecd2ad..48134e5ff524 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi @@ -69,6 +69,9 @@ rmi4-f11@11 { }; &blsp_uart1 { + pinctrl-0 = <&blsp_uart1_default>; + pinctrl-1 = <&blsp_uart1_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index c11a845e91bb..c115142df364 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -23,5 +23,8 @@ chosen { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index e6355e5e2177..58a548d220a4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -302,6 +302,9 @@ charger: charger { &blsp_uart2 { status = "okay"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; }; &gpu { diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index 7a7e99b015d9..4290ae7782d6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -304,6 +304,9 @@ charger: charger { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index fbd2caf405d5..30e34574999c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -116,6 +116,9 @@ fuelgauge@36 { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index 5ca2ada266f4..d4af7856f5f3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -135,6 +135,9 @@ touchscreen: touchscreen@50 { &blsp_uart2 { status = "okay"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; }; &mpss_mem { diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index caad1dead2e0..45c3b3387b52 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -319,6 +319,9 @@ rt5033_charger: charger { &blsp_uart2 { status = "okay"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; }; &gpu { diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index c77ed04bb6c3..2bfe56da8f6c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -72,6 +72,9 @@ &bam_dmux_dma { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi index 1a7c347dc3f0..f5caac42bbad 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi @@ -93,6 +93,9 @@ touchscreen@38 { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 510b3b3c4e3c..10d0974334ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -169,6 +169,9 @@ led@2 { &blsp_uart2 { status = "okay"; + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; }; &mpss_mem { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c89f9e92e832..733c17d04956 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -2159,9 +2159,6 @@ blsp_uart1: serial@78af000 { clock-names = "core", "iface"; dmas = <&blsp_dma 0>, <&blsp_dma 1>; dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_uart1_default>; - pinctrl-1 = <&blsp_uart1_sleep>; status = "disabled"; }; @@ -2173,9 +2170,6 @@ blsp_uart2: serial@78b0000 { clock-names = "core", "iface"; dmas = <&blsp_dma 2>, <&blsp_dma 3>; dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts b/arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts index 3cec51891aed..9f647027d082 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts @@ -126,6 +126,9 @@ touchscreen@1c { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts b/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts index b845da4fa23e..f59647b5b7df 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts @@ -243,6 +243,9 @@ touchscreen@4a { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts index ceba6e73b211..3d9cbe7fdad8 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts @@ -373,6 +373,9 @@ charger: charger { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi b/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi index 800e0747a2f7..cbefe34327ba 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi @@ -126,6 +126,9 @@ touchscreen: touchscreen@38 { }; &blsp_uart2 { + pinctrl-0 = <&blsp_uart2_default>; + pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index ca478db63be4..67ff2ffc6e45 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1770,9 +1770,6 @@ blsp_uart1: serial@78af000 { clock-names = "core", "iface"; dmas = <&blsp_dma 0>, <&blsp_dma 1>; dma-names = "tx", "rx"; - pinctrl-0 = <&blsp_uart1_default>; - pinctrl-1 = <&blsp_uart1_sleep>; - pinctrl-names = "default", "sleep"; status = "disabled"; }; @@ -1784,9 +1781,6 @@ blsp_uart2: serial@78b0000 { clock-names = "core", "iface"; dmas = <&blsp_dma 2>, <&blsp_dma 3>; dma-names = "tx", "rx"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; - pinctrl-names = "default", "sleep"; status = "disabled"; }; From 5c0c8b7a315ff63e01e9a608f78dea16daa57aed Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 22 Apr 2025 13:03:49 +0200 Subject: [PATCH 280/308] arm64: dts: qcom: msm8916/39: Introduce new UART console pinctrl At the moment, msm8916/39.dtsi have two inconsistent UART pinctrl templates that are used by all the boards: - &blsp_uart1_default configures all 4 pins (TX, RX, CTS, RTS), some boards then limit this to just RX and TX - &blsp_uart2_default only configures 2 pins (TX, RX), even though UART2 also supports CTS/RTS It's difficult to define a generic pinctrl template for all UART use cases, since they are quite different in practice. The main use case for most of the 40+ MSM8916/39-based boards upstream is the UART debug console. The current generic template is lacking some properties to work properly: - bias-pull-up for RX: Generally, UART is push-pull and does not need pull up/down. Both sides drive TX, so RX should never be floating. This is why the current pinctrl in msm8916/39.dtsi uses bias-disable. However, this assumes that UART is always connected. For the debug console this will be rarely the case on mobile devices, only during debugging sessions. The rest of the time, the RX pin is floating. This has never caused massive problems, but it's obvious now that this needs fixing: (1) In U-Boot, we have been fighting with problems with autoboot for years. Most of the time, there is a single \0 byte ("break event") read during boot, which interrupts the autoboot process. I tried to work around that by inserting some random delay [1], but it turned out this is also not working reliably on all boards. What happens is: Since RX is floating, it switches randomly between high or low. A long low state is interpreted as "break event" (\0). (2) In postmarketOS, we used to have the "magic SysRq key" enabled by default for the serial console. We had to disable this at some point, because there was a small number of users who were reporting sysrq spam in the kernel log, possibly even crashes/panics triggered by sysrq. What likely happened is: SysRq is triggered by sending a "break event", like in (1). With enough luck, you could even trigger any of the SysRq actions if the RX pin switches between high and low (e.g. because of noise introduced by the LTE radio close by). We can fix this using bias-pull-up, but this may be unneeded, unexpected, or even unwanted for other UART use cases. - bootph-all: U-Boot needs to know which pinctrl to apply during early boot stages, so we should specify "bootph-all" for the console UART pinctrl. Without bootph-all, the bias-pull-up won't be applied early enough in U-Boot to avoid the problem with autoboot in point (1) above. It doesn't make sense to specify this for the other UART instances. bootph-all is a generic property documented in dt-schema bootph.yaml. Define these two additional properties only for the debug UART console, by defining a new pinctrl template specifically for that. In the following commits, boards will be converted to use these where appropriate. [1]: https://source.denx.de/u-boot/u-boot/-/commit/ad7e967738a9c639e07cf50b83ffccdf9a8537b0 Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250422-msm8916-console-pinctrl-v2-2-f345b7a53c91@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 45 ++++++++++++++++++++++++++- arch/arm64/boot/dts/qcom/msm8939.dtsi | 45 ++++++++++++++++++++++++++- 2 files changed, 88 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 733c17d04956..07ae0b921afa 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1247,6 +1247,31 @@ blsp_uart1_sleep: blsp-uart1-sleep-state { bias-pull-down; }; + blsp_uart1_console_default: blsp-uart1-console-default-state { + tx-pins { + pins = "gpio0"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + bootph-all; + }; + + rx-pins { + pins = "gpio1"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-pull-up; + bootph-all; + }; + }; + + blsp_uart1_console_sleep: blsp-uart1-console-sleep-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + blsp_uart2_default: blsp-uart2-default-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; @@ -1254,7 +1279,25 @@ blsp_uart2_default: blsp-uart2-default-state { bias-disable; }; - blsp_uart2_sleep: blsp-uart2-sleep-state { + blsp_uart2_console_default: blsp-uart2-console-default-state { + tx-pins { + pins = "gpio4"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + bootph-all; + }; + + rx-pins { + pins = "gpio5"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-pull-up; + bootph-all; + }; + }; + + blsp_uart2_sleep: blsp_uart2_console_sleep: blsp-uart2-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 67ff2ffc6e45..52a99aea210e 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -919,6 +919,31 @@ blsp_uart1_sleep: blsp-uart1-sleep-state { bias-pull-down; }; + blsp_uart1_console_default: blsp-uart1-console-default-state { + tx-pins { + pins = "gpio0"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + bootph-all; + }; + + rx-pins { + pins = "gpio1"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-pull-up; + bootph-all; + }; + }; + + blsp_uart1_console_sleep: blsp-uart1-console-sleep-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + blsp_uart2_default: blsp-uart2-default-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; @@ -926,7 +951,25 @@ blsp_uart2_default: blsp-uart2-default-state { bias-disable; }; - blsp_uart2_sleep: blsp-uart2-sleep-state { + blsp_uart2_console_default: blsp-uart2-console-default-state { + tx-pins { + pins = "gpio4"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + bootph-all; + }; + + rx-pins { + pins = "gpio5"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-pull-up; + bootph-all; + }; + }; + + blsp_uart2_sleep: blsp_uart2_console_sleep: blsp-uart2-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>; From 2b8d22ef1687768e4b572d01cd2432eb86340dd1 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 22 Apr 2025 13:03:50 +0200 Subject: [PATCH 281/308] arm64: dts: qcom: msm8919/39: Use UART2 console pinctrl where appropriate Convert the majority of MSM8916/39-based boards, which use UART2 with 2 pins (TX, RX) for the debug UART console. This adds the needed bias-pull-up and bootph-all properties to avoid garbage input when UART is disconnected. apq8016-schneider-hmibsc.dts does not use UART2 as a debug console, so it's left as-is in this commit. Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250422-msm8916-console-pinctrl-v2-3-f345b7a53c91@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 4 ++-- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi | 4 ++-- 24 files changed, 48 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 6175b1b9d7c6..f12a5e2b1e8c 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -230,8 +230,8 @@ &blsp_uart1 { &blsp_uart2 { status = "okay"; label = "LS-UART1"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; }; diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index f656eca59ee2..4aa0ad19bc0f 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -131,8 +131,8 @@ &blsp_uart1_sleep { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index 9b82468ace3e..3a6eba904641 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -133,8 +133,8 @@ touchscreen@38 { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 1c2f8e8f9b26..2de8b6f9531b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -214,8 +214,8 @@ led@1 { &blsp_uart2 { status = "okay"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index f7a9ee0dba09..29d61f8d5dc9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -130,8 +130,8 @@ touchscreen@38 { &blsp_uart2 { status = "okay"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index e5ca1ca0d997..742a325245c5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -131,8 +131,8 @@ touchscreen@38 { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index f75e60b5d1b3..aa414b5d7ee4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -214,8 +214,8 @@ nfc@28 { &blsp_uart2 { status = "okay"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts b/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts index 7c49b4cb27cb..22bc73b94344 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-lg-c50.dts @@ -59,8 +59,8 @@ reg_sd_vmmc: regulator-sdcard-vmmc { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts b/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts index 6e55d37f588c..c50374979939 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-lg-m216.dts @@ -112,8 +112,8 @@ touchscreen@34 { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 4576178cc9b0..eb449112a226 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -254,8 +254,8 @@ rmi4-f12@12 { &blsp_uart2 { status = "okay"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index e0dacdf55245..887764dc55b2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -178,8 +178,8 @@ imu@68 { &blsp_uart2 { status = "okay"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index c115142df364..63d476523544 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -23,8 +23,8 @@ chosen { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 58a548d220a4..6f75707b6f9b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -302,8 +302,8 @@ charger: charger { &blsp_uart2 { status = "okay"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index 4290ae7782d6..fb790b02736a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -304,8 +304,8 @@ charger: charger { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index 30e34574999c..ff9679d3f664 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -116,8 +116,8 @@ fuelgauge@36 { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index d4af7856f5f3..697f25d51d9d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -135,8 +135,8 @@ touchscreen: touchscreen@50 { &blsp_uart2 { status = "okay"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 45c3b3387b52..71b5c98458ff 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -319,8 +319,8 @@ rt5033_charger: charger { &blsp_uart2 { status = "okay"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index 2bfe56da8f6c..5719933fa8e0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -72,8 +72,8 @@ &bam_dmux_dma { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi index f5caac42bbad..ebe85cd85ddf 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt865x8.dtsi @@ -93,8 +93,8 @@ touchscreen@38 { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index 10d0974334ab..68c8856d4c2e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -169,8 +169,8 @@ led@2 { &blsp_uart2 { status = "okay"; - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts b/arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts index 9f647027d082..18381a66daef 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-huawei-kiwi.dts @@ -126,8 +126,8 @@ touchscreen@1c { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts b/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts index f59647b5b7df..13422a19c26a 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-longcheer-l9100.dts @@ -243,8 +243,8 @@ touchscreen@4a { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts index 3d9cbe7fdad8..07613080e79e 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts @@ -373,8 +373,8 @@ charger: charger { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi b/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi index cbefe34327ba..a5187355f9fa 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939-wingtech-wt82918.dtsi @@ -126,8 +126,8 @@ touchscreen: touchscreen@38 { }; &blsp_uart2 { - pinctrl-0 = <&blsp_uart2_default>; - pinctrl-1 = <&blsp_uart2_sleep>; + pinctrl-0 = <&blsp_uart2_console_default>; + pinctrl-1 = <&blsp_uart2_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; From fe848d64cc6516cd56f38d23cfb544a68231a6e8 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 22 Apr 2025 13:03:51 +0200 Subject: [PATCH 282/308] arm64: dts: qcom: msm8916-motorola: Use UART1 console pinctrl The Motorola MSM8916-based smartphones all use UART1 with 2 pins (TX, RX) as debug UART console, so make use of the new &blsp_uart1_console_default template. This applies the needed bias-pull-up to avoid garbage input, bootph-all for U-Boot and avoids having to override the UART pins. Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250422-msm8916-console-pinctrl-v2-4-f345b7a53c91@linaro.org Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/msm8916-motorola-common.dtsi | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi index 48134e5ff524..4e202e7ed7db 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi @@ -69,8 +69,8 @@ rmi4-f11@11 { }; &blsp_uart1 { - pinctrl-0 = <&blsp_uart1_default>; - pinctrl-1 = <&blsp_uart1_sleep>; + pinctrl-0 = <&blsp_uart1_console_default>; + pinctrl-1 = <&blsp_uart1_console_sleep>; pinctrl-names = "default", "sleep"; status = "okay"; }; @@ -132,14 +132,6 @@ &wcnss_mem { status = "okay"; }; -/* CTS/RTX are not used */ -&blsp_uart1_default { - pins = "gpio0", "gpio1"; -}; -&blsp_uart1_sleep { - pins = "gpio0", "gpio1"; -}; - &tlmm { gpio_keys_default: gpio-keys-default-state { pins = "gpio107"; From 979b65d8f416353c6b44ec5c0ddc837b2d20ab47 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 22 Apr 2025 13:03:52 +0200 Subject: [PATCH 283/308] arm64: dts: qcom: msm8916: Drop generic UART pinctrl templates Remove the generic UART pinctrl templates from msm8916.dtsi and copy the definition for the custom UART use cases into the board DT files. This makes it clear that the set of pins/pull etc are specific to the board and UART use case. No functional change. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250422-msm8916-console-pinctrl-v2-5-f345b7a53c91@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 15 ++++++++ .../dts/qcom/apq8016-schneider-hmibsc.dts | 35 ++++++++++++++++--- arch/arm64/boot/dts/qcom/msm8916.dtsi | 24 +------------ 3 files changed, 47 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index f12a5e2b1e8c..b0c594c5f236 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -597,6 +597,21 @@ &tlmm { "USR_LED_2_CTRL", /* GPIO 120 */ "SB_HS_ID"; + blsp_uart1_default: blsp-uart1-default-state { + /* TX, RX, CTS_N, RTS_N */ + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart1_sleep: blsp-uart1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + sdc2_cd_default: sdc2-cd-default-state { pins = "gpio38"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts b/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts index 7a03893530c7..ce75046ffdac 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts @@ -373,6 +373,37 @@ adv7533_switch_suspend: adv7533-switch-suspend-state { bias-disable; }; + blsp_uart1_default: blsp-uart1-default-state { + /* TX, RX, CTS_N, RTS_N */ + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + bootph-all; + }; + + blsp_uart1_sleep: blsp-uart1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + blsp_uart2_default: blsp-uart2-default-state { + /* TX, RX */ + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart2_sleep: blsp-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + msm_key_volp_n_default: msm-key-volp-n-default-state { pins = "gpio107"; function = "gpio"; @@ -469,10 +500,6 @@ &blsp_i2c6_default { drive-strength = <16>; }; -&blsp_uart1_default { - bootph-all; -}; - /* Enable CoreSight */ &cti0 { status = "okay"; }; &cti1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 07ae0b921afa..de9fdc0dfc5f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1232,21 +1232,6 @@ blsp_spi6_sleep: blsp-spi6-sleep-state { bias-pull-down; }; - blsp_uart1_default: blsp-uart1-default-state { - /* TX, RX, CTS_N, RTS_N */ - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "blsp_uart1"; - drive-strength = <16>; - bias-disable; - }; - - blsp_uart1_sleep: blsp-uart1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - blsp_uart1_console_default: blsp-uart1-console-default-state { tx-pins { pins = "gpio0"; @@ -1272,13 +1257,6 @@ blsp_uart1_console_sleep: blsp-uart1-console-sleep-state { bias-pull-down; }; - blsp_uart2_default: blsp-uart2-default-state { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - drive-strength = <16>; - bias-disable; - }; - blsp_uart2_console_default: blsp-uart2-console-default-state { tx-pins { pins = "gpio4"; @@ -1297,7 +1275,7 @@ rx-pins { }; }; - blsp_uart2_sleep: blsp_uart2_console_sleep: blsp-uart2-sleep-state { + blsp_uart2_console_sleep: blsp-uart2-console-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>; From f7f65536124db6a5666992f0d6fd9595fbbf067a Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 22 Apr 2025 13:03:53 +0200 Subject: [PATCH 284/308] arm64: dts: qcom: msm8939: Drop generic UART pinctrl templates Remove the generic UART pinctrl templates from msm8939.dtsi and copy the definition for the custom UART use cases into the board DT files. This makes it clear that the set of pins/pull etc are specific to the board and UART use case. No functional change. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250422-msm8916-console-pinctrl-v2-6-f345b7a53c91@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 22 ++++++++++++++-------- arch/arm64/boot/dts/qcom/msm8939.dtsi | 23 +---------------------- 2 files changed, 15 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index 4aa0ad19bc0f..38c281f0fe65 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -122,14 +122,6 @@ &blsp_uart1 { status = "okay"; }; -&blsp_uart1_default { - pins = "gpio0", "gpio1"; -}; - -&blsp_uart1_sleep { - pins = "gpio0", "gpio1"; -}; - &blsp_uart2 { pinctrl-0 = <&blsp_uart2_console_default>; pinctrl-1 = <&blsp_uart2_console_sleep>; @@ -329,6 +321,20 @@ &tlmm { "USBC_GPIO7_1V8", /* GPIO_120 */ "NC"; + blsp_uart1_default: blsp-uart1-default-state { + pins = "gpio0", "gpio1"; + function = "blsp_uart1"; + drive-strength = <16>; + bias-disable; + }; + + blsp_uart1_sleep: blsp-uart1-sleep-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + pinctrl_backlight: backlight-state { pins = "gpio98"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 52a99aea210e..68b92fdb996c 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -905,20 +905,6 @@ blsp_spi6_sleep: blsp-spi6-sleep-state { bias-pull-down; }; - blsp_uart1_default: blsp-uart1-default-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "blsp_uart1"; - drive-strength = <16>; - bias-disable; - }; - - blsp_uart1_sleep: blsp-uart1-sleep-state { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - blsp_uart1_console_default: blsp-uart1-console-default-state { tx-pins { pins = "gpio0"; @@ -944,13 +930,6 @@ blsp_uart1_console_sleep: blsp-uart1-console-sleep-state { bias-pull-down; }; - blsp_uart2_default: blsp-uart2-default-state { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - drive-strength = <16>; - bias-disable; - }; - blsp_uart2_console_default: blsp-uart2-console-default-state { tx-pins { pins = "gpio4"; @@ -969,7 +948,7 @@ rx-pins { }; }; - blsp_uart2_sleep: blsp_uart2_console_sleep: blsp-uart2-sleep-state { + blsp_uart2_console_sleep: blsp-uart2-console-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>; From bd4718d97d308fdc20ddcd471444b3e398ce877d Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Wed, 23 Apr 2025 00:31:35 +0300 Subject: [PATCH 285/308] dt-bindings: arm: qcom: Add SM7150 Google Pixel 4a Google Pixel 4a (google,sunfish) is a smartphone based on the SM7150 SoC Signed-off-by: Danila Tikhonov Link: https://lore.kernel.org/r/20250422213137.80366-15-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index bb589021a97a..a61c85a47e2e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -90,6 +90,7 @@ description: | sm6350 sm6375 sm7125 + sm7150 sm7225 sm7325 sm8150 @@ -1040,6 +1041,11 @@ properties: - xiaomi,joyeuse - const: qcom,sm7125 + - items: + - enum: + - google,sunfish + - const: qcom,sm7150 + - items: - enum: - fairphone,fp4 From 8881698cbd8df8966bcc5fd6b500f2b048d5f0fe Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 4 Apr 2025 10:42:22 +0200 Subject: [PATCH 286/308] arm64: dts: qcom: sc7280: Stop setting dmic01 pinctrl for va-macro There's devices that don't have a DMIC connected to va-macro, so stop setting the pinctrl in sc7280.dtsi, but move it to the devices that actually are using it. No change in functionality is expected, just some boards with disabled va-macro are losing the pinctrl (herobrine-r1, villager-r0, zombie*). Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250404-sc7280-va-dmic01-v1-1-2862ddd20c48@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi | 3 +++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 --- 4 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi index a90c70b1b73e..0e07429982bd 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi @@ -139,6 +139,7 @@ &lpass_va_macro { vdd-micb-supply = <&pp1800_l2c>; pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>, <&lpass_dmic23_clk>, <&lpass_dmic23_data>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi index 020ef666e35f..ce48e4cda170 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi @@ -141,6 +141,9 @@ &lpass_tx_macro { }; &lpass_va_macro { + pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 7370aa0dbf0e..90e5b9ab5b84 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -412,6 +412,8 @@ &lpass_tx_macro { &lpass_va_macro { status = "okay"; vdd-micb-supply = <&vreg_bob>; + pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; + pinctrl-names = "default"; }; &pcie1 { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 911e104a219d..7388cabeded3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2652,9 +2652,6 @@ lpass_va_macro: codec@3370000 { compatible = "qcom,sc7280-lpass-va-macro"; reg = <0 0x03370000 0 0x1000>; - pinctrl-names = "default"; - pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; - clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; clock-names = "mclk"; From a0a287b4776a3e8d559383e057cca384b3255813 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 24 Mar 2025 09:41:01 +0100 Subject: [PATCH 287/308] arm64: dts: qcom: sm6350: Align reg properties with latest style While in the past the 'reg' properties were often written using decimal '0' for #address-cells = <2> & #size-cells = <2>, nowadays the style is to use hexadecimal '0x0' instead. Align this dtsi file to the new style to make it consistent, and don't use mixed 0x0 and 0 anymore. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250324-sm6350-videocc-v2-1-cc22386433f4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 204 +++++++++++++-------------- 1 file changed, 102 insertions(+), 102 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index a77cf57fcfb1..f80b21d28a92 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -567,114 +567,114 @@ reserved_memory: reserved-memory { ranges; hyp_mem: memory@80000000 { - reg = <0 0x80000000 0 0x600000>; + reg = <0x0 0x80000000 0x0 0x600000>; no-map; }; xbl_aop_mem: memory@80700000 { - reg = <0 0x80700000 0 0x160000>; + reg = <0x0 0x80700000 0x0 0x160000>; no-map; }; cmd_db: memory@80860000 { compatible = "qcom,cmd-db"; - reg = <0 0x80860000 0 0x20000>; + reg = <0x0 0x80860000 0x0 0x20000>; no-map; }; sec_apps_mem: memory@808ff000 { - reg = <0 0x808ff000 0 0x1000>; + reg = <0x0 0x808ff000 0x0 0x1000>; no-map; }; smem_mem: memory@80900000 { - reg = <0 0x80900000 0 0x200000>; + reg = <0x0 0x80900000 0x0 0x200000>; no-map; }; cdsp_sec_mem: memory@80b00000 { - reg = <0 0x80b00000 0 0x1e00000>; + reg = <0x0 0x80b00000 0x0 0x1e00000>; no-map; }; pil_camera_mem: memory@86000000 { - reg = <0 0x86000000 0 0x500000>; + reg = <0x0 0x86000000 0x0 0x500000>; no-map; }; pil_npu_mem: memory@86500000 { - reg = <0 0x86500000 0 0x500000>; + reg = <0x0 0x86500000 0x0 0x500000>; no-map; }; pil_video_mem: memory@86a00000 { - reg = <0 0x86a00000 0 0x500000>; + reg = <0x0 0x86a00000 0x0 0x500000>; no-map; }; pil_cdsp_mem: memory@86f00000 { - reg = <0 0x86f00000 0 0x1e00000>; + reg = <0x0 0x86f00000 0x0 0x1e00000>; no-map; }; pil_adsp_mem: memory@88d00000 { - reg = <0 0x88d00000 0 0x2800000>; + reg = <0x0 0x88d00000 0x0 0x2800000>; no-map; }; wlan_fw_mem: memory@8b500000 { - reg = <0 0x8b500000 0 0x200000>; + reg = <0x0 0x8b500000 0x0 0x200000>; no-map; }; pil_ipa_fw_mem: memory@8b700000 { - reg = <0 0x8b700000 0 0x10000>; + reg = <0x0 0x8b700000 0x0 0x10000>; no-map; }; pil_ipa_gsi_mem: memory@8b710000 { - reg = <0 0x8b710000 0 0x5400>; + reg = <0x0 0x8b710000 0x0 0x5400>; no-map; }; pil_modem_mem: memory@8b800000 { - reg = <0 0x8b800000 0 0xf800000>; + reg = <0x0 0x8b800000 0x0 0xf800000>; no-map; }; cont_splash_memory: memory@a0000000 { - reg = <0 0xa0000000 0 0x2300000>; + reg = <0x0 0xa0000000 0x0 0x2300000>; no-map; }; dfps_data_memory: memory@a2300000 { - reg = <0 0xa2300000 0 0x100000>; + reg = <0x0 0xa2300000 0x0 0x100000>; no-map; }; removed_region: memory@c0000000 { - reg = <0 0xc0000000 0 0x3900000>; + reg = <0x0 0xc0000000 0x0 0x3900000>; no-map; }; pil_gpu_mem: memory@f0d00000 { - reg = <0 0xf0d00000 0 0x1000>; + reg = <0x0 0xf0d00000 0x0 0x1000>; no-map; }; debug_region: memory@ffb00000 { - reg = <0 0xffb00000 0 0xc0000>; + reg = <0x0 0xffb00000 0x0 0xc0000>; no-map; }; last_log_region: memory@ffbc0000 { - reg = <0 0xffbc0000 0 0x40000>; + reg = <0x0 0xffbc0000 0x0 0x40000>; no-map; }; ramoops: ramoops@ffc00000 { compatible = "ramoops"; - reg = <0 0xffc00000 0 0x100000>; + reg = <0x0 0xffc00000 0x0 0x100000>; record-size = <0x1000>; console-size = <0x40000>; pmsg-size = <0x20000>; @@ -683,7 +683,7 @@ ramoops: ramoops@ffc00000 { }; cmdline_region: memory@ffd00000 { - reg = <0 0xffd00000 0 0x1000>; + reg = <0x0 0xffd00000 0x0 0x1000>; no-map; }; }; @@ -787,7 +787,7 @@ soc: soc@0 { gcc: clock-controller@100000 { compatible = "qcom,gcc-sm6350"; - reg = <0 0x00100000 0 0x1f0000>; + reg = <0x0 0x00100000 0x0 0x1f0000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -801,7 +801,7 @@ gcc: clock-controller@100000 { ipcc: mailbox@408000 { compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; - reg = <0 0x00408000 0 0x1000>; + reg = <0x0 0x00408000 0x0 0x1000>; interrupts = ; interrupt-controller; #interrupt-cells = <3>; @@ -810,7 +810,7 @@ ipcc: mailbox@408000 { qfprom: qfprom@784000 { compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; - reg = <0 0x00784000 0 0x3000>; + reg = <0x0 0x00784000 0x0 0x3000>; #address-cells = <1>; #size-cells = <1>; @@ -822,16 +822,16 @@ gpu_speed_bin: gpu-speed-bin@2015 { rng: rng@793000 { compatible = "qcom,prng-ee"; - reg = <0 0x00793000 0 0x1000>; + reg = <0x0 0x00793000 0x0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; sdhc_1: mmc@7c4000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x007c4000 0 0x1000>, - <0 0x007c5000 0 0x1000>, - <0 0x007c8000 0 0x8000>; + reg = <0x0 0x007c4000 0x0 0x1000>, + <0x0 0x007c5000 0x0 0x1000>, + <0x0 0x007c8000 0x0 0x8000>; reg-names = "hc", "cqhci", "ice"; interrupts = , @@ -876,7 +876,7 @@ opp-384000000 { gpi_dma0: dma-controller@800000 { compatible = "qcom,sm6350-gpi-dma"; - reg = <0 0x00800000 0 0x60000>; + reg = <0x0 0x00800000 0x0 0x60000>; interrupts = , , , @@ -908,7 +908,7 @@ qupv3_id_0: geniqup@8c0000 { i2c0: i2c@880000 { compatible = "qcom,geni-i2c"; - reg = <0 0x00880000 0 0x4000>; + reg = <0x0 0x00880000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; @@ -928,7 +928,7 @@ i2c0: i2c@880000 { uart1: serial@884000 { compatible = "qcom,geni-uart"; - reg = <0 0x00884000 0 0x4000>; + reg = <0x0 0x00884000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; @@ -944,7 +944,7 @@ uart1: serial@884000 { i2c2: i2c@888000 { compatible = "qcom,geni-i2c"; - reg = <0 0x00888000 0 0x4000>; + reg = <0x0 0x00888000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; @@ -965,7 +965,7 @@ i2c2: i2c@888000 { gpi_dma1: dma-controller@900000 { compatible = "qcom,sm6350-gpi-dma"; - reg = <0 0x00900000 0 0x60000>; + reg = <0x0 0x00900000 0x0 0x60000>; interrupts = , , , @@ -997,7 +997,7 @@ qupv3_id_1: geniqup@9c0000 { i2c6: i2c@980000 { compatible = "qcom,geni-i2c"; - reg = <0 0x00980000 0 0x4000>; + reg = <0x0 0x00980000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; @@ -1017,7 +1017,7 @@ i2c6: i2c@980000 { i2c7: i2c@984000 { compatible = "qcom,geni-i2c"; - reg = <0 0x00984000 0 0x4000>; + reg = <0x0 0x00984000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; @@ -1037,7 +1037,7 @@ i2c7: i2c@984000 { i2c8: i2c@988000 { compatible = "qcom,geni-i2c"; - reg = <0 0x00988000 0 0x4000>; + reg = <0x0 0x00988000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; @@ -1057,7 +1057,7 @@ i2c8: i2c@988000 { uart9: serial@98c000 { compatible = "qcom,geni-debug-uart"; - reg = <0 0x0098c000 0 0x4000>; + reg = <0x0 0x0098c000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; @@ -1071,7 +1071,7 @@ uart9: serial@98c000 { i2c10: i2c@990000 { compatible = "qcom,geni-i2c"; - reg = <0 0x00990000 0 0x4000>; + reg = <0x0 0x00990000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; @@ -1092,14 +1092,14 @@ i2c10: i2c@990000 { config_noc: interconnect@1500000 { compatible = "qcom,sm6350-config-noc"; - reg = <0 0x01500000 0 0x28000>; + reg = <0x0 0x01500000 0x0 0x28000>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sm6350-system-noc"; - reg = <0 0x01620000 0 0x17080>; + reg = <0x0 0x01620000 0x0 0x17080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -1112,14 +1112,14 @@ clk_virt: interconnect-clk-virt { aggre1_noc: interconnect@16e0000 { compatible = "qcom,sm6350-aggre1-noc"; - reg = <0 0x016e0000 0 0x15080>; + reg = <0x0 0x016e0000 0x0 0x15080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sm6350-aggre2-noc"; - reg = <0 0x01700000 0 0x1f880>; + reg = <0x0 0x01700000 0x0 0x1f880>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -1132,7 +1132,7 @@ compute_noc: interconnect-compute-noc { mmss_noc: interconnect@1740000 { compatible = "qcom,sm6350-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; + reg = <0x0 0x01740000 0x0 0x1c100>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -1140,8 +1140,8 @@ mmss_noc: interconnect@1740000 { ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm6350-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>, - <0 0x01d90000 0 0x8000>; + reg = <0x0 0x01d84000 0x0 0x3000>, + <0x0 0x01d90000 0x0 0x8000>; reg-names = "std", "ice"; interrupts = ; phys = <&ufs_mem_phy>; @@ -1189,7 +1189,7 @@ ufs_mem_hc: ufshc@1d84000 { ufs_mem_phy: phy@1d87000 { compatible = "qcom,sm6350-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1000>; + reg = <0x0 0x01d87000 0x0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, @@ -1210,7 +1210,7 @@ ufs_mem_phy: phy@1d87000 { cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; - reg = <0 0x01dc4000 0 0x24000>; + reg = <0x0 0x01dc4000 0x0 0x24000>; interrupts = ; #dma-cells = <1>; qcom,ee = <0>; @@ -1226,7 +1226,7 @@ cryptobam: dma-controller@1dc4000 { crypto: crypto@1dfa000 { compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; - reg = <0 0x01dfa000 0 0x6000>; + reg = <0x0 0x01dfa000 0x0 0x6000>; dmas = <&cryptobam 4>, <&cryptobam 5>; dma-names = "rx", "tx"; iommus = <&apps_smmu 0x426 0x11>, @@ -1244,9 +1244,9 @@ ipa: ipa@1e40000 { iommus = <&apps_smmu 0x440 0x0>, <&apps_smmu 0x442 0x0>; - reg = <0 0x01e40000 0 0x8000>, - <0 0x01e50000 0 0x3000>, - <0 0x01e04000 0 0x23000>; + reg = <0x0 0x01e40000 0x0 0x8000>, + <0x0 0x01e50000 0x0 0x3000>, + <0x0 0x01e04000 0x0 0x23000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; @@ -1352,8 +1352,8 @@ compute-cb@5 { gpu: gpu@3d00000 { compatible = "qcom,adreno-619.0", "qcom,adreno"; - reg = <0 0x03d00000 0 0x40000>, - <0 0x03d9e000 0 0x1000>; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>; reg-names = "kgsl_3d0_reg_memory", "cx_mem"; interrupts = ; @@ -1420,7 +1420,7 @@ opp-253000000 { adreno_smmu: iommu@3d40000 { compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; - reg = <0 0x03d40000 0 0x10000>; + reg = <0x0 0x03d40000 0x0 0x10000>; #iommu-cells = <1>; #global-interrupts = <2>; interrupts = , @@ -1446,9 +1446,9 @@ adreno_smmu: iommu@3d40000 { gmu: gmu@3d6a000 { compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; - reg = <0 0x03d6a000 0 0x31000>, - <0 0x0b290000 0 0x10000>, - <0 0x0b490000 0 0x10000>; + reg = <0x0 0x03d6a000 0x0 0x31000>, + <0x0 0x0b290000 0x0 0x10000>, + <0x0 0x0b490000 0x0 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; @@ -1490,7 +1490,7 @@ opp-200000000 { gpucc: clock-controller@3d90000 { compatible = "qcom,sm6350-gpucc"; - reg = <0 0x03d90000 0 0x9000>; + reg = <0x0 0x03d90000 0x0 0x9000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK>, <&gcc GCC_GPU_GPLL0_DIV_CLK>; @@ -1544,7 +1544,7 @@ IPCC_MPROC_SIGNAL_GLINK_QMP cdsp: remoteproc@8300000 { compatible = "qcom,sm6350-cdsp-pas"; - reg = <0 0x08300000 0 0x10000>; + reg = <0x0 0x08300000 0x0 0x10000>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, @@ -1643,7 +1643,7 @@ compute-cb@8 { sdhc_2: mmc@8804000 { compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x08804000 0 0x1000>; + reg = <0x0 0x08804000 0x0 0x1000>; interrupts = , ; @@ -1692,7 +1692,7 @@ opp-202000000 { usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; - reg = <0 0x088e3000 0 0x400>; + reg = <0x0 0x088e3000 0x0 0x400>; status = "disabled"; #phy-cells = <0>; @@ -1704,7 +1704,7 @@ usb_1_hsphy: phy@88e3000 { usb_1_qmpphy: phy@88e8000 { compatible = "qcom,sm6350-qmp-usb3-dp-phy"; - reg = <0 0x088e8000 0 0x3000>; + reg = <0x0 0x088e8000 0x0 0x3000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, @@ -1755,27 +1755,27 @@ usb_1_qmpphy_dp_in: endpoint { dc_noc: interconnect@9160000 { compatible = "qcom,sm6350-dc-noc"; - reg = <0 0x09160000 0 0x3200>; + reg = <0x0 0x09160000 0x0 0x3200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; - reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; + reg = <0x0 0x09200000 0x0 0x50000>, <0x0 0x09600000 0x0 0x50000>; reg-names = "llcc0_base", "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { compatible = "qcom,sm6350-gem-noc"; - reg = <0 0x09680000 0 0x3e200>; + reg = <0x0 0x09680000 0x0 0x3e200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; npu_noc: interconnect@9990000 { compatible = "qcom,sm6350-npu-noc"; - reg = <0 0x09990000 0 0x1600>; + reg = <0x0 0x09990000 0x0 0x1600>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -1879,7 +1879,7 @@ opp-10 { usb_1: usb@a6f8800 { compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; + reg = <0x0 0x0a6f8800 0x0 0x400>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; @@ -1917,7 +1917,7 @@ usb_1: usb@a6f8800 { usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; + reg = <0x0 0x0a600000 0x0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x540 0x0>; snps,dis_u2_susphy_quirk; @@ -1955,7 +1955,7 @@ usb_1_dwc3_ss_out: endpoint { cci0: cci@ac4a000 { compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; - reg = <0 0x0ac4a000 0 0x1000>; + reg = <0x0 0x0ac4a000 0x0 0x1000>; interrupts = ; power-domains = <&camcc TITAN_TOP_GDSC>; @@ -2002,7 +2002,7 @@ cci0_i2c1: i2c-bus@1 { cci1: cci@ac4b000 { compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; - reg = <0 0x0ac4b000 0 0x1000>; + reg = <0x0 0x0ac4b000 0x0 0x1000>; interrupts = ; power-domains = <&camcc TITAN_TOP_GDSC>; @@ -2044,7 +2044,7 @@ cci1_i2c0: i2c-bus@0 { camcc: clock-controller@ad00000 { compatible = "qcom,sm6350-camcc"; - reg = <0 0x0ad00000 0 0x16000>; + reg = <0x0 0x0ad00000 0x0 0x16000>; clocks = <&rpmhcc RPMH_CXO_CLK>; #clock-cells = <1>; #reset-cells = <1>; @@ -2053,7 +2053,7 @@ camcc: clock-controller@ad00000 { mdss: display-subsystem@ae00000 { compatible = "qcom,sm6350-mdss"; - reg = <0 0x0ae00000 0 0x1000>; + reg = <0x0 0x0ae00000 0x0 0x1000>; reg-names = "mdss"; interrupts = ; @@ -2085,8 +2085,8 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm6350-dpu"; - reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x3000>; + reg = <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; reg-names = "mdp", "vbif"; interrupt-parent = <&mdss>; @@ -2169,11 +2169,11 @@ opp-560000000 { mdss_dp: displayport-controller@ae90000 { compatible = "qcom,sm6350-dp", "qcom,sm8350-dp"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0x600>, - <0 0xae91000 0 0x400>, - <0 0xae91400 0 0x400>; + reg = <0x0 0xae90000 0x0 0x200>, + <0x0 0xae90200 0x0 0x200>, + <0x0 0xae90400 0x0 0x600>, + <0x0 0xae91000 0x0 0x400>, + <0x0 0xae91400 0x0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, @@ -2249,7 +2249,7 @@ opp-810000000 { mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae94000 0 0x400>; + reg = <0x0 0x0ae94000 0x0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -2326,9 +2326,9 @@ opp-358000000 { mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-10nm"; - reg = <0 0x0ae94400 0 0x200>, - <0 0x0ae94600 0 0x280>, - <0 0x0ae94a00 0 0x1e0>; + reg = <0x0 0x0ae94400 0x0 0x200>, + <0x0 0x0ae94600 0x0 0x280>, + <0x0 0x0ae94a00 0x0 0x1e0>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -2346,7 +2346,7 @@ mdss_dsi0_phy: phy@ae94400 { dispcc: clock-controller@af00000 { compatible = "qcom,sm6350-dispcc"; - reg = <0 0x0af00000 0 0x20000>; + reg = <0x0 0x0af00000 0x0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK>, <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, @@ -2366,7 +2366,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sm6350-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; + reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 655 12>, <138 139 15>; #interrupt-cells = <2>; @@ -2376,8 +2376,8 @@ pdc: interrupt-controller@b220000 { tsens0: thermal-sensor@c263000 { compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x8>; /* SROT */ + reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */ + <0x0 0x0c222000 0x0 0x8>; /* SROT */ #qcom,sensors = <16>; interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; @@ -2387,8 +2387,8 @@ tsens0: thermal-sensor@c263000 { tsens1: thermal-sensor@c265000 { compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x8>; /* SROT */ + reg = <0x0 0x0c265000 0x0 0x1ff>, /* TM */ + <0x0 0x0c223000 0x0 0x8>; /* SROT */ #qcom,sensors = <16>; interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; @@ -2398,7 +2398,7 @@ tsens1: thermal-sensor@c265000 { aoss_qmp: power-management@c300000 { compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x1000>; + reg = <0x0 0x0c300000 0x0 0x1000>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; @@ -2408,11 +2408,11 @@ aoss_qmp: power-management@c300000 { spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0 0x0c440000 0 0x1100>, - <0 0x0c600000 0 0x2000000>, - <0 0x0e600000 0 0x100000>, - <0 0x0e700000 0 0xa0000>, - <0 0x0c40a000 0 0x26000>; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; @@ -2426,7 +2426,7 @@ spmi_bus: spmi@c440000 { tlmm: pinctrl@f100000 { compatible = "qcom,sm6350-tlmm"; - reg = <0 0x0f100000 0 0x300000>; + reg = <0x0 0x0f100000 0x0 0x300000>; interrupts = , , , @@ -2605,7 +2605,7 @@ qup_uart1_tx: qup-uart1-tx-default-state { apps_smmu: iommu@15000000 { compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; + reg = <0x0 0x15000000 0x0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; interrupts = , @@ -2703,7 +2703,7 @@ intc: interrupt-controller@17a00000 { watchdog@17c10000 { compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; - reg = <0 0x17c10000 0 0x1000>; + reg = <0x0 0x17c10000 0x0 0x1000>; clocks = <&sleep_clk>; interrupts = ; }; @@ -2857,7 +2857,7 @@ osm_l3: interconnect@18321000 { cpufreq_hw: cpufreq@18323000 { compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; - reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; + reg = <0x0 0x18323000 0x0 0x1000>, <0x0 0x18325800 0x0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; @@ -2868,7 +2868,7 @@ cpufreq_hw: cpufreq@18323000 { wifi: wifi@18800000 { compatible = "qcom,wcn3990-wifi"; - reg = <0 0x18800000 0 0x800000>; + reg = <0x0 0x18800000 0x0 0x800000>; reg-names = "membase"; memory-region = <&wlan_fw_mem>; interrupts = , From 90485e48b8889deec74cf2ce07df174da84b1ac1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 09:08:13 +0200 Subject: [PATCH 288/308] arm64: dts: qcom: qcm6490-fairphone-fp5: Add PTN36502 redriver Add a node for the "Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver" found on this device. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250425-fp5-pmic-glink-dp-v3-2-cc9c2aeb42fb@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcm6490-fairphone-fp5.dts | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 0f1c83822f66..ea9f5517e8a0 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -166,6 +166,23 @@ vreg_oled_vci: regulator-oled-vci { regulator-boot-on; }; + vreg_usb_redrive_1v8: regulator-usb-redrive-1v8 { + compatible = "regulator-fixed"; + regulator-name = "USB_REDRIVE_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 61 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + + regulator-boot-on; + + pinctrl-0 = <&usb_redrive_1v8_en_default>; + pinctrl-names = "default"; + }; + reserved-memory { cont_splash_mem: cont-splash@e1000000 { reg = <0x0 0xe1000000 0x0 0x2300000>; @@ -747,7 +764,15 @@ &i2c2 { &i2c4 { status = "okay"; - /* PTN36502 USB redriver @ 1a */ + typec-mux@1a { + compatible = "nxp,ptn36502"; + reg = <0x1a>; + + vdd18-supply = <&vreg_usb_redrive_1v8>; + + retimer-switch; + orientation-switch; + }; }; &i2c9 { @@ -1182,6 +1207,14 @@ sw_ctrl_default: sw-ctrl-default-state { function = "gpio"; bias-pull-down; }; + + usb_redrive_1v8_en_default: usb-redrive-1v8-en-default-state { + pins = "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; }; &uart5 { From 1efa79c7536896b6fcd71760c3d4f0a0d40a9e1c Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 09:08:14 +0200 Subject: [PATCH 289/308] arm64: dts: qcom: qcm6490-fairphone-fp5: Add OCP96011 audio switch Add a node for the OCP96011 on the board which is used to handle USB-C analog audio switch and handles the SBU mux for DisplayPort-over-USB-C. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250425-fp5-pmic-glink-dp-v3-3-cc9c2aeb42fb@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index ea9f5517e8a0..e0470be9142c 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -750,7 +750,19 @@ vreg_l7p: ldo7 { }; /* Pixelworks @ 26 */ - /* FSA4480 USB audio switch @ 42 */ + + typec-mux@42 { + compatible = "ocs,ocp96011", "fcs,fsa4480"; + reg = <0x42>; + + interrupts-extended = <&tlmm 7 IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&vreg_bob>; + + mode-switch; + orientation-switch; + }; + /* AW86927FCR haptics @ 5a */ }; From 6b51f5e1811398dce5c1d67b746dde74c75f6ce7 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 09:08:15 +0200 Subject: [PATCH 290/308] arm64: dts: qcom: qcm6490-fairphone-fp5: Hook up DisplayPort over USB-C Extend the USB graph to connect the OCP96011 switch, the PTN36502 redriver, the USB controllers and the MDSS, so that DisplayPort over USB-C is working. Connect some parts of the graph directly in the SoC dtsi since those parts are wired up like this in the SoC directly. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-fp5-pmic-glink-dp-v3-4-cc9c2aeb42fb@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcm6490-fairphone-fp5.dts | 54 +++++++++++++++++-- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++- 2 files changed, 57 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index e0470be9142c..9e8f9fb57c47 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -101,7 +101,15 @@ port@1 { reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&redriver_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&ocp96011_sbu_mux>; }; }; }; @@ -761,6 +769,13 @@ typec-mux@42 { mode-switch; orientation-switch; + + port { + ocp96011_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + data-lanes = <1 0>; + }; + }; }; /* AW86927FCR haptics @ 5a */ @@ -784,6 +799,27 @@ typec-mux@1a { retimer-switch; orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; }; }; @@ -805,6 +841,14 @@ &mdss { status = "okay"; }; +&mdss_dp { + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; +}; + &mdss_dsi { vdda-supply = <&vreg_l6b>; status = "okay"; @@ -1301,10 +1345,6 @@ &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; -}; - &usb_1_hsphy { vdda-pll-supply = <&vreg_l10c>; vdda18-supply = <&vreg_l1c>; @@ -1331,6 +1371,10 @@ &usb_1_qmpphy { status = "okay"; }; +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_ss_in>; +}; + &venus { firmware-name = "qcom/qcm6490/fairphone5/venus.mbn"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7388cabeded3..d9f422da942b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3671,6 +3671,8 @@ usb_1_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + ports { #address-cells = <1>; #size-cells = <0>; @@ -3686,6 +3688,7 @@ port@1 { reg = <1>; usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -3693,6 +3696,7 @@ port@2 { reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp_out>; }; }; }; @@ -4299,6 +4303,7 @@ port@1 { reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; @@ -5024,7 +5029,9 @@ dp_in: endpoint { port@1 { reg = <1>; - mdss_dp_out: endpoint { }; + mdss_dp_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; }; }; From e99e02edac8ba46fedc6536f18a86915af52b7ae Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:40 +0200 Subject: [PATCH 291/308] arm64: dts: qcom: apq8096-db820c: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-1-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 1089964e6c0d..5b2e88915c2f 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -953,15 +953,15 @@ &sdhc2 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; From 0c5b597651e0c708b3dec4c6da56e70947c1c893 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:41 +0200 Subject: [PATCH 292/308] arm64: dts: qcom: msm8916-modem-qdsp6: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-2-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-modem-qdsp6.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-modem-qdsp6.dtsi b/arch/arm64/boot/dts/qcom/msm8916-modem-qdsp6.dtsi index 039961622633..75103168c1fc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-modem-qdsp6.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-modem-qdsp6.dtsi @@ -58,19 +58,19 @@ dai@20 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; direction = ; }; dai@1 { - reg = <1>; + reg = ; direction = ; }; dai@2 { - reg = <2>; + reg = ; direction = ; }; dai@3 { - reg = <3>; + reg = ; direction = ; is-compress-dai; }; From d89ed52f3f506531c32767dc1b91cfbc322d6959 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:42 +0200 Subject: [PATCH 293/308] arm64: dts: qcom: msm8953: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-3-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 4793a60fa946..28fef68f7348 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1933,19 +1933,19 @@ q6asmdai: dais { #sound-dai-cells = <1>; dai@0 { - reg = <0>; + reg = ; direction = ; }; dai@1 { - reg = <1>; + reg = ; direction = ; }; dai@2 { - reg = <2>; + reg = ; direction = ; }; dai@3 { - reg = <3>; + reg = ; direction = ; is-compress-dai; }; From 01160256f4b2be614abbe24dcb05967e9916440e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:43 +0200 Subject: [PATCH 294/308] arm64: dts: qcom: msm8996*: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-4-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 6 +++--- arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts | 6 +++--- arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 38035e0db80b..3897a177f12e 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -288,15 +288,15 @@ &q6asmdai { #size-cells = <0>; dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index d7fa56808747..bd3f39e1b98f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -137,15 +137,15 @@ &mss_pil { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts index 5e3fd1637f44..443599a5a5dd 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts @@ -87,15 +87,15 @@ &pmi8994_wled { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts index 5e3b9130e9c2..33d84ac541e1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dts @@ -139,15 +139,15 @@ led@6 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; From 6ac93e5b21e025f54af5b5a3f0639632ce72b95c Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:44 +0200 Subject: [PATCH 295/308] arm64: dts: qcom: qrb5165-rb5: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-5-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index dcb998b8b054..33ecbc81997c 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1008,21 +1008,21 @@ dai@20 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; dai@3 { direction = ; is-compress-dai; - reg = <3>; + reg = ; }; }; From 08b8a9fdced825dbd4553d14d45b3ae7a286ef16 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:45 +0200 Subject: [PATCH 296/308] arm64: dts: qcom: sc7180-acer-aspire1: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-6-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts index 3f0d3e33894a..672ac4c3afa3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -530,19 +530,19 @@ dai@104 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; dai@3 { - reg = <3>; + reg = ; }; }; From f1275b0a1de7339fd4ef7ea5cfaa5a79389fc6f8 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:46 +0200 Subject: [PATCH 297/308] arm64: dts: qcom: sc7280: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-7-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d9f422da942b..ac59dd41a495 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -28,6 +28,7 @@ #include #include #include +#include #include / { @@ -3868,15 +3869,15 @@ q6asmdai: dais { iommus = <&apps_smmu 0x1801 0x0>; dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; }; From 84665986b7dd7ac44b9703328fe0a5b1184e0a8c Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:47 +0200 Subject: [PATCH 298/308] arm64: dts: qcom: sdm845*: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-8-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 12 ++++++------ .../dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 6 +++--- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index adfd91627005..b5c63fa0365d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -714,19 +714,19 @@ dai@22 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; dai@3 { - reg = <3>; + reg = ; direction = <2>; is-compress-dai; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 8a0f154bffc3..b118d666e535 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -517,27 +517,27 @@ dai@23 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; dai@3 { - reg = <3>; + reg = ; }; dai@4 { - reg = <4>; + reg = ; }; dai@5 { - reg = <5>; + reg = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index f790eb73abdd..341b9d345f04 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -388,15 +388,15 @@ dai@22 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 501575c9beda..63cf879a7a29 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -543,15 +543,15 @@ dai@22 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; From f18b14d2bec4fb604e2feb81e12e2869f5ce82b1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:48 +0200 Subject: [PATCH 299/308] arm64: dts: qcom: sdm850*: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-9-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 6 +++--- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 7677acd08e2d..3b28c543fd96 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -612,15 +612,15 @@ &qupv3_id_1 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index d6d4e7184c56..a676d3ea01b9 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -425,15 +425,15 @@ &qupv3_id_1 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; From 69a8b068dcf6dc42846f0764149461d2166a19a6 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:49 +0200 Subject: [PATCH 300/308] arm64: dts: qcom: sm7325-nothing-spacewar: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-10-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts index 85a928f98077..befbb40228b5 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -1223,7 +1223,7 @@ dai@16 { &q6asmdai { dai@0 { - reg = <0>; + reg = ; }; }; From 5e170ce69d204b59116539d8b3a789c4d5d82563 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Apr 2025 13:53:50 +0200 Subject: [PATCH 301/308] arm64: dts: qcom: sm8350: Use q6asm defines for reg Use the MSM_FRONTEND_DAI_MULTIMEDIA* defines to make the code more readable. No functional change intended. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250425-q6asmdai-defines-v1-11-28308e2ce7d4@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 04a30df4362b..f2e12da13e68 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -1957,15 +1958,15 @@ q6asmdai: dais { iommus = <&apps_smmu 0x1801 0x0>; dai@0 { - reg = <0>; + reg = ; }; dai@1 { - reg = <1>; + reg = ; }; dai@2 { - reg = <2>; + reg = ; }; }; }; From b7bc69b90736a281490d535c6786b6c23c1b22e8 Mon Sep 17 00:00:00 2001 From: Felix Kaechele Date: Sun, 6 Apr 2025 15:52:02 +0200 Subject: [PATCH 302/308] arm64: dts: qcom: msm8953: Add uart_5 Add the node and pinctrl for uart_5 found on the MSM8953 SoC. Signed-off-by: Felix Kaechele [luca: Prepare patch for upstream submission] Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250406-msm8953-uart_5-v1-1-7e4841674137@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 28fef68f7348..d18a59238535 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -768,6 +768,20 @@ spi_6_sleep: spi-6-sleep-state { bias-disable; }; + uart_5_default: uart-5-default-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "blsp_uart5"; + drive-strength = <16>; + bias-disable; + }; + + uart_5_sleep: uart-5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wcnss_pin_a: wcnss-active-state { wcss-wlan2-pins { @@ -1593,6 +1607,24 @@ blsp2_dma: dma-controller@7ac4000 { qcom,controlled-remotely; }; + uart_5: serial@7aef000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x07aef000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", + "iface"; + dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&uart_5_default>; + pinctrl-1 = <&uart_5_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + }; + i2c_5: i2c@7af5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af5000 0x600>; From 6aeda4f2042711f99d63c5b7bf846c2bba711696 Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Sun, 20 Apr 2025 17:12:44 +0200 Subject: [PATCH 303/308] arm64: dts: qcom: msm8953: Add interconnects Add the nodes for the bimc, pcnoc, snoc and snoc_mm. And wire up the interconnects where applicable. Signed-off-by: Vladimir Lypak [luca: Prepare patch for upstream submission] Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250420-msm8953-interconnect-v2-2-828715dcb674@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 101 ++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index d18a59238535..273e79fb7569 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -5,6 +5,8 @@ #include #include #include +#include +#include #include #include #include @@ -45,6 +47,8 @@ cpu0: cpu@0 { reg = <0x0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &bimc SLV_EBI RPM_ACTIVE_TAG>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -55,6 +59,8 @@ cpu1: cpu@1 { reg = <0x1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &bimc SLV_EBI RPM_ACTIVE_TAG>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -65,6 +71,8 @@ cpu2: cpu@2 { reg = <0x2>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &bimc SLV_EBI RPM_ACTIVE_TAG>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -75,6 +83,8 @@ cpu3: cpu@3 { reg = <0x3>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &bimc SLV_EBI RPM_ACTIVE_TAG>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -85,6 +95,8 @@ cpu4: cpu@100 { reg = <0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &bimc SLV_EBI RPM_ACTIVE_TAG>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -95,6 +107,8 @@ cpu5: cpu@101 { reg = <0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &bimc SLV_EBI RPM_ACTIVE_TAG>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -105,6 +119,8 @@ cpu6: cpu@102 { reg = <0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &bimc SLV_EBI RPM_ACTIVE_TAG>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -115,6 +131,8 @@ cpu7: cpu@103 { reg = <0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &bimc SLV_EBI RPM_ACTIVE_TAG>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -471,6 +489,13 @@ rng@e3000 { clock-names = "core"; }; + bimc: interconnect@400000 { + compatible = "qcom,msm8953-bimc"; + reg = <0x00400000 0x5a000>; + + #interconnect-cells = <2>; + }; + tsens0: thermal-sensor@4a9000 { compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; reg = <0x004a9000 0x1000>, /* TM */ @@ -487,6 +512,29 @@ restart@4ab000 { reg = <0x004ab000 0x4>; }; + pcnoc: interconnect@500000 { + compatible = "qcom,msm8953-pcnoc"; + reg = <0x00500000 0x12080>; + + clocks = <&gcc GCC_PCNOC_USB3_AXI_CLK>; + clock-names = "pcnoc_usb3_axi"; + + #interconnect-cells = <2>; + }; + + snoc: interconnect@580000 { + compatible = "qcom,msm8953-snoc"; + reg = <0x00580000 0x16080>; + + #interconnect-cells = <2>; + + snoc_mm: interconnect-snoc { + compatible = "qcom,msm8953-snoc-mm"; + + #interconnect-cells = <2>; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,msm8953-pinctrl"; reg = <0x01000000 0x300000>; @@ -864,6 +912,13 @@ mdss: display-subsystem@1a00000 { interrupt-controller; #interrupt-cells = <1>; + interconnects = <&snoc_mm MAS_MDP RPM_ALWAYS_TAG + &bimc SLV_EBI RPM_ALWAYS_TAG>, + <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &pcnoc SLV_DISP_SS_CFG RPM_ACTIVE_TAG>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&gcc GCC_MDSS_AXI_CLK>, <&gcc GCC_MDSS_VSYNC_CLK>, @@ -1080,6 +1135,11 @@ gpu: gpu@1c00000 { "alwayson"; power-domains = <&gcc OXILI_GX_GDSC>; + interconnects = <&bimc MAS_OXILI RPM_ALWAYS_TAG + &bimc SLV_EBI RPM_ALWAYS_TAG>, + <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &pcnoc SLV_GPU_CFG RPM_ACTIVE_TAG>; + iommus = <&gpu_iommu 0>; operating-points-v2 = <&gpu_opp_table>; @@ -1317,6 +1377,13 @@ usb3: usb@70f8800 { <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <133330000>; + interconnects = <&pcnoc MAS_USB3 RPM_ALWAYS_TAG + &bimc SLV_EBI RPM_ALWAYS_TAG>, + <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &pcnoc SLV_USB3 RPM_ACTIVE_TAG>; + interconnect-names = "usb-ddr", + "apps-usb"; + power-domains = <&gcc USB30_GDSC>; qcom,select-utmi-as-pipe-clk; @@ -1369,6 +1436,13 @@ sdhc_1: mmc@7824900 { <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; + interconnects = <&pcnoc MAS_SDCC_1 RPM_ALWAYS_TAG + &bimc SLV_EBI RPM_ALWAYS_TAG>, + <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &pcnoc SLV_SDCC_1 RPM_ACTIVE_TAG>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + power-domains = <&rpmpd MSM8953_VDDCX>; operating-points-v2 = <&sdhc1_opp_table>; @@ -1389,26 +1463,36 @@ sdhc1_opp_table: opp-table-sdhc1 { opp-25000000 { opp-hz = /bits/ 64 <25000000>; + opp-peak-kBps = <200000>, <100000>; + opp-avg-kBps = <65360>, <32768>; required-opps = <&rpmpd_opp_low_svs>; }; opp-50000000 { opp-hz = /bits/ 64 <50000000>; + opp-peak-kBps = <400000>, <200000>; + opp-avg-kBps = <130718>, <65360>; required-opps = <&rpmpd_opp_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <400000>, <400000>; + opp-avg-kBps = <130718>, <65360>; required-opps = <&rpmpd_opp_svs>; }; opp-192000000 { opp-hz = /bits/ 64 <192000000>; + opp-peak-kBps = <800000>, <600000>; + opp-avg-kBps = <261438>, <130718>; required-opps = <&rpmpd_opp_nom>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <800000>, <800000>; + opp-avg-kBps = <261438>, <300000>; required-opps = <&rpmpd_opp_nom>; }; }; @@ -1429,6 +1513,13 @@ sdhc_2: mmc@7864900 { <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; + interconnects = <&pcnoc MAS_SDCC_2 RPM_ALWAYS_TAG + &bimc SLV_EBI RPM_ALWAYS_TAG>, + <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG + &pcnoc SLV_SDCC_2 RPM_ACTIVE_TAG>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + power-domains = <&rpmpd MSM8953_VDDCX>; operating-points-v2 = <&sdhc2_opp_table>; @@ -1445,26 +1536,36 @@ sdhc2_opp_table: opp-table-sdhc2 { opp-25000000 { opp-hz = /bits/ 64 <25000000>; + opp-peak-kBps = <200000>, <100000>; + opp-avg-kBps = <65360>, <32768>; required-opps = <&rpmpd_opp_low_svs>; }; opp-50000000 { opp-hz = /bits/ 64 <50000000>; + opp-peak-kBps = <400000>, <400000>; + opp-avg-kBps = <130718>, <65360>; required-opps = <&rpmpd_opp_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <800000>, <400000>; + opp-avg-kBps = <130718>, <130718>; required-opps = <&rpmpd_opp_svs>; }; opp-177770000 { opp-hz = /bits/ 64 <177770000>; + opp-peak-kBps = <600000>, <600000>; + opp-avg-kBps = <261438>, <130718>; required-opps = <&rpmpd_opp_nom>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; + opp-peak-kBps = <800000>, <800000>; + opp-avg-kBps = <261438>, <130718>; required-opps = <&rpmpd_opp_nom>; }; }; From 28bce181daf3ba87d414f75ad9f2a680f69f2c25 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 9 May 2025 10:08:52 +0300 Subject: [PATCH 304/308] arm64: dts: qcom: x1e80100-*: Drop useless DP3 compatible override Back when display support was added initially to CRD, and we used to have two separate compatibles for eDP and DP, it was supposed to override the DP compatible with the eDP one in the board specific devicetree. Since then, the DP driver has been reworked to figure out the eDP/DP at runtime while only DP compatible remained in the end. Even though the override does nothing basically, drop it to avoid further confusion. Drop it from all X Elite based platforms. Reviewed-by: Dmitry Baryshkov Reviewed-by: Johan Hovold Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250509-x1e80100-dts-drop-useless-dp-compatible-override-v2-1-126db05cb70a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 1 - arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 1 - arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 1 - arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts | 1 - arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 1 - arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 1 - arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 1 - 7 files changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index dbdf542c7ce5..c9f0d5052670 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1148,7 +1148,6 @@ &mdss_dp2_out { }; &mdss_dp3 { - compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 962fb050c55c..88cbf2a81861 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -972,7 +972,6 @@ &mdss_dp1_out { }; &mdss_dp3 { - compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index c94ddba5fbf1..a9ac4b81daf6 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -479,7 +479,6 @@ &mdss { }; &mdss_dp3 { - compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index 199e25674352..e3f9354aa8ab 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -1154,7 +1154,6 @@ &mdss_dp1_out { }; &mdss_dp3 { - compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 9fb306456e33..873ebafa933a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -615,7 +615,6 @@ &mdss { }; &mdss_dp3 { - compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index da8cef62ae73..26ae19b34b37 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -945,7 +945,6 @@ &mdss { }; &mdss_dp3 { - compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index c0c8ecb666e1..4dfba835af6a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -871,7 +871,6 @@ &mdss_dp2_out { }; &mdss_dp3 { - compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; status = "okay"; From 061402552e98a55b419a5045ba366dd51cfb24f1 Mon Sep 17 00:00:00 2001 From: Pratyush Brahma Date: Thu, 8 May 2025 11:51:02 +0530 Subject: [PATCH 305/308] arm64: dts: qcom: qcs8300: add the pcie smmu node Add the PCIe SMMU node to enable address translations for pcie. Reviewed-by: Dmitry Baryshkov Signed-off-by: Pratyush Brahma Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250508-qcs8300-pcie-smmu-v3-1-c6b4453b0b22@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 75 +++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 9bc6cf9a3495..009f9658a4fa 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -5127,6 +5127,81 @@ apps_smmu: iommu@15000000 { ; }; + pcie_smmu: iommu@15200000 { + compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15200000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, From 424246ed3e5d1d7b4a33e2b13a30c8d1b284fad5 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Tue, 6 May 2025 13:18:39 -0500 Subject: [PATCH 306/308] arm64: dts: qcom: sdm845-xiaomi-beryllium-common: add touchscreen related nodes Enable qupv3_id_1 and gpi_dma1 as they are required for configuring touchscreen. Also add pinctrl configurations needed for touchscreen. These are common for both the tianma and ebbg touchscreen variant. In the subsequent patches, we will enable support for the Novatek NT36672a touchscreen and FocalTech FT8719 touchscreen that are used in the Poco F1 Tianma and EBBG panel variant respectively. This is done in preparation for that. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Joel Selvaraj Link: https://lore.kernel.org/r/20250506-pocof1-touchscreen-support-v4-2-bfb53da52945@joelselvaraj.com Signed-off-by: Bjorn Andersson --- .../qcom/sdm845-xiaomi-beryllium-common.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 341b9d345f04..7810b0ce7591 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -239,6 +239,10 @@ &gcc { ; }; +&gpi_dma1 { + status = "okay"; +}; + &gpu { status = "okay"; @@ -404,6 +408,10 @@ &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &sdhc_2 { status = "okay"; @@ -509,6 +517,37 @@ sdc2_card_det_n: sd-card-det-n-state { function = "gpio"; bias-pull-up; }; + + ts_int_default: ts-int-default-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <16>; + bias-pull-down; + output-disable; + }; + + ts_reset_default: ts-reset-default-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <16>; + output-high; + }; + + ts_int_sleep: ts-int-sleep-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-disable; + }; + + ts_reset_sleep: ts-reset-sleep-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; }; &uart6 { From 2be670d00b4002f56b11a57a510540001ef1cacb Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Tue, 6 May 2025 13:18:40 -0500 Subject: [PATCH 307/308] arm64: dts: qcom: sdm845-xiaomi-beryllium-tianma: introduce touchscreen support Enable the Novatek NT36672A touchscreen controller used in the Poco F1 (Tianma) panel variant. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Joel Selvaraj Link: https://lore.kernel.org/r/20250506-pocof1-touchscreen-support-v4-3-bfb53da52945@joelselvaraj.com Signed-off-by: Bjorn Andersson --- .../qcom/sdm845-xiaomi-beryllium-tianma.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts index e9427851ebaa..b58964cde834 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts @@ -13,3 +13,26 @@ &display_panel { compatible = "tianma,fhd-video", "novatek,nt36672a"; status = "okay"; }; + +&i2c14 { + status = "okay"; + + touchscreen@1 { + compatible = "novatek,nt36672a-ts"; + reg = <0x01>; + + interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + panel = <&display_panel>; + + iovcc-supply = <&vreg_l14a_1p8>; + vcc-supply = <&lab>; + + pinctrl-0 = <&ts_int_default &ts_reset_default>; + pinctrl-1 = <&ts_int_sleep &ts_reset_sleep>; + pinctrl-names = "default", "sleep"; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2246>; + }; +}; From a18226be95c7ae7c9ec22fd31a6124bef5675c64 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Tue, 6 May 2025 13:18:41 -0500 Subject: [PATCH 308/308] arm64: dts: qcom: sdm845-xiaomi-beryllium-ebbg: introduce touchscreen support Enable the Focaltech FT8719 touchscreen controller used in the Poco F1 (EBBG) panel variant. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Joel Selvaraj Link: https://lore.kernel.org/r/20250506-pocof1-touchscreen-support-v4-4-bfb53da52945@joelselvaraj.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts index 76931ebad065..2d6f0e382a6c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-ebbg.dts @@ -13,3 +13,26 @@ &display_panel { compatible = "ebbg,ft8719"; status = "okay"; }; + +&i2c14 { + status = "okay"; + + touchscreen@38 { + compatible = "focaltech,ft8719"; + reg = <0x38>; + + interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + panel = <&display_panel>; + + iovcc-supply = <&vreg_l14a_1p8>; + vcc-supply = <&lab>; + + pinctrl-0 = <&ts_int_default &ts_reset_default>; + pinctrl-1 = <&ts_int_sleep &ts_reset_sleep>; + pinctrl-names = "default", "sleep"; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2246>; + }; +};