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PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED

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Tegra Endpoint exposes three 64-bit BARs at indices 0, 2, and 4:
- BAR0+BAR1: EPF test/data (programmable 64-bit BAR)
- BAR2+BAR3: MSI-X table (hardware-backed)
- BAR4+BAR5: DMA registers (hardware-backed)

Update tegra_pcie_epc_features so that BAR2 is BAR_RESERVED with
PCI_EPC_BAR_RSVD_MSIX_TBL_RAM (64 KB) & PCI_EPC_BAR_RSVD_MSIX_PBA_RAM
(64 KB) and BAR4 is BAR_RESERVED with PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO (4KB).
This keeps CONSECUTIVE_BAR_TEST working while allowing the host to use
64-bit BAR2 (MSI-X) and BAR4 (DMA).

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Link: https://patch.msgid.link/20260324080857.916263-4-mmaddireddy@nvidia.com
This commit is contained in:
Manikanta Maddireddy 2026-03-24 13:38:56 +05:30 committed by Manivannan Sadhasivam
parent 5aec1f18b3
commit 12a22fb38c
1 changed files with 37 additions and 5 deletions
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42
drivers/pci/controller/dwc/pcie-tegra194.c
View File

@ -1978,16 +1978,48 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
/* Tegra EP: BAR0 = 64-bit programmable BAR */
static const struct pci_epc_bar_rsvd_region tegra194_bar2_rsvd[] = {
{
/* MSI-X table structure */
.type = PCI_EPC_BAR_RSVD_MSIX_TBL_RAM,
.offset = 0x0,
.size = SZ_64K,
},
{
/* MSI-X PBA structure */
.type = PCI_EPC_BAR_RSVD_MSIX_PBA_RAM,
.offset = 0x10000,
.size = SZ_64K,
},
};
static const struct pci_epc_bar_rsvd_region tegra194_bar4_rsvd[] = {
{
/* DMA_CAP (BAR4: DMA Port Logic Structure) */
.type = PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,
.offset = 0x0,
.size = SZ_4K,
},
};
/* Tegra EP: BAR0 = 64-bit programmable BAR, BAR2 = 64-bit MSI-X table, BAR4 = 64-bit DMA regs. */
static const struct pci_epc_features tegra_pcie_epc_features = {
DWC_EPC_COMMON_FEATURES,
.linkup_notifier = true,
.msi_capable = true,
.bar[BAR_0] = { .only_64bit = true, },
.bar[BAR_2] = { .type = BAR_DISABLED, },
.bar[BAR_3] = { .type = BAR_DISABLED, },
.bar[BAR_4] = { .type = BAR_DISABLED, },
.bar[BAR_5] = { .type = BAR_DISABLED, },
.bar[BAR_2] = {
.type = BAR_RESERVED,
.only_64bit = true,
.nr_rsvd_regions = ARRAY_SIZE(tegra194_bar2_rsvd),
.rsvd_regions = tegra194_bar2_rsvd,
},
.bar[BAR_4] = {
.type = BAR_RESERVED,
.only_64bit = true,
.nr_rsvd_regions = ARRAY_SIZE(tegra194_bar4_rsvd),
.rsvd_regions = tegra194_bar4_rsvd,
},
.align = SZ_64K,
};