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rk3368: clk: cpll: make cpll low jitter.

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This modify is for cpll low jitter.
Make the signal of clk_gmac better.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
This commit is contained in:
zhangqing 2015-06-25 16:50:06 -07:00
parent fca072d64b
commit 12a178aad2
2 changed files with 2 additions and 1 deletions
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2
arch/arm64/boot/dts/rk3368-clocks.dtsi
View File

@ -330,7 +330,7 @@ clk_cpll: pll-clk@0030 {
status-reg = <0x0480 3>;
clocks = <&xin24m>;
clock-output-names = "clk_cpll";
rockchip,pll-type = <CLK_PLL_3188PLUS>;
rockchip,pll-type = <CLK_PLL_3368_LOW_JITTER>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};

1
drivers/clk/rockchip/clk-pll.c
View File

@ -332,6 +332,7 @@ static const struct apll_clk_set rk3368_aplll_table[] = {
static const struct pll_clk_set rk3368_pll_table_low_jitter[] = {
/* _khz, nr, nf, no, nb */
_RK3188PLUS_PLL_SET_CLKS_NB(1188000, 1, 99, 2, 1),
_RK3188PLUS_PLL_SET_CLKS_NB(400000, 1, 100, 6, 1),
_RK3188PLUS_PLL_SET_CLKS( 0, 0, 0, 0),
};