From a8cf500c42c751b992f5480c390d6ad2419472e0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:54 +0200 Subject: [PATCH 1/2] arm64: dts: nuvoton: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: nuvoton-npcm845-evb.dtb: l2-cache: 'cache-level' is a required property nuvoton-npcm845-evb.dtb: l2-cache: 'cache-unified' is a required property Reviewed-by: Tomer Maimon Link: https://lore.kernel.org/r/20230421223154.115312-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi index 12118b75c0e6..383938dcd3ce 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi @@ -49,6 +49,8 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; From 1193001081e98d13c786fe0cae407cb747104cdc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:32:01 +0200 Subject: [PATCH 2/2] arm64: dts: lg: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: lg1312-ref.dtb: l2-cache0: 'cache-level' is a required property Acked-by: Chanho Min Link: https://lore.kernel.org/r/20230421223201.115439-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/lg/lg1312.dtsi | 2 ++ arch/arm64/boot/dts/lg/lg1313.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 78ae73d0cf36..48ec4ebec0a8 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -48,6 +48,8 @@ cpu3: cpu@3 { }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index 2173316573be..3869460aa5dc 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -48,6 +48,8 @@ cpu3: cpu@3 { }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; };