From 903caf42eabec2e39d836cb0aa8bbc23717408e7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Mar 2023 22:44:13 +0100 Subject: [PATCH 01/51] soc: qcom: gsbi: mark OF related data as maybe unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver can be compile tested with !CONFIG_OF making certain data unused: drivers/soc/qcom/qcom_gsbi.c:117:34: error: ‘tcsr_dt_match’ defined but not used [-Werror=unused-const-variable=] Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230310214413.275054-1-krzysztof.kozlowski@linaro.org --- drivers/soc/qcom/qcom_gsbi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c index 290bdefbf28a..f1742e5bddb9 100644 --- a/drivers/soc/qcom/qcom_gsbi.c +++ b/drivers/soc/qcom/qcom_gsbi.c @@ -114,7 +114,7 @@ struct gsbi_info { struct regmap *tcsr; }; -static const struct of_device_id tcsr_dt_match[] = { +static const struct of_device_id tcsr_dt_match[] __maybe_unused = { { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064}, { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064}, { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960}, From 4a1b9f4eb122f3e36fdfe62dce96091d3e45132f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:24 -0600 Subject: [PATCH 02/51] soc: qcom: Use of_property_present() for testing DT property presence It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230310144724.1545153-1-robh@kernel.org --- drivers/soc/qcom/qcom_aoss.c | 2 +- drivers/soc/qcom/smem.c | 2 +- drivers/soc/qcom/smsm.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 18c856056475..e376c32cc16e 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -395,7 +395,7 @@ static int qmp_cooling_devices_register(struct qmp *qmp) return -ENOMEM; for_each_available_child_of_node(np, child) { - if (!of_find_property(child, "#cooling-cells", NULL)) + if (!of_property_present(child, "#cooling-cells")) continue; ret = qmp_cooling_device_add(qmp, &qmp->cooling_devs[count++], child); diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 4f163d62942c..25f5925a8d51 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -1045,7 +1045,7 @@ static int qcom_smem_probe(struct platform_device *pdev) int i; num_regions = 1; - if (of_find_property(pdev->dev.of_node, "qcom,rpm-msg-ram", NULL)) + if (of_property_present(pdev->dev.of_node, "qcom,rpm-msg-ram")) num_regions++; array_size = num_regions * sizeof(struct smem_region); diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index 3e8994d6110e..8c137dff7dac 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -510,7 +510,7 @@ static int qcom_smsm_probe(struct platform_device *pdev) return -ENOMEM; for_each_child_of_node(pdev->dev.of_node, local_node) { - if (of_find_property(local_node, "#qcom,smem-state-cells", NULL)) + if (of_property_present(local_node, "#qcom,smem-state-cells")) break; } if (!local_node) { From 34bb2c1c1bb5d36487c1e7ff00dbf49bb91056e2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 23 Jan 2023 21:26:01 +0100 Subject: [PATCH 03/51] soc: qcom: restrict L2 accessors to ARM64 build tests The QCOM_KRYO_L2_ACCESSORS can be compile tested only on ARM64 because it references asm/sysreg.h present only on ARM64. Mark the dependency correct, even though as a non-selectable option it does not have real effect. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230123202601.1296983-1-krzysztof.kozlowski@linaro.org --- drivers/soc/qcom/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a8f283086a21..a25df9e3c70e 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -72,7 +72,7 @@ config QCOM_LLCC config QCOM_KRYO_L2_ACCESSORS bool - depends on ARCH_QCOM && ARM64 || COMPILE_TEST + depends on (ARCH_QCOM || COMPILE_TEST) && ARM64 config QCOM_MDT_LOADER tristate From b5bec0f00ee1c52ff0965a5dba4c91c413a6f3de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Feb 2023 11:15:43 +0100 Subject: [PATCH 04/51] dt-bindings: soc: qcom,apr: correct qcom,intents type The qcom,intents property is a list of pairs, thus it should be defined as uint32-matrix. Fixes: b2d7616e13c4 ("dt-bindings: soc: qcom: apr: add missing properties") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208101545.45711-5-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml index 6026c21736d8..4502458b0669 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -62,7 +62,14 @@ properties: maxItems: 1 qcom,intents: - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 32 + items: + items: + - description: size of each intent to preallocate + - description: amount of intents to preallocate + minimum: 1 description: List of (size, amount) pairs describing what intents should be preallocated for this virtual channel. This can be used to tweak the From b302c64a3c0a005f39155e9aef5e99ad8a9abbb7 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Feb 2023 10:57:51 +0100 Subject: [PATCH 05/51] soc: qcom: smem: update max processor count Update max processor count to reflect the number of co-processors on SA8775P SoCs. Signed-off-by: Bartosz Golaszewski Reviewed-by: Eric Chanudet Tested-by: Eric Chanudet Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230209095753.447347-2-brgl@bgdev.pl --- drivers/soc/qcom/smem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 25f5925a8d51..6be7ea93c78c 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -85,7 +85,7 @@ #define SMEM_GLOBAL_HOST 0xfffe /* Max number of processors/hosts in a system */ -#define SMEM_HOST_COUNT 15 +#define SMEM_HOST_COUNT 20 /** * struct smem_proc_comm - proc_comm communication struct (legacy) From 26a4bf805c6cd88847dd045f6b29d8a20f02d8df Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Feb 2023 10:57:52 +0100 Subject: [PATCH 06/51] dt-bindings: arm: qcom: add the SoC ID for SA8775P Add the SoC ID entry for SA8775P. Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski Reviewed-by: Eric Chanudet Tested-by: Eric Chanudet Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230209095753.447347-3-brgl@bgdev.pl --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index aa95439708dc..c3c078a8c0da 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -229,6 +229,7 @@ #define QCOM_ID_SC7180P 495 #define QCOM_ID_SM6375 507 #define QCOM_ID_SM8550 519 +#define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 #define QCOM_ID_QDU1000 545 #define QCOM_ID_QDU1010 587 From 7fa9c5fc1a753ac593904ebe9c4e8628a4240096 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Feb 2023 10:57:53 +0100 Subject: [PATCH 07/51] soc: qcom: socinfo: add support for SA8775P Add SocInfo support for SA8775P. Signed-off-by: Bartosz Golaszewski Reviewed-by: Eric Chanudet Tested-by: Eric Chanudet # sa8775p-ride Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230209095753.447347-4-brgl@bgdev.pl --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index e9012ca1a87b..6929bef72514 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -442,6 +442,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SC7180P) }, { qcom_board_id(SM6375) }, { qcom_board_id(SM8550) }, + { qcom_board_id(SA8775P) }, { qcom_board_id(QRU1000) }, { qcom_board_id(QDU1000) }, { qcom_board_id(QDU1010) }, From 112d96fd29272726b2a4bc59d027f76fe1e78af3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Feb 2023 22:55:00 +0100 Subject: [PATCH 08/51] soc: qcom: socinfo: Add some PMICs Add some missing PMICs based on the _SUBTYPE defines in include/soc/qcom/qcom-spmi-pmic.h Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230213215500.2131511-1-konrad.dybcio@linaro.org --- drivers/soc/qcom/socinfo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 6929bef72514..89081ec34dba 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -109,15 +109,20 @@ static const char *const pmic_models[] = { [32] = "PM8150B", [33] = "PMK8002", [36] = "PM8009", + [37] = "PMI632", [38] = "PM8150C", + [40] = "PM6150", [41] = "SMB2351", + [44] = "PM8008", [45] = "PM6125", + [46] = "PM7250B", [47] = "PMK8350", [48] = "PM8350", [49] = "PM8350C", [50] = "PM8350B", [51] = "PMR735A", [52] = "PMR735B", + [55] = "PM2250", [58] = "PM8450", [65] = "PM8010", }; From fe8aa1ba078366ba23fc676efab57183b12a3a81 Mon Sep 17 00:00:00 2001 From: Visweswara Tanuku Date: Tue, 14 Feb 2023 21:05:28 -0800 Subject: [PATCH 09/51] soc: qcom: geni-se: Update Tx and Rx fifo depth based on QUP HW version From QUP HW Version 3.10 and above the Tx and Rx fifo depth bits are increased to 23:16 bits from 21:16 bits in SE_HW_PARAM registers accomodating 256bytes of fifo depth. Updated geni_se_get_tx_fifo_depth and geni_se_get_rx_fifo_depth to retrieve right fifo depth based on QUP HW version. Signed-off-by: Visweswara Tanuku Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215050528.9507-1-quic_vtanuku@quicinc.com --- include/linux/soc/qcom/geni-se.h | 42 +++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 400213daa461..c55a0bc8cb0e 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -245,12 +245,22 @@ struct geni_se { /* SE_HW_PARAM_0 fields */ #define TX_FIFO_WIDTH_MSK GENMASK(29, 24) #define TX_FIFO_WIDTH_SHFT 24 +/* + * For QUP HW Version >= 3.10 Tx fifo depth support is increased + * to 256bytes and corresponding bits are 16 to 23 + */ +#define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) #define TX_FIFO_DEPTH_MSK GENMASK(21, 16) #define TX_FIFO_DEPTH_SHFT 16 /* SE_HW_PARAM_1 fields */ #define RX_FIFO_WIDTH_MSK GENMASK(29, 24) #define RX_FIFO_WIDTH_SHFT 24 +/* + * For QUP HW Version >= 3.10 Rx fifo depth support is increased + * to 256bytes and corresponding bits are 16 to 23 + */ +#define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) #define RX_FIFO_DEPTH_MSK GENMASK(21, 16) #define RX_FIFO_DEPTH_SHFT 16 @@ -391,7 +401,8 @@ static inline void geni_se_abort_s_cmd(struct geni_se *se) /** * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine - * @se: Pointer to the concerned serial engine. + * based on QUP HW version + * @se: Pointer to the concerned serial engine. * * This function is used to get the depth i.e. number of elements in the * TX fifo of the serial engine. @@ -400,11 +411,20 @@ static inline void geni_se_abort_s_cmd(struct geni_se *se) */ static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se) { - u32 val; + u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask; + + hw_version = geni_se_get_qup_hw_version(se); + hw_major = GENI_SE_VERSION_MAJOR(hw_version); + hw_minor = GENI_SE_VERSION_MINOR(hw_version); + + if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) + tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES; + else + tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK; val = readl_relaxed(se->base + SE_HW_PARAM_0); - return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT; + return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT; } /** @@ -427,7 +447,8 @@ static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) /** * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine - * @se: Pointer to the concerned serial engine. + * based on QUP HW version + * @se: Pointer to the concerned serial engine. * * This function is used to get the depth i.e. number of elements in the * RX fifo of the serial engine. @@ -436,11 +457,20 @@ static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) */ static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se) { - u32 val; + u32 val, hw_version, hw_major, hw_minor, rx_fifo_depth_mask; + + hw_version = geni_se_get_qup_hw_version(se); + hw_major = GENI_SE_VERSION_MAJOR(hw_version); + hw_minor = GENI_SE_VERSION_MINOR(hw_version); + + if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) + rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK_256_BYTES; + else + rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK; val = readl_relaxed(se->base + SE_HW_PARAM_1); - return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT; + return (val & rx_fifo_depth_mask) >> RX_FIFO_DEPTH_SHFT; } void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr); From f26e18bda9e3b069fbb07a2827597952a6d0afe0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 11:17:26 +0100 Subject: [PATCH 10/51] dt-bindings: arm: qcom,ids: Add IDs for QCM2290/QRB2210 Add the missing IDs for scuba and its QRB variant. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314-topic-scuba_socinfo-v2-1-44fa1256aa6d@linaro.org --- include/dt-bindings/arm/qcom,ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index c3c078a8c0da..197873ed3a17 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -213,6 +213,7 @@ #define QCOM_ID_QCM2150 436 #define QCOM_ID_SDA429W 437 #define QCOM_ID_SM8350 439 +#define QCOM_ID_QCM2290 441 #define QCOM_ID_SM6115 444 #define QCOM_ID_SC8280XP 449 #define QCOM_ID_IPQ6005 453 @@ -229,6 +230,7 @@ #define QCOM_ID_SC7180P 495 #define QCOM_ID_SM6375 507 #define QCOM_ID_SM8550 519 +#define QCOM_ID_QRB2210 524 #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 #define QCOM_ID_QDU1000 545 From 18290c2eec4be239318cb4e01cafe12217e36de8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 11:17:27 +0100 Subject: [PATCH 11/51] soc: qcom: socinfo: Add IDs for QCM2290/QRB2210 Add the missing IDs for scuba and its QRB variant. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314-topic-scuba_socinfo-v2-2-44fa1256aa6d@linaro.org --- drivers/soc/qcom/socinfo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 89081ec34dba..f352cd58630d 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -431,6 +431,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QCM2150) }, { qcom_board_id(SDA429W) }, { qcom_board_id(SM8350) }, + { qcom_board_id(QCM2290) }, { qcom_board_id(SM6115) }, { qcom_board_id(SC8280XP) }, { qcom_board_id(IPQ6005) }, @@ -447,6 +448,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SC7180P) }, { qcom_board_id(SM6375) }, { qcom_board_id(SM8550) }, + { qcom_board_id(QRB2210) }, { qcom_board_id(SA8775P) }, { qcom_board_id(QRU1000) }, { qcom_board_id(QDU1000) }, From 94b1d58f887a147d9a0e8bccc7fffd067c5b9588 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:30 +0530 Subject: [PATCH 12/51] dt-bindings: arm: msm: Update the maintainers for LLCC Both Rishabh and Sai have left Qualcomm, and there is no evidence of them maintaining with a new identity. So their entry needs to be removed. Listed Bjorn as the interim maintainer until someone volunteers to maintain this binding. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-2-manivannan.sadhasivam@linaro.org --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..6570b808fd0d 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Bjorn Andersson description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, From 43aa006e074c4dcaf7493895fb2bd4af16d7c0ab Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:31 +0530 Subject: [PATCH 13/51] dt-bindings: arm: msm: Fix register regions used for LLCC banks Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are split and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by: Parikshit Pareek Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-3-manivannan.sadhasivam@linaro.org --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 6570b808fd0d..93b977428a14 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false examples: - | #include - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = ; + }; }; From ee13b5008707948d3052c1b5aab485c6cd53658e Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:41 +0530 Subject: [PATCH 14/51] qcom: llcc/edac: Fix the base address used for accessing LLCC banks The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, there is no need to rely on reg-names property and the base addresses can be obtained using the index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those need to be defined in devicetree for index from 1..N-1. Reported-by: Parikshit Pareek Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reviewed-by: Borislav Petkov (AMD) Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-13-manivannan.sadhasivam@linaro.org --- drivers/edac/qcom_edac.c | 14 ++---- drivers/soc/qcom/llcc-qcom.c | 78 +++++++++++++++++------------- include/linux/soc/qcom/llcc-qcom.h | 6 +-- 3 files changed, 51 insertions(+), 47 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 3256254c3722..1d3cc1930a74 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) for (i = 0; i < reg_data.reg_cnt; i++) { synd_reg = reg_data.synd_reg + (i * 4); - ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret = regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) reg_data.name, i, synd_val); } - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i = 0; i < drv->num_banks; i++) { - ret = regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret = regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, &drp_error); if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc = IRQ_HANDLED; - ret = regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret = regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, &trp_error); if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..72f3f2a9aaa0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -898,8 +896,8 @@ static int qcom_llcc_remove(struct platform_device *pdev) return 0; } -static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, - const char *name) +static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index, + const char *name) { void __iomem *base; struct regmap_config llcc_regmap_config = { @@ -909,7 +907,7 @@ static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, .fast_io = true, }; - base = devm_platform_ioremap_resource_byname(pdev, name); + base = devm_platform_ioremap_resource(pdev, index); if (IS_ERR(base)) return ERR_CAST(base); @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,21 +933,51 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } - drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret = PTR_ERR(drv_data->regmap); - goto err; - } - - drv_data->bcast_regmap = - qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); - if (IS_ERR(drv_data->bcast_regmap)) { - ret = PTR_ERR(drv_data->bcast_regmap); + /* Initialize the first LLCC bank regmap */ + regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); goto err; } cfg = of_device_get_match_data(&pdev->dev); + ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks); + if (ret) + goto err; + + num_banks &= LLCC_LB_CNT_MASK; + num_banks >>= LLCC_LB_CNT_SHIFT; + drv_data->num_banks = num_banks; + + drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL); + if (!drv_data->regmaps) { + ret = -ENOMEM; + goto err; + } + + drv_data->regmaps[0] = regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i = 1; i < num_banks; i++) { + char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base); + if (IS_ERR(drv_data->regmaps[i])) { + ret = PTR_ERR(drv_data->regmaps[i]); + kfree(base); + goto err; + } + + kfree(base); + } + + drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base"); + if (IS_ERR(drv_data->bcast_regmap)) { + ret = PTR_ERR(drv_data->bcast_regmap); + goto err; + } + /* Extract version of the IP */ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], &version); @@ -957,15 +986,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], - &num_banks); - if (ret) - goto err; - - num_banks &= LLCC_LB_CNT_MASK; - num_banks >>= LLCC_LB_CNT_SHIFT; - drv_data->num_banks = num_banks; - llcc_cfg = cfg->sct_data; sz = cfg->size; @@ -973,16 +993,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices = llcc_cfg[i].slice_id; - drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret = -ENOMEM; - goto err; - } - - for (i = 0; i < num_banks; i++) - drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; - drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index ad1fd718169d..423220e66026 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -120,7 +120,7 @@ struct llcc_edac_reg_offset { /** * struct llcc_drv_data - Data associated with the llcc driver - * @regmap: regmap associated with the llcc device + * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmaps; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; From 721d3e91bfc93975c5e1a76c7d588dd8df5d82da Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:42 +0530 Subject: [PATCH 15/51] qcom: llcc/edac: Support polling mode for ECC handling Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosen based on Qcom downstream/vendor driver. Reported-by: Luca Weiss Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reviewed-by: Borislav Petkov (AMD) Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-14-manivannan.sadhasivam@linaro.org --- drivers/edac/qcom_edac.c | 52 +++++++++++++++++++++--------------- drivers/soc/qcom/llcc-qcom.c | 13 +++++---- 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 1d3cc1930a74..265e0fb39bc7 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -76,6 +76,8 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 +#define ECC_POLL_MSEC 5000 + enum { LLCC_DRAM_CE = 0, LLCC_DRAM_UE, @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) return ret; } -static irqreturn_t -llcc_ecc_irq_handler(int irq, void *edev_ctl) +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) return irq_rc; } +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) +{ + llcc_ecc_irq_handler(0, edev_ctl); +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; @@ -355,30 +361,32 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) edev_ctl->ctl_name = "llcc"; edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; + /* Check if LLCC driver has passed ECC IRQ */ + ecc_irq = llcc_driv_data->ecc_irq; + if (ecc_irq > 0) { + /* Use interrupt mode if IRQ is available */ + rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); + if (!rc) { + edac_op_state = EDAC_OPSTATE_INT; + goto irq_done; + } + } + + /* Fall back to polling mode otherwise */ + edev_ctl->poll_msec = ECC_POLL_MSEC; + edev_ctl->edac_check = llcc_ecc_check; + edac_op_state = EDAC_OPSTATE_POLL; + +irq_done: rc = edac_device_add_device(edev_ctl); - if (rc) - goto out_mem; + if (rc) { + edac_device_free_ctl_info(edev_ctl); + return rc; + } platform_set_drvdata(pdev, edev_ctl); - /* Request for ecc irq */ - ecc_irq = llcc_driv_data->ecc_irq; - if (ecc_irq < 0) { - rc = -ENODEV; - goto out_dev; - } - rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, - IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); - if (rc) - goto out_dev; - - return rc; - -out_dev: - edac_device_del_device(edev_ctl->dev); -out_mem: - edac_device_free_ctl_info(edev_ctl); - return rc; } diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 72f3f2a9aaa0..7b7c5a38bac6 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >= 0) { - llcc_edac = platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); - } + + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); return 0; err: From cca94f1dd6d0a4c7e5c8190672f5747e3c00ddde Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:43 +0530 Subject: [PATCH 16/51] soc: qcom: llcc: Do not create EDAC platform device on SDM845 The platforms based on SDM845 SoC locks the access to EDAC registers in the bootloader. So probing the EDAC driver will result in a crash. Hence, disable the creation of EDAC platform device on all SDM845 devices. The issue has been observed on Lenovo Yoga C630 and DB845c. While at it, also sort the members of `struct qcom_llcc_config` to avoid any holes in-between. Cc: # 5.10 Reported-by: Steev Klimaszewski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-15-manivannan.sadhasivam@linaro.org --- drivers/soc/qcom/llcc-qcom.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 7b7c5a38bac6..a5140f19f200 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -120,10 +120,11 @@ struct llcc_slice_config { struct qcom_llcc_config { const struct llcc_slice_config *sct_data; - int size; - bool need_llcc_cfg; const u32 *reg_offset; const struct llcc_edac_reg_offset *edac_reg_offset; + int size; + bool need_llcc_cfg; + bool no_edac; }; enum llcc_reg_offset { @@ -452,6 +453,7 @@ static const struct qcom_llcc_config sdm845_cfg = { .need_llcc_cfg = false, .reg_offset = llcc_v1_reg_offset, .edac_reg_offset = &llcc_v1_edac_reg_offset, + .no_edac = true, }; static const struct qcom_llcc_config sm6350_cfg = { @@ -1012,11 +1014,19 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - llcc_edac = platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); + /* + * On some platforms, the access to EDAC registers will be locked by + * the bootloader. So probing the EDAC driver will result in a crash. + * Hence, disable the creation of EDAC platform device for the + * problematic platforms. + */ + if (!cfg->no_edac) { + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); + } return 0; err: From fd972da1b228974f788c115d37abe209828ca5a9 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 14 Mar 2023 11:43:33 +0530 Subject: [PATCH 17/51] dt-bindings: arm: qcom,ids: Add IDs for IPQ9574 and its variants Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550, IPQ9514 and IPQ9510 Signed-off-by: Varadarajan Narayanan Acked-by: Krzysztof Kozlowski Reviewed-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1678774414-14414-2-git-send-email-quic_varada@quicinc.com --- include/dt-bindings/arm/qcom,ids.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 197873ed3a17..c3cc440dec33 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -229,7 +229,13 @@ #define QCOM_ID_SC7280 487 #define QCOM_ID_SC7180P 495 #define QCOM_ID_SM6375 507 +#define QCOM_ID_IPQ9514 510 +#define QCOM_ID_IPQ9550 511 +#define QCOM_ID_IPQ9554 512 +#define QCOM_ID_IPQ9570 513 +#define QCOM_ID_IPQ9574 514 #define QCOM_ID_SM8550 519 +#define QCOM_ID_IPQ9510 521 #define QCOM_ID_QRB2210 524 #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 From c6653d8f24f4bcc255e3ffb28c629ff5d0e0ba13 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 14 Mar 2023 11:43:34 +0530 Subject: [PATCH 18/51] soc: qcom: socinfo: Add IDs for IPQ9574 and its variants Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550, IPQ9514 and IPQ9510 Signed-off-by: Varadarajan Narayanan Reviewed-by: Krzysztof Kozlowski Reviewed-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1678774414-14414-3-git-send-email-quic_varada@quicinc.com --- drivers/soc/qcom/socinfo.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index f352cd58630d..cc1204ae2198 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -447,7 +447,13 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SC7280) }, { qcom_board_id(SC7180P) }, { qcom_board_id(SM6375) }, + { qcom_board_id(IPQ9514) }, + { qcom_board_id(IPQ9550) }, + { qcom_board_id(IPQ9554) }, + { qcom_board_id(IPQ9570) }, + { qcom_board_id(IPQ9574) }, { qcom_board_id(SM8550) }, + { qcom_board_id(IPQ9510) }, { qcom_board_id(QRB2210) }, { qcom_board_id(SA8775P) }, { qcom_board_id(QRU1000) }, From ee6ae544ddfabe60245d4eaee41a7330acd46d94 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Wed, 15 Mar 2023 21:31:50 +0530 Subject: [PATCH 19/51] dt-bindings: arm: qcom,ids: Add IDs for QRB4210 Add the ID for QRB4210 variant. Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315160151.2166861-2-bhupesh.sharma@linaro.org --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index c3cc440dec33..cd7a95756ea1 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -236,6 +236,7 @@ #define QCOM_ID_IPQ9574 514 #define QCOM_ID_SM8550 519 #define QCOM_ID_IPQ9510 521 +#define QCOM_ID_QRB4210 523 #define QCOM_ID_QRB2210 524 #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 From a11bc4a5b371e05e89c0fba5756efe5788a4d1ab Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Wed, 15 Mar 2023 21:31:51 +0530 Subject: [PATCH 20/51] soc: qcom: socinfo: Add IDs for QRB4210 Add the ID for QRB4210 variant. Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315160151.2166861-3-bhupesh.sharma@linaro.org --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index cc1204ae2198..cd370fe28d19 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -454,6 +454,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(IPQ9574) }, { qcom_board_id(SM8550) }, { qcom_board_id(IPQ9510) }, + { qcom_board_id(QRB4210) }, { qcom_board_id(QRB2210) }, { qcom_board_id(SA8775P) }, { qcom_board_id(QRU1000) }, From de7aeee0d942d2e1d85b3db3652e037af38e24d7 Mon Sep 17 00:00:00 2001 From: David Wronek Date: Sun, 5 Mar 2023 22:17:44 +0300 Subject: [PATCH 21/51] dt-bindings: arm: qcom,ids: Add Soc ID for SM7150 Add the ID for the Qualcomm SM7150 SoC. Signed-off-by: David Wronek Signed-off-by: Danila Tikhonov Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305191745.386862-2-danila@jiaxyga.com --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index cd7a95756ea1..802495b20276 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -192,6 +192,7 @@ #define QCOM_ID_SA8155 362 #define QCOM_ID_SDA439 363 #define QCOM_ID_SDA429 364 +#define QCOM_ID_SM7150 365 #define QCOM_ID_IPQ8070 375 #define QCOM_ID_IPQ8071 376 #define QCOM_ID_QM215 386 From bad8cdc20690fa830c49783b68c6403dd44bc0bd Mon Sep 17 00:00:00 2001 From: David Wronek Date: Sun, 5 Mar 2023 22:17:45 +0300 Subject: [PATCH 22/51] soc: qcom: socinfo: Add Soc ID for SM7150 Add Soc ID table entries for Qualcomm SM7150. Signed-off-by: David Wronek Signed-off-by: Danila Tikhonov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305191745.386862-3-danila@jiaxyga.com --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index cd370fe28d19..c2e4a57dd666 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -410,6 +410,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SA8155) }, { qcom_board_id(SDA439) }, { qcom_board_id(SDA429) }, + { qcom_board_id(SM7150) }, { qcom_board_id(IPQ8070) }, { qcom_board_id(IPQ8071) }, { qcom_board_id(QM215) }, From f1eb5e6fc18c5e6f4ee7fd2985743f2fe7978951 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 20:59:59 +0100 Subject: [PATCH 23/51] soc: qcom: rpmpd: Remove SoC names from RPMPD definitions Replace the SoC names with type+id_key (or type+id+..name..+key for fixed-key definitions) and remove duplicate entries. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-1-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 360 ++++++++++++++++++--------------------- 1 file changed, 164 insertions(+), 196 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 337b1ad1cd3b..d99a56509e33 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -40,51 +40,50 @@ #define MAX_CORNER_RPMPD_STATE 6 -#define DEFINE_RPMPD_PAIR(_platform, _name, _active, r_type, r_key, \ - r_id) \ - static struct rpmpd _platform##_##_active; \ - static struct rpmpd _platform##_##_name = { \ +#define DEFINE_RPMPD_PAIR(_name, _active, r_type, r_key, r_id) \ + static struct rpmpd r_type##r_id##_##r_key##_##_active; \ + static struct rpmpd r_type##r_id##_##r_key##_##_name = { \ .pd = { .name = #_name, }, \ - .peer = &_platform##_##_active, \ + .peer = &r_type##r_id##_##r_key##_##_active, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ .key = KEY_##r_key, \ }; \ - static struct rpmpd _platform##_##_active = { \ + static struct rpmpd r_type##r_id##_##r_key##_##_active = { \ .pd = { .name = #_active, }, \ - .peer = &_platform##_##_name, \ + .peer = &r_type##r_id##_##r_key##_##_name, \ .active_only = true, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ .key = KEY_##r_key, \ } -#define DEFINE_RPMPD_CORNER(_platform, _name, r_type, r_id) \ - static struct rpmpd _platform##_##_name = { \ +#define DEFINE_RPMPD_CORNER(_name, r_type, r_id) \ + static struct rpmpd r_type##r_id##_##_name##_corner = { \ .pd = { .name = #_name, }, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ .key = KEY_CORNER, \ } -#define DEFINE_RPMPD_LEVEL(_platform, _name, r_type, r_id) \ - static struct rpmpd _platform##_##_name = { \ +#define DEFINE_RPMPD_LEVEL(_name, r_type, r_id) \ + static struct rpmpd r_type##r_id##_##_name##_lvl = { \ .pd = { .name = #_name, }, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ .key = KEY_LEVEL, \ } -#define DEFINE_RPMPD_VFC(_platform, _name, r_type, r_id) \ - static struct rpmpd _platform##_##_name = { \ +#define DEFINE_RPMPD_VFC(_name, r_type, r_id) \ + static struct rpmpd r_type##r_id##_##_name = { \ .pd = { .name = #_name, }, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ .key = KEY_FLOOR_CORNER, \ } -#define DEFINE_RPMPD_VFL(_platform, _name, r_type, r_id) \ - static struct rpmpd _platform##_##_name = { \ +#define DEFINE_RPMPD_VFL(_name, r_type, r_id) \ + static struct rpmpd r_type##r_id##_##_name = { \ .pd = { .name = #_name, }, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ @@ -119,18 +118,18 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); /* mdm9607 RPM Power Domains */ -DEFINE_RPMPD_PAIR(mdm9607, vddcx, vddcx_ao, SMPA, LEVEL, 3); -DEFINE_RPMPD_VFL(mdm9607, vddcx_vfl, SMPA, 3); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 3); +DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 3); -DEFINE_RPMPD_PAIR(mdm9607, vddmx, vddmx_ao, LDOA, LEVEL, 12); -DEFINE_RPMPD_VFL(mdm9607, vddmx_vfl, LDOA, 12); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, LEVEL, 12); +DEFINE_RPMPD_VFL(vddmx_vfl, LDOA, 12); static struct rpmpd *mdm9607_rpmpds[] = { - [MDM9607_VDDCX] = &mdm9607_vddcx, - [MDM9607_VDDCX_AO] = &mdm9607_vddcx_ao, - [MDM9607_VDDCX_VFL] = &mdm9607_vddcx_vfl, - [MDM9607_VDDMX] = &mdm9607_vddmx, - [MDM9607_VDDMX_AO] = &mdm9607_vddmx_ao, - [MDM9607_VDDMX_VFL] = &mdm9607_vddmx_vfl, + [MDM9607_VDDCX] = &SMPA3_LEVEL_vddcx, + [MDM9607_VDDCX_AO] = &SMPA3_LEVEL_vddcx_ao, + [MDM9607_VDDCX_VFL] = &SMPA3_vddcx_vfl, + [MDM9607_VDDMX] = &LDOA12_LEVEL_vddmx, + [MDM9607_VDDMX_AO] = &LDOA12_LEVEL_vddmx_ao, + [MDM9607_VDDMX_VFL] = &LDOA12_vddmx_vfl, }; static const struct rpmpd_desc mdm9607_desc = { @@ -140,13 +139,13 @@ static const struct rpmpd_desc mdm9607_desc = { }; /* msm8226 RPM Power Domains */ -DEFINE_RPMPD_PAIR(msm8226, vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_VFC(msm8226, vddcx_vfc, SMPA, 1); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 1); static struct rpmpd *msm8226_rpmpds[] = { - [MSM8226_VDDCX] = &msm8226_vddcx, - [MSM8226_VDDCX_AO] = &msm8226_vddcx_ao, - [MSM8226_VDDCX_VFC] = &msm8226_vddcx_vfc, + [MSM8226_VDDCX] = &SMPA1_CORNER_vddcx, + [MSM8226_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, + [MSM8226_VDDCX_VFC] = &SMPA1_vddcx_vfc, }; static const struct rpmpd_desc msm8226_desc = { @@ -156,23 +155,23 @@ static const struct rpmpd_desc msm8226_desc = { }; /* msm8939 RPM Power Domains */ -DEFINE_RPMPD_PAIR(msm8939, vddmd, vddmd_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_VFC(msm8939, vddmd_vfc, SMPA, 1); +DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_VFC(vddmd_vfc, SMPA, 1); -DEFINE_RPMPD_PAIR(msm8939, vddcx, vddcx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_VFC(msm8939, vddcx_vfc, SMPA, 2); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 2); -DEFINE_RPMPD_PAIR(msm8939, vddmx, vddmx_ao, LDOA, CORNER, 3); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, CORNER, 3); static struct rpmpd *msm8939_rpmpds[] = { - [MSM8939_VDDMDCX] = &msm8939_vddmd, - [MSM8939_VDDMDCX_AO] = &msm8939_vddmd_ao, - [MSM8939_VDDMDCX_VFC] = &msm8939_vddmd_vfc, - [MSM8939_VDDCX] = &msm8939_vddcx, - [MSM8939_VDDCX_AO] = &msm8939_vddcx_ao, - [MSM8939_VDDCX_VFC] = &msm8939_vddcx_vfc, - [MSM8939_VDDMX] = &msm8939_vddmx, - [MSM8939_VDDMX_AO] = &msm8939_vddmx_ao, + [MSM8939_VDDMDCX] = &SMPA1_CORNER_vddmd, + [MSM8939_VDDMDCX_AO] = &SMPA1_CORNER_vddmd_ao, + [MSM8939_VDDMDCX_VFC] = &SMPA1_vddmd_vfc, + [MSM8939_VDDCX] = &SMPA2_CORNER_vddcx, + [MSM8939_VDDCX_AO] = &SMPA2_CORNER_vddcx_ao, + [MSM8939_VDDCX_VFC] = &SMPA2_vddcx_vfc, + [MSM8939_VDDMX] = &LDOA3_CORNER_vddmx, + [MSM8939_VDDMX_AO] = &LDOA3_CORNER_vddmx_ao, }; static const struct rpmpd_desc msm8939_desc = { @@ -182,17 +181,12 @@ static const struct rpmpd_desc msm8939_desc = { }; /* msm8916 RPM Power Domains */ -DEFINE_RPMPD_PAIR(msm8916, vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(msm8916, vddmx, vddmx_ao, LDOA, CORNER, 3); - -DEFINE_RPMPD_VFC(msm8916, vddcx_vfc, SMPA, 1); - static struct rpmpd *msm8916_rpmpds[] = { - [MSM8916_VDDCX] = &msm8916_vddcx, - [MSM8916_VDDCX_AO] = &msm8916_vddcx_ao, - [MSM8916_VDDCX_VFC] = &msm8916_vddcx_vfc, - [MSM8916_VDDMX] = &msm8916_vddmx, - [MSM8916_VDDMX_AO] = &msm8916_vddmx_ao, + [MSM8916_VDDCX] = &SMPA1_CORNER_vddcx, + [MSM8916_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, + [MSM8916_VDDCX_VFC] = &SMPA1_vddcx_vfc, + [MSM8916_VDDMX] = &LDOA3_CORNER_vddmx, + [MSM8916_VDDMX_AO] = &LDOA3_CORNER_vddmx_ao, }; static const struct rpmpd_desc msm8916_desc = { @@ -202,20 +196,20 @@ static const struct rpmpd_desc msm8916_desc = { }; /* msm8953 RPM Power Domains */ -DEFINE_RPMPD_PAIR(msm8953, vddmd, vddmd_ao, SMPA, LEVEL, 1); -DEFINE_RPMPD_PAIR(msm8953, vddcx, vddcx_ao, SMPA, LEVEL, 2); -DEFINE_RPMPD_PAIR(msm8953, vddmx, vddmx_ao, SMPA, LEVEL, 7); +DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, LEVEL, 1); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 2); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 7); -DEFINE_RPMPD_VFL(msm8953, vddcx_vfl, SMPA, 2); +DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 2); static struct rpmpd *msm8953_rpmpds[] = { - [MSM8953_VDDMD] = &msm8953_vddmd, - [MSM8953_VDDMD_AO] = &msm8953_vddmd_ao, - [MSM8953_VDDCX] = &msm8953_vddcx, - [MSM8953_VDDCX_AO] = &msm8953_vddcx_ao, - [MSM8953_VDDCX_VFL] = &msm8953_vddcx_vfl, - [MSM8953_VDDMX] = &msm8953_vddmx, - [MSM8953_VDDMX_AO] = &msm8953_vddmx_ao, + [MSM8953_VDDMD] = &SMPA1_LEVEL_vddmd, + [MSM8953_VDDMD_AO] = &SMPA1_LEVEL_vddmd_ao, + [MSM8953_VDDCX] = &SMPA2_LEVEL_vddcx, + [MSM8953_VDDCX_AO] = &SMPA2_LEVEL_vddcx_ao, + [MSM8953_VDDCX_VFL] = &SMPA2_vddcx_vfl, + [MSM8953_VDDMX] = &SMPA7_LEVEL_vddmx, + [MSM8953_VDDMX_AO] = &SMPA7_LEVEL_vddmx_ao, }; static const struct rpmpd_desc msm8953_desc = { @@ -225,19 +219,18 @@ static const struct rpmpd_desc msm8953_desc = { }; /* msm8976 RPM Power Domains */ -DEFINE_RPMPD_PAIR(msm8976, vddcx, vddcx_ao, SMPA, LEVEL, 2); -DEFINE_RPMPD_PAIR(msm8976, vddmx, vddmx_ao, SMPA, LEVEL, 6); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 6); -DEFINE_RPMPD_VFL(msm8976, vddcx_vfl, RWSC, 2); -DEFINE_RPMPD_VFL(msm8976, vddmx_vfl, RWSM, 6); +DEFINE_RPMPD_VFL(vddcx_vfl, RWSC, 2); +DEFINE_RPMPD_VFL(vddmx_vfl, RWSM, 6); static struct rpmpd *msm8976_rpmpds[] = { - [MSM8976_VDDCX] = &msm8976_vddcx, - [MSM8976_VDDCX_AO] = &msm8976_vddcx_ao, - [MSM8976_VDDCX_VFL] = &msm8976_vddcx_vfl, - [MSM8976_VDDMX] = &msm8976_vddmx, - [MSM8976_VDDMX_AO] = &msm8976_vddmx_ao, - [MSM8976_VDDMX_VFL] = &msm8976_vddmx_vfl, + [MSM8976_VDDCX] = &SMPA2_LEVEL_vddcx, + [MSM8976_VDDCX_AO] = &SMPA2_LEVEL_vddcx_ao, + [MSM8976_VDDCX_VFL] = &RWSC2_vddcx_vfl, + [MSM8976_VDDMX] = &SMPA6_LEVEL_vddmx, + [MSM8976_VDDMX_AO] = &SMPA6_LEVEL_vddmx_ao, + [MSM8976_VDDMX_VFL] = &RWSM6_vddmx_vfl, }; static const struct rpmpd_desc msm8976_desc = { @@ -247,22 +240,20 @@ static const struct rpmpd_desc msm8976_desc = { }; /* msm8994 RPM Power domains */ -DEFINE_RPMPD_PAIR(msm8994, vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(msm8994, vddmx, vddmx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, CORNER, 2); /* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */ -DEFINE_RPMPD_CORNER(msm8994, vddgfx, SMPB, 2); +DEFINE_RPMPD_CORNER(vddgfx, SMPB, 2); -DEFINE_RPMPD_VFC(msm8994, vddcx_vfc, SMPA, 1); -DEFINE_RPMPD_VFC(msm8994, vddgfx_vfc, SMPB, 2); +DEFINE_RPMPD_VFC(vddgfx_vfc, SMPB, 2); static struct rpmpd *msm8994_rpmpds[] = { - [MSM8994_VDDCX] = &msm8994_vddcx, - [MSM8994_VDDCX_AO] = &msm8994_vddcx_ao, - [MSM8994_VDDCX_VFC] = &msm8994_vddcx_vfc, - [MSM8994_VDDMX] = &msm8994_vddmx, - [MSM8994_VDDMX_AO] = &msm8994_vddmx_ao, - [MSM8994_VDDGFX] = &msm8994_vddgfx, - [MSM8994_VDDGFX_VFC] = &msm8994_vddgfx_vfc, + [MSM8994_VDDCX] = &SMPA1_CORNER_vddcx, + [MSM8994_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, + [MSM8994_VDDCX_VFC] = &SMPA1_vddcx_vfc, + [MSM8994_VDDMX] = &SMPA2_CORNER_vddmx, + [MSM8994_VDDMX_AO] = &SMPA2_CORNER_vddmx_ao, + [MSM8994_VDDGFX] = &SMPB2_vddgfx_corner, + [MSM8994_VDDGFX_VFC] = &SMPB2_vddgfx_vfc, }; static const struct rpmpd_desc msm8994_desc = { @@ -272,21 +263,18 @@ static const struct rpmpd_desc msm8994_desc = { }; /* msm8996 RPM Power domains */ -DEFINE_RPMPD_PAIR(msm8996, vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(msm8996, vddmx, vddmx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_CORNER(msm8996, vddsscx, LDOA, 26); +DEFINE_RPMPD_CORNER(vddsscx, LDOA, 26); -DEFINE_RPMPD_VFC(msm8996, vddcx_vfc, SMPA, 1); -DEFINE_RPMPD_VFC(msm8996, vddsscx_vfc, LDOA, 26); +DEFINE_RPMPD_VFC(vddsscx_vfc, LDOA, 26); static struct rpmpd *msm8996_rpmpds[] = { - [MSM8996_VDDCX] = &msm8996_vddcx, - [MSM8996_VDDCX_AO] = &msm8996_vddcx_ao, - [MSM8996_VDDCX_VFC] = &msm8996_vddcx_vfc, - [MSM8996_VDDMX] = &msm8996_vddmx, - [MSM8996_VDDMX_AO] = &msm8996_vddmx_ao, - [MSM8996_VDDSSCX] = &msm8996_vddsscx, - [MSM8996_VDDSSCX_VFC] = &msm8996_vddsscx_vfc, + [MSM8996_VDDCX] = &SMPA1_CORNER_vddcx, + [MSM8996_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, + [MSM8996_VDDCX_VFC] = &SMPA1_vddcx_vfc, + [MSM8996_VDDMX] = &SMPA2_CORNER_vddmx, + [MSM8996_VDDMX_AO] = &SMPA2_CORNER_vddmx_ao, + [MSM8996_VDDSSCX] = &LDOA26_vddsscx_corner, + [MSM8996_VDDSSCX_VFC] = &LDOA26_vddsscx_vfc, }; static const struct rpmpd_desc msm8996_desc = { @@ -296,29 +284,29 @@ static const struct rpmpd_desc msm8996_desc = { }; /* msm8998 RPM Power domains */ -DEFINE_RPMPD_PAIR(msm8998, vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_VFL(msm8998, vddcx_vfl, RWCX, 0); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, RWCX, LEVEL, 0); +DEFINE_RPMPD_VFL(vddcx_vfl, RWCX, 0); -DEFINE_RPMPD_PAIR(msm8998, vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(msm8998, vddmx_vfl, RWMX, 0); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, RWMX, LEVEL, 0); +DEFINE_RPMPD_VFL(vddmx_vfl, RWMX, 0); -DEFINE_RPMPD_LEVEL(msm8998, vdd_ssccx, RWSC, 0); -DEFINE_RPMPD_VFL(msm8998, vdd_ssccx_vfl, RWSC, 0); +DEFINE_RPMPD_LEVEL(vdd_ssccx, RWSC, 0); +DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWSC, 0); -DEFINE_RPMPD_LEVEL(msm8998, vdd_sscmx, RWSM, 0); -DEFINE_RPMPD_VFL(msm8998, vdd_sscmx_vfl, RWSM, 0); +DEFINE_RPMPD_LEVEL(vdd_sscmx, RWSM, 0); +DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWSM, 0); static struct rpmpd *msm8998_rpmpds[] = { - [MSM8998_VDDCX] = &msm8998_vddcx, - [MSM8998_VDDCX_AO] = &msm8998_vddcx_ao, - [MSM8998_VDDCX_VFL] = &msm8998_vddcx_vfl, - [MSM8998_VDDMX] = &msm8998_vddmx, - [MSM8998_VDDMX_AO] = &msm8998_vddmx_ao, - [MSM8998_VDDMX_VFL] = &msm8998_vddmx_vfl, - [MSM8998_SSCCX] = &msm8998_vdd_ssccx, - [MSM8998_SSCCX_VFL] = &msm8998_vdd_ssccx_vfl, - [MSM8998_SSCMX] = &msm8998_vdd_sscmx, - [MSM8998_SSCMX_VFL] = &msm8998_vdd_sscmx_vfl, + [MSM8998_VDDCX] = &RWCX0_LEVEL_vddcx, + [MSM8998_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [MSM8998_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [MSM8998_VDDMX] = &RWMX0_LEVEL_vddmx, + [MSM8998_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [MSM8998_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [MSM8998_SSCCX] = &RWSC0_vdd_ssccx_lvl, + [MSM8998_SSCCX_VFL] = &RWSC0_vdd_ssccx_vfl, + [MSM8998_SSCMX] = &RWSM0_vdd_sscmx_lvl, + [MSM8998_SSCMX_VFL] = &RWSM0_vdd_sscmx_vfl, }; static const struct rpmpd_desc msm8998_desc = { @@ -328,23 +316,20 @@ static const struct rpmpd_desc msm8998_desc = { }; /* qcs404 RPM Power domains */ -DEFINE_RPMPD_PAIR(qcs404, vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(qcs404, vddmx_vfl, RWMX, 0); +DEFINE_RPMPD_LEVEL(vdd_lpicx, RWLC, 0); +DEFINE_RPMPD_VFL(vdd_lpicx_vfl, RWLC, 0); -DEFINE_RPMPD_LEVEL(qcs404, vdd_lpicx, RWLC, 0); -DEFINE_RPMPD_VFL(qcs404, vdd_lpicx_vfl, RWLC, 0); - -DEFINE_RPMPD_LEVEL(qcs404, vdd_lpimx, RWLM, 0); -DEFINE_RPMPD_VFL(qcs404, vdd_lpimx_vfl, RWLM, 0); +DEFINE_RPMPD_LEVEL(vdd_lpimx, RWLM, 0); +DEFINE_RPMPD_VFL(vdd_lpimx_vfl, RWLM, 0); static struct rpmpd *qcs404_rpmpds[] = { - [QCS404_VDDMX] = &qcs404_vddmx, - [QCS404_VDDMX_AO] = &qcs404_vddmx_ao, - [QCS404_VDDMX_VFL] = &qcs404_vddmx_vfl, - [QCS404_LPICX] = &qcs404_vdd_lpicx, - [QCS404_LPICX_VFL] = &qcs404_vdd_lpicx_vfl, - [QCS404_LPIMX] = &qcs404_vdd_lpimx, - [QCS404_LPIMX_VFL] = &qcs404_vdd_lpimx_vfl, + [QCS404_VDDMX] = &RWMX0_LEVEL_vddmx, + [QCS404_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [QCS404_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [QCS404_LPICX] = &RWLC0_vdd_lpicx_lvl, + [QCS404_LPICX_VFL] = &RWLC0_vdd_lpicx_vfl, + [QCS404_LPIMX] = &RWLM0_vdd_lpimx_lvl, + [QCS404_LPIMX_VFL] = &RWLM0_vdd_lpimx_vfl, }; static const struct rpmpd_desc qcs404_desc = { @@ -354,29 +339,24 @@ static const struct rpmpd_desc qcs404_desc = { }; /* sdm660 RPM Power domains */ -DEFINE_RPMPD_PAIR(sdm660, vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_VFL(sdm660, vddcx_vfl, RWCX, 0); -DEFINE_RPMPD_PAIR(sdm660, vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(sdm660, vddmx_vfl, RWMX, 0); +DEFINE_RPMPD_LEVEL(vdd_ssccx, RWLC, 0); +DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWLC, 0); -DEFINE_RPMPD_LEVEL(sdm660, vdd_ssccx, RWLC, 0); -DEFINE_RPMPD_VFL(sdm660, vdd_ssccx_vfl, RWLC, 0); - -DEFINE_RPMPD_LEVEL(sdm660, vdd_sscmx, RWLM, 0); -DEFINE_RPMPD_VFL(sdm660, vdd_sscmx_vfl, RWLM, 0); +DEFINE_RPMPD_LEVEL(vdd_sscmx, RWLM, 0); +DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWLM, 0); static struct rpmpd *sdm660_rpmpds[] = { - [SDM660_VDDCX] = &sdm660_vddcx, - [SDM660_VDDCX_AO] = &sdm660_vddcx_ao, - [SDM660_VDDCX_VFL] = &sdm660_vddcx_vfl, - [SDM660_VDDMX] = &sdm660_vddmx, - [SDM660_VDDMX_AO] = &sdm660_vddmx_ao, - [SDM660_VDDMX_VFL] = &sdm660_vddmx_vfl, - [SDM660_SSCCX] = &sdm660_vdd_ssccx, - [SDM660_SSCCX_VFL] = &sdm660_vdd_ssccx_vfl, - [SDM660_SSCMX] = &sdm660_vdd_sscmx, - [SDM660_SSCMX_VFL] = &sdm660_vdd_sscmx_vfl, + [SDM660_VDDCX] = &RWCX0_LEVEL_vddcx, + [SDM660_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [SDM660_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [SDM660_VDDMX] = &RWMX0_LEVEL_vddmx, + [SDM660_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [SDM660_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [SDM660_SSCCX] = &RWLC0_vdd_ssccx_lvl, + [SDM660_SSCCX_VFL] = &RWLC0_vdd_ssccx_vfl, + [SDM660_SSCMX] = &RWLM0_vdd_sscmx_lvl, + [SDM660_SSCMX_VFL] = &RWLM0_vdd_sscmx_vfl, }; static const struct rpmpd_desc sdm660_desc = { @@ -386,24 +366,18 @@ static const struct rpmpd_desc sdm660_desc = { }; /* sm4250/6115 RPM Power domains */ -DEFINE_RPMPD_PAIR(sm6115, vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_VFL(sm6115, vddcx_vfl, RWCX, 0); - -DEFINE_RPMPD_PAIR(sm6115, vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(sm6115, vddmx_vfl, RWMX, 0); - -DEFINE_RPMPD_LEVEL(sm6115, vdd_lpi_cx, RWLC, 0); -DEFINE_RPMPD_LEVEL(sm6115, vdd_lpi_mx, RWLM, 0); +DEFINE_RPMPD_LEVEL(vdd_lpi_cx, RWLC, 0); +DEFINE_RPMPD_LEVEL(vdd_lpi_mx, RWLM, 0); static struct rpmpd *sm6115_rpmpds[] = { - [SM6115_VDDCX] = &sm6115_vddcx, - [SM6115_VDDCX_AO] = &sm6115_vddcx_ao, - [SM6115_VDDCX_VFL] = &sm6115_vddcx_vfl, - [SM6115_VDDMX] = &sm6115_vddmx, - [SM6115_VDDMX_AO] = &sm6115_vddmx_ao, - [SM6115_VDDMX_VFL] = &sm6115_vddmx_vfl, - [SM6115_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, - [SM6115_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, + [SM6115_VDDCX] = &RWCX0_LEVEL_vddcx, + [SM6115_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [SM6115_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [SM6115_VDDMX] = &RWMX0_LEVEL_vddmx, + [SM6115_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [SM6115_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [SM6115_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, + [SM6115_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, }; static const struct rpmpd_desc sm6115_desc = { @@ -413,19 +387,13 @@ static const struct rpmpd_desc sm6115_desc = { }; /* sm6125 RPM Power domains */ -DEFINE_RPMPD_PAIR(sm6125, vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_VFL(sm6125, vddcx_vfl, RWCX, 0); - -DEFINE_RPMPD_PAIR(sm6125, vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(sm6125, vddmx_vfl, RWMX, 0); - static struct rpmpd *sm6125_rpmpds[] = { - [SM6125_VDDCX] = &sm6125_vddcx, - [SM6125_VDDCX_AO] = &sm6125_vddcx_ao, - [SM6125_VDDCX_VFL] = &sm6125_vddcx_vfl, - [SM6125_VDDMX] = &sm6125_vddmx, - [SM6125_VDDMX_AO] = &sm6125_vddmx_ao, - [SM6125_VDDMX_VFL] = &sm6125_vddmx_vfl, + [SM6125_VDDCX] = &RWCX0_LEVEL_vddcx, + [SM6125_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [SM6125_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [SM6125_VDDMX] = &RWMX0_LEVEL_vddmx, + [SM6125_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [SM6125_VDDMX_VFL] = &RWMX0_vddmx_vfl, }; static const struct rpmpd_desc sm6125_desc = { @@ -434,18 +402,18 @@ static const struct rpmpd_desc sm6125_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; -DEFINE_RPMPD_PAIR(sm6375, vddgx, vddgx_ao, RWGX, LEVEL, 0); +DEFINE_RPMPD_PAIR(vddgx, vddgx_ao, RWGX, LEVEL, 0); static struct rpmpd *sm6375_rpmpds[] = { - [SM6375_VDDCX] = &sm6125_vddcx, - [SM6375_VDDCX_AO] = &sm6125_vddcx_ao, - [SM6375_VDDCX_VFL] = &sm6125_vddcx_vfl, - [SM6375_VDDMX] = &sm6125_vddmx, - [SM6375_VDDMX_AO] = &sm6125_vddmx_ao, - [SM6375_VDDMX_VFL] = &sm6125_vddmx_vfl, - [SM6375_VDDGX] = &sm6375_vddgx, - [SM6375_VDDGX_AO] = &sm6375_vddgx_ao, - [SM6375_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, - [SM6375_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, + [SM6375_VDDCX] = &RWCX0_LEVEL_vddcx, + [SM6375_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [SM6375_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [SM6375_VDDMX] = &RWMX0_LEVEL_vddmx, + [SM6375_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [SM6375_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [SM6375_VDDGX] = &RWGX0_LEVEL_vddgx, + [SM6375_VDDGX_AO] = &RWGX0_LEVEL_vddgx_ao, + [SM6375_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, + [SM6375_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, }; static const struct rpmpd_desc sm6375_desc = { @@ -455,14 +423,14 @@ static const struct rpmpd_desc sm6375_desc = { }; static struct rpmpd *qcm2290_rpmpds[] = { - [QCM2290_VDDCX] = &sm6115_vddcx, - [QCM2290_VDDCX_AO] = &sm6115_vddcx_ao, - [QCM2290_VDDCX_VFL] = &sm6115_vddcx_vfl, - [QCM2290_VDDMX] = &sm6115_vddmx, - [QCM2290_VDDMX_AO] = &sm6115_vddmx_ao, - [QCM2290_VDDMX_VFL] = &sm6115_vddmx_vfl, - [QCM2290_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, - [QCM2290_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, + [QCM2290_VDDCX] = &RWCX0_LEVEL_vddcx, + [QCM2290_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [QCM2290_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [QCM2290_VDDMX] = &RWMX0_LEVEL_vddmx, + [QCM2290_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [QCM2290_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [QCM2290_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, + [QCM2290_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, }; static const struct rpmpd_desc qcm2290_desc = { From a5d0e2819fd013e3629d3fedcae877777214ed34 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:00 +0100 Subject: [PATCH 24/51] soc: qcom: rpmpd: Bring all definitions to the top Keep all definitions in one place in preparation for a cleanup to make things tidier. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-2-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 111 +++++++++++++++++---------------------- 1 file changed, 49 insertions(+), 62 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index d99a56509e33..7d9e762232ea 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -117,12 +117,58 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); -/* mdm9607 RPM Power Domains */ +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, RWCX, LEVEL, 0); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 2); DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 3); +DEFINE_RPMPD_VFL(vddcx_vfl, RWCX, 0); +DEFINE_RPMPD_VFL(vddcx_vfl, RWSC, 2); +DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 1); +DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 2); +DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 2); DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 3); +DEFINE_RPMPD_CORNER(vddgfx, SMPB, 2); +DEFINE_RPMPD_VFC(vddgfx_vfc, SMPB, 2); + +DEFINE_RPMPD_PAIR(vddgx, vddgx_ao, RWGX, LEVEL, 0); + +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, CORNER, 3); DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, LEVEL, 12); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, RWMX, LEVEL, 0); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 6); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 7); DEFINE_RPMPD_VFL(vddmx_vfl, LDOA, 12); +DEFINE_RPMPD_VFL(vddmx_vfl, RWMX, 0); +DEFINE_RPMPD_VFL(vddmx_vfl, RWSM, 6); + +DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, LEVEL, 1); +DEFINE_RPMPD_VFC(vddmd_vfc, SMPA, 1); + +DEFINE_RPMPD_LEVEL(vdd_lpi_cx, RWLC, 0); +DEFINE_RPMPD_LEVEL(vdd_lpicx, RWLC, 0); +DEFINE_RPMPD_VFL(vdd_lpicx_vfl, RWLC, 0); + +DEFINE_RPMPD_LEVEL(vdd_lpi_mx, RWLM, 0); +DEFINE_RPMPD_LEVEL(vdd_lpimx, RWLM, 0); +DEFINE_RPMPD_VFL(vdd_lpimx_vfl, RWLM, 0); + +DEFINE_RPMPD_CORNER(vddsscx, LDOA, 26); +DEFINE_RPMPD_LEVEL(vdd_ssccx, RWLC, 0); +DEFINE_RPMPD_LEVEL(vdd_ssccx, RWSC, 0); +DEFINE_RPMPD_VFC(vddsscx_vfc, LDOA, 26); +DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWLC, 0); +DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWSC, 0); + +DEFINE_RPMPD_LEVEL(vdd_sscmx, RWLM, 0); +DEFINE_RPMPD_LEVEL(vdd_sscmx, RWSM, 0); +DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWLM, 0); +DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWSM, 0); + +/* mdm9607 RPM Power Domains */ static struct rpmpd *mdm9607_rpmpds[] = { [MDM9607_VDDCX] = &SMPA3_LEVEL_vddcx, [MDM9607_VDDCX_AO] = &SMPA3_LEVEL_vddcx_ao, @@ -139,9 +185,6 @@ static const struct rpmpd_desc mdm9607_desc = { }; /* msm8226 RPM Power Domains */ -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 1); - static struct rpmpd *msm8226_rpmpds[] = { [MSM8226_VDDCX] = &SMPA1_CORNER_vddcx, [MSM8226_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, @@ -155,14 +198,6 @@ static const struct rpmpd_desc msm8226_desc = { }; /* msm8939 RPM Power Domains */ -DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_VFC(vddmd_vfc, SMPA, 1); - -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 2); - -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, CORNER, 3); - static struct rpmpd *msm8939_rpmpds[] = { [MSM8939_VDDMDCX] = &SMPA1_CORNER_vddmd, [MSM8939_VDDMDCX_AO] = &SMPA1_CORNER_vddmd_ao, @@ -196,12 +231,6 @@ static const struct rpmpd_desc msm8916_desc = { }; /* msm8953 RPM Power Domains */ -DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, LEVEL, 1); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 2); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 7); - -DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 2); - static struct rpmpd *msm8953_rpmpds[] = { [MSM8953_VDDMD] = &SMPA1_LEVEL_vddmd, [MSM8953_VDDMD_AO] = &SMPA1_LEVEL_vddmd_ao, @@ -219,11 +248,6 @@ static const struct rpmpd_desc msm8953_desc = { }; /* msm8976 RPM Power Domains */ -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 6); - -DEFINE_RPMPD_VFL(vddcx_vfl, RWSC, 2); -DEFINE_RPMPD_VFL(vddmx_vfl, RWSM, 6); - static struct rpmpd *msm8976_rpmpds[] = { [MSM8976_VDDCX] = &SMPA2_LEVEL_vddcx, [MSM8976_VDDCX_AO] = &SMPA2_LEVEL_vddcx_ao, @@ -240,18 +264,14 @@ static const struct rpmpd_desc msm8976_desc = { }; /* msm8994 RPM Power domains */ -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, CORNER, 2); -/* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */ -DEFINE_RPMPD_CORNER(vddgfx, SMPB, 2); - -DEFINE_RPMPD_VFC(vddgfx_vfc, SMPB, 2); - static struct rpmpd *msm8994_rpmpds[] = { [MSM8994_VDDCX] = &SMPA1_CORNER_vddcx, [MSM8994_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, [MSM8994_VDDCX_VFC] = &SMPA1_vddcx_vfc, [MSM8994_VDDMX] = &SMPA2_CORNER_vddmx, [MSM8994_VDDMX_AO] = &SMPA2_CORNER_vddmx_ao, + + /* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */ [MSM8994_VDDGFX] = &SMPB2_vddgfx_corner, [MSM8994_VDDGFX_VFC] = &SMPB2_vddgfx_vfc, }; @@ -263,10 +283,6 @@ static const struct rpmpd_desc msm8994_desc = { }; /* msm8996 RPM Power domains */ -DEFINE_RPMPD_CORNER(vddsscx, LDOA, 26); - -DEFINE_RPMPD_VFC(vddsscx_vfc, LDOA, 26); - static struct rpmpd *msm8996_rpmpds[] = { [MSM8996_VDDCX] = &SMPA1_CORNER_vddcx, [MSM8996_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, @@ -284,18 +300,6 @@ static const struct rpmpd_desc msm8996_desc = { }; /* msm8998 RPM Power domains */ -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_VFL(vddcx_vfl, RWCX, 0); - -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(vddmx_vfl, RWMX, 0); - -DEFINE_RPMPD_LEVEL(vdd_ssccx, RWSC, 0); -DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWSC, 0); - -DEFINE_RPMPD_LEVEL(vdd_sscmx, RWSM, 0); -DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWSM, 0); - static struct rpmpd *msm8998_rpmpds[] = { [MSM8998_VDDCX] = &RWCX0_LEVEL_vddcx, [MSM8998_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, @@ -316,12 +320,6 @@ static const struct rpmpd_desc msm8998_desc = { }; /* qcs404 RPM Power domains */ -DEFINE_RPMPD_LEVEL(vdd_lpicx, RWLC, 0); -DEFINE_RPMPD_VFL(vdd_lpicx_vfl, RWLC, 0); - -DEFINE_RPMPD_LEVEL(vdd_lpimx, RWLM, 0); -DEFINE_RPMPD_VFL(vdd_lpimx_vfl, RWLM, 0); - static struct rpmpd *qcs404_rpmpds[] = { [QCS404_VDDMX] = &RWMX0_LEVEL_vddmx, [QCS404_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, @@ -339,13 +337,6 @@ static const struct rpmpd_desc qcs404_desc = { }; /* sdm660 RPM Power domains */ - -DEFINE_RPMPD_LEVEL(vdd_ssccx, RWLC, 0); -DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWLC, 0); - -DEFINE_RPMPD_LEVEL(vdd_sscmx, RWLM, 0); -DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWLM, 0); - static struct rpmpd *sdm660_rpmpds[] = { [SDM660_VDDCX] = &RWCX0_LEVEL_vddcx, [SDM660_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, @@ -366,9 +357,6 @@ static const struct rpmpd_desc sdm660_desc = { }; /* sm4250/6115 RPM Power domains */ -DEFINE_RPMPD_LEVEL(vdd_lpi_cx, RWLC, 0); -DEFINE_RPMPD_LEVEL(vdd_lpi_mx, RWLM, 0); - static struct rpmpd *sm6115_rpmpds[] = { [SM6115_VDDCX] = &RWCX0_LEVEL_vddcx, [SM6115_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, @@ -402,7 +390,6 @@ static const struct rpmpd_desc sm6125_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; -DEFINE_RPMPD_PAIR(vddgx, vddgx_ao, RWGX, LEVEL, 0); static struct rpmpd *sm6375_rpmpds[] = { [SM6375_VDDCX] = &RWCX0_LEVEL_vddcx, [SM6375_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, From d280f3d66d9a79b1bd50258ccb3fbb413216c1be Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:01 +0100 Subject: [PATCH 25/51] soc: qcom: rpmpd: Unify Low Power Island definitions Up until now, we had 2 separate entries for VDD_LPI[CM]X and VDD_LPI_[CM]X which both pointed to the same RPM resource. Fix it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-3-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 7d9e762232ea..8ba025c4eca3 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -149,11 +149,9 @@ DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, LEVEL, 1); DEFINE_RPMPD_VFC(vddmd_vfc, SMPA, 1); DEFINE_RPMPD_LEVEL(vdd_lpi_cx, RWLC, 0); -DEFINE_RPMPD_LEVEL(vdd_lpicx, RWLC, 0); DEFINE_RPMPD_VFL(vdd_lpicx_vfl, RWLC, 0); DEFINE_RPMPD_LEVEL(vdd_lpi_mx, RWLM, 0); -DEFINE_RPMPD_LEVEL(vdd_lpimx, RWLM, 0); DEFINE_RPMPD_VFL(vdd_lpimx_vfl, RWLM, 0); DEFINE_RPMPD_CORNER(vddsscx, LDOA, 26); @@ -324,9 +322,9 @@ static struct rpmpd *qcs404_rpmpds[] = { [QCS404_VDDMX] = &RWMX0_LEVEL_vddmx, [QCS404_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, [QCS404_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [QCS404_LPICX] = &RWLC0_vdd_lpicx_lvl, + [QCS404_LPICX] = &RWLC0_vdd_lpi_cx_lvl, [QCS404_LPICX_VFL] = &RWLC0_vdd_lpicx_vfl, - [QCS404_LPIMX] = &RWLM0_vdd_lpimx_lvl, + [QCS404_LPIMX] = &RWLM0_vdd_lpi_mx_lvl, [QCS404_LPIMX_VFL] = &RWLM0_vdd_lpimx_vfl, }; From 1c940cc42aba5b27a259634f4aedb71e5f46dac1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:02 +0100 Subject: [PATCH 26/51] soc: qcom: rpmpd: Remove vdd* from struct names It's rather obvious by the characteristic of these resources that they correspond to some voltage lines governed by RPM. Remove the "vdd" unnecessary prefix from them. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-4-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 296 +++++++++++++++++++-------------------- 1 file changed, 148 insertions(+), 148 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 8ba025c4eca3..8f145663af9a 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -117,63 +117,63 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 2); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 3); -DEFINE_RPMPD_VFL(vddcx_vfl, RWCX, 0); -DEFINE_RPMPD_VFL(vddcx_vfl, RWSC, 2); -DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 1); -DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 2); -DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 2); -DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 3); +DEFINE_RPMPD_PAIR(cx, cx_ao, RWCX, LEVEL, 0); +DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, LEVEL, 2); +DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, LEVEL, 3); +DEFINE_RPMPD_VFL(cx_vfl, RWCX, 0); +DEFINE_RPMPD_VFL(cx_vfl, RWSC, 2); +DEFINE_RPMPD_VFC(cx_vfc, SMPA, 1); +DEFINE_RPMPD_VFC(cx_vfc, SMPA, 2); +DEFINE_RPMPD_VFL(cx_vfl, SMPA, 2); +DEFINE_RPMPD_VFL(cx_vfl, SMPA, 3); -DEFINE_RPMPD_CORNER(vddgfx, SMPB, 2); -DEFINE_RPMPD_VFC(vddgfx_vfc, SMPB, 2); +DEFINE_RPMPD_CORNER(gfx, SMPB, 2); +DEFINE_RPMPD_VFC(gfx_vfc, SMPB, 2); -DEFINE_RPMPD_PAIR(vddgx, vddgx_ao, RWGX, LEVEL, 0); +DEFINE_RPMPD_PAIR(gx, gx_ao, RWGX, LEVEL, 0); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, CORNER, 3); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, LEVEL, 12); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 6); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 7); -DEFINE_RPMPD_VFL(vddmx_vfl, LDOA, 12); -DEFINE_RPMPD_VFL(vddmx_vfl, RWMX, 0); -DEFINE_RPMPD_VFL(vddmx_vfl, RWSM, 6); +DEFINE_RPMPD_PAIR(mx, mx_ao, LDOA, CORNER, 3); +DEFINE_RPMPD_PAIR(mx, mx_ao, LDOA, LEVEL, 12); +DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_PAIR(mx, mx_ao, RWMX, LEVEL, 0); +DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, LEVEL, 6); +DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, LEVEL, 7); +DEFINE_RPMPD_VFL(mx_vfl, LDOA, 12); +DEFINE_RPMPD_VFL(mx_vfl, RWMX, 0); +DEFINE_RPMPD_VFL(mx_vfl, RWSM, 6); -DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, LEVEL, 1); -DEFINE_RPMPD_VFC(vddmd_vfc, SMPA, 1); +DEFINE_RPMPD_PAIR(md, md_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_PAIR(md, md_ao, SMPA, LEVEL, 1); +DEFINE_RPMPD_VFC(md_vfc, SMPA, 1); -DEFINE_RPMPD_LEVEL(vdd_lpi_cx, RWLC, 0); -DEFINE_RPMPD_VFL(vdd_lpicx_vfl, RWLC, 0); +DEFINE_RPMPD_LEVEL(lpi_cx, RWLC, 0); +DEFINE_RPMPD_VFL(lpicx_vfl, RWLC, 0); -DEFINE_RPMPD_LEVEL(vdd_lpi_mx, RWLM, 0); -DEFINE_RPMPD_VFL(vdd_lpimx_vfl, RWLM, 0); +DEFINE_RPMPD_LEVEL(lpi_mx, RWLM, 0); +DEFINE_RPMPD_VFL(lpimx_vfl, RWLM, 0); -DEFINE_RPMPD_CORNER(vddsscx, LDOA, 26); -DEFINE_RPMPD_LEVEL(vdd_ssccx, RWLC, 0); -DEFINE_RPMPD_LEVEL(vdd_ssccx, RWSC, 0); -DEFINE_RPMPD_VFC(vddsscx_vfc, LDOA, 26); -DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWLC, 0); -DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWSC, 0); +DEFINE_RPMPD_CORNER(sscx, LDOA, 26); +DEFINE_RPMPD_LEVEL(ssccx, RWLC, 0); +DEFINE_RPMPD_LEVEL(ssccx, RWSC, 0); +DEFINE_RPMPD_VFC(sscx_vfc, LDOA, 26); +DEFINE_RPMPD_VFL(ssccx_vfl, RWLC, 0); +DEFINE_RPMPD_VFL(ssccx_vfl, RWSC, 0); -DEFINE_RPMPD_LEVEL(vdd_sscmx, RWLM, 0); -DEFINE_RPMPD_LEVEL(vdd_sscmx, RWSM, 0); -DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWLM, 0); -DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWSM, 0); +DEFINE_RPMPD_LEVEL(sscmx, RWLM, 0); +DEFINE_RPMPD_LEVEL(sscmx, RWSM, 0); +DEFINE_RPMPD_VFL(sscmx_vfl, RWLM, 0); +DEFINE_RPMPD_VFL(sscmx_vfl, RWSM, 0); /* mdm9607 RPM Power Domains */ static struct rpmpd *mdm9607_rpmpds[] = { - [MDM9607_VDDCX] = &SMPA3_LEVEL_vddcx, - [MDM9607_VDDCX_AO] = &SMPA3_LEVEL_vddcx_ao, - [MDM9607_VDDCX_VFL] = &SMPA3_vddcx_vfl, - [MDM9607_VDDMX] = &LDOA12_LEVEL_vddmx, - [MDM9607_VDDMX_AO] = &LDOA12_LEVEL_vddmx_ao, - [MDM9607_VDDMX_VFL] = &LDOA12_vddmx_vfl, + [MDM9607_VDDCX] = &SMPA3_LEVEL_cx, + [MDM9607_VDDCX_AO] = &SMPA3_LEVEL_cx_ao, + [MDM9607_VDDCX_VFL] = &SMPA3_cx_vfl, + [MDM9607_VDDMX] = &LDOA12_LEVEL_mx, + [MDM9607_VDDMX_AO] = &LDOA12_LEVEL_mx_ao, + [MDM9607_VDDMX_VFL] = &LDOA12_mx_vfl, }; static const struct rpmpd_desc mdm9607_desc = { @@ -184,9 +184,9 @@ static const struct rpmpd_desc mdm9607_desc = { /* msm8226 RPM Power Domains */ static struct rpmpd *msm8226_rpmpds[] = { - [MSM8226_VDDCX] = &SMPA1_CORNER_vddcx, - [MSM8226_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, - [MSM8226_VDDCX_VFC] = &SMPA1_vddcx_vfc, + [MSM8226_VDDCX] = &SMPA1_CORNER_cx, + [MSM8226_VDDCX_AO] = &SMPA1_CORNER_cx_ao, + [MSM8226_VDDCX_VFC] = &SMPA1_cx_vfc, }; static const struct rpmpd_desc msm8226_desc = { @@ -197,14 +197,14 @@ static const struct rpmpd_desc msm8226_desc = { /* msm8939 RPM Power Domains */ static struct rpmpd *msm8939_rpmpds[] = { - [MSM8939_VDDMDCX] = &SMPA1_CORNER_vddmd, - [MSM8939_VDDMDCX_AO] = &SMPA1_CORNER_vddmd_ao, - [MSM8939_VDDMDCX_VFC] = &SMPA1_vddmd_vfc, - [MSM8939_VDDCX] = &SMPA2_CORNER_vddcx, - [MSM8939_VDDCX_AO] = &SMPA2_CORNER_vddcx_ao, - [MSM8939_VDDCX_VFC] = &SMPA2_vddcx_vfc, - [MSM8939_VDDMX] = &LDOA3_CORNER_vddmx, - [MSM8939_VDDMX_AO] = &LDOA3_CORNER_vddmx_ao, + [MSM8939_VDDMDCX] = &SMPA1_CORNER_md, + [MSM8939_VDDMDCX_AO] = &SMPA1_CORNER_md_ao, + [MSM8939_VDDMDCX_VFC] = &SMPA1_md_vfc, + [MSM8939_VDDCX] = &SMPA2_CORNER_cx, + [MSM8939_VDDCX_AO] = &SMPA2_CORNER_cx_ao, + [MSM8939_VDDCX_VFC] = &SMPA2_cx_vfc, + [MSM8939_VDDMX] = &LDOA3_CORNER_mx, + [MSM8939_VDDMX_AO] = &LDOA3_CORNER_mx_ao, }; static const struct rpmpd_desc msm8939_desc = { @@ -215,11 +215,11 @@ static const struct rpmpd_desc msm8939_desc = { /* msm8916 RPM Power Domains */ static struct rpmpd *msm8916_rpmpds[] = { - [MSM8916_VDDCX] = &SMPA1_CORNER_vddcx, - [MSM8916_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, - [MSM8916_VDDCX_VFC] = &SMPA1_vddcx_vfc, - [MSM8916_VDDMX] = &LDOA3_CORNER_vddmx, - [MSM8916_VDDMX_AO] = &LDOA3_CORNER_vddmx_ao, + [MSM8916_VDDCX] = &SMPA1_CORNER_cx, + [MSM8916_VDDCX_AO] = &SMPA1_CORNER_cx_ao, + [MSM8916_VDDCX_VFC] = &SMPA1_cx_vfc, + [MSM8916_VDDMX] = &LDOA3_CORNER_mx, + [MSM8916_VDDMX_AO] = &LDOA3_CORNER_mx_ao, }; static const struct rpmpd_desc msm8916_desc = { @@ -230,13 +230,13 @@ static const struct rpmpd_desc msm8916_desc = { /* msm8953 RPM Power Domains */ static struct rpmpd *msm8953_rpmpds[] = { - [MSM8953_VDDMD] = &SMPA1_LEVEL_vddmd, - [MSM8953_VDDMD_AO] = &SMPA1_LEVEL_vddmd_ao, - [MSM8953_VDDCX] = &SMPA2_LEVEL_vddcx, - [MSM8953_VDDCX_AO] = &SMPA2_LEVEL_vddcx_ao, - [MSM8953_VDDCX_VFL] = &SMPA2_vddcx_vfl, - [MSM8953_VDDMX] = &SMPA7_LEVEL_vddmx, - [MSM8953_VDDMX_AO] = &SMPA7_LEVEL_vddmx_ao, + [MSM8953_VDDMD] = &SMPA1_LEVEL_md, + [MSM8953_VDDMD_AO] = &SMPA1_LEVEL_md_ao, + [MSM8953_VDDCX] = &SMPA2_LEVEL_cx, + [MSM8953_VDDCX_AO] = &SMPA2_LEVEL_cx_ao, + [MSM8953_VDDCX_VFL] = &SMPA2_cx_vfl, + [MSM8953_VDDMX] = &SMPA7_LEVEL_mx, + [MSM8953_VDDMX_AO] = &SMPA7_LEVEL_mx_ao, }; static const struct rpmpd_desc msm8953_desc = { @@ -247,12 +247,12 @@ static const struct rpmpd_desc msm8953_desc = { /* msm8976 RPM Power Domains */ static struct rpmpd *msm8976_rpmpds[] = { - [MSM8976_VDDCX] = &SMPA2_LEVEL_vddcx, - [MSM8976_VDDCX_AO] = &SMPA2_LEVEL_vddcx_ao, - [MSM8976_VDDCX_VFL] = &RWSC2_vddcx_vfl, - [MSM8976_VDDMX] = &SMPA6_LEVEL_vddmx, - [MSM8976_VDDMX_AO] = &SMPA6_LEVEL_vddmx_ao, - [MSM8976_VDDMX_VFL] = &RWSM6_vddmx_vfl, + [MSM8976_VDDCX] = &SMPA2_LEVEL_cx, + [MSM8976_VDDCX_AO] = &SMPA2_LEVEL_cx_ao, + [MSM8976_VDDCX_VFL] = &RWSC2_cx_vfl, + [MSM8976_VDDMX] = &SMPA6_LEVEL_mx, + [MSM8976_VDDMX_AO] = &SMPA6_LEVEL_mx_ao, + [MSM8976_VDDMX_VFL] = &RWSM6_mx_vfl, }; static const struct rpmpd_desc msm8976_desc = { @@ -263,15 +263,15 @@ static const struct rpmpd_desc msm8976_desc = { /* msm8994 RPM Power domains */ static struct rpmpd *msm8994_rpmpds[] = { - [MSM8994_VDDCX] = &SMPA1_CORNER_vddcx, - [MSM8994_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, - [MSM8994_VDDCX_VFC] = &SMPA1_vddcx_vfc, - [MSM8994_VDDMX] = &SMPA2_CORNER_vddmx, - [MSM8994_VDDMX_AO] = &SMPA2_CORNER_vddmx_ao, + [MSM8994_VDDCX] = &SMPA1_CORNER_cx, + [MSM8994_VDDCX_AO] = &SMPA1_CORNER_cx_ao, + [MSM8994_VDDCX_VFC] = &SMPA1_cx_vfc, + [MSM8994_VDDMX] = &SMPA2_CORNER_mx, + [MSM8994_VDDMX_AO] = &SMPA2_CORNER_mx_ao, /* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */ - [MSM8994_VDDGFX] = &SMPB2_vddgfx_corner, - [MSM8994_VDDGFX_VFC] = &SMPB2_vddgfx_vfc, + [MSM8994_VDDGFX] = &SMPB2_gfx_corner, + [MSM8994_VDDGFX_VFC] = &SMPB2_gfx_vfc, }; static const struct rpmpd_desc msm8994_desc = { @@ -282,13 +282,13 @@ static const struct rpmpd_desc msm8994_desc = { /* msm8996 RPM Power domains */ static struct rpmpd *msm8996_rpmpds[] = { - [MSM8996_VDDCX] = &SMPA1_CORNER_vddcx, - [MSM8996_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, - [MSM8996_VDDCX_VFC] = &SMPA1_vddcx_vfc, - [MSM8996_VDDMX] = &SMPA2_CORNER_vddmx, - [MSM8996_VDDMX_AO] = &SMPA2_CORNER_vddmx_ao, - [MSM8996_VDDSSCX] = &LDOA26_vddsscx_corner, - [MSM8996_VDDSSCX_VFC] = &LDOA26_vddsscx_vfc, + [MSM8996_VDDCX] = &SMPA1_CORNER_cx, + [MSM8996_VDDCX_AO] = &SMPA1_CORNER_cx_ao, + [MSM8996_VDDCX_VFC] = &SMPA1_cx_vfc, + [MSM8996_VDDMX] = &SMPA2_CORNER_mx, + [MSM8996_VDDMX_AO] = &SMPA2_CORNER_mx_ao, + [MSM8996_VDDSSCX] = &LDOA26_sscx_corner, + [MSM8996_VDDSSCX_VFC] = &LDOA26_sscx_vfc, }; static const struct rpmpd_desc msm8996_desc = { @@ -299,16 +299,16 @@ static const struct rpmpd_desc msm8996_desc = { /* msm8998 RPM Power domains */ static struct rpmpd *msm8998_rpmpds[] = { - [MSM8998_VDDCX] = &RWCX0_LEVEL_vddcx, - [MSM8998_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [MSM8998_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [MSM8998_VDDMX] = &RWMX0_LEVEL_vddmx, - [MSM8998_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [MSM8998_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [MSM8998_SSCCX] = &RWSC0_vdd_ssccx_lvl, - [MSM8998_SSCCX_VFL] = &RWSC0_vdd_ssccx_vfl, - [MSM8998_SSCMX] = &RWSM0_vdd_sscmx_lvl, - [MSM8998_SSCMX_VFL] = &RWSM0_vdd_sscmx_vfl, + [MSM8998_VDDCX] = &RWCX0_LEVEL_cx, + [MSM8998_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [MSM8998_VDDCX_VFL] = &RWCX0_cx_vfl, + [MSM8998_VDDMX] = &RWMX0_LEVEL_mx, + [MSM8998_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [MSM8998_VDDMX_VFL] = &RWMX0_mx_vfl, + [MSM8998_SSCCX] = &RWSC0_ssccx_lvl, + [MSM8998_SSCCX_VFL] = &RWSC0_ssccx_vfl, + [MSM8998_SSCMX] = &RWSM0_sscmx_lvl, + [MSM8998_SSCMX_VFL] = &RWSM0_sscmx_vfl, }; static const struct rpmpd_desc msm8998_desc = { @@ -319,13 +319,13 @@ static const struct rpmpd_desc msm8998_desc = { /* qcs404 RPM Power domains */ static struct rpmpd *qcs404_rpmpds[] = { - [QCS404_VDDMX] = &RWMX0_LEVEL_vddmx, - [QCS404_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [QCS404_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [QCS404_LPICX] = &RWLC0_vdd_lpi_cx_lvl, - [QCS404_LPICX_VFL] = &RWLC0_vdd_lpicx_vfl, - [QCS404_LPIMX] = &RWLM0_vdd_lpi_mx_lvl, - [QCS404_LPIMX_VFL] = &RWLM0_vdd_lpimx_vfl, + [QCS404_VDDMX] = &RWMX0_LEVEL_mx, + [QCS404_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [QCS404_VDDMX_VFL] = &RWMX0_mx_vfl, + [QCS404_LPICX] = &RWLC0_lpi_cx_lvl, + [QCS404_LPICX_VFL] = &RWLC0_lpicx_vfl, + [QCS404_LPIMX] = &RWLM0_lpi_mx_lvl, + [QCS404_LPIMX_VFL] = &RWLM0_lpimx_vfl, }; static const struct rpmpd_desc qcs404_desc = { @@ -336,16 +336,16 @@ static const struct rpmpd_desc qcs404_desc = { /* sdm660 RPM Power domains */ static struct rpmpd *sdm660_rpmpds[] = { - [SDM660_VDDCX] = &RWCX0_LEVEL_vddcx, - [SDM660_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [SDM660_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [SDM660_VDDMX] = &RWMX0_LEVEL_vddmx, - [SDM660_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [SDM660_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [SDM660_SSCCX] = &RWLC0_vdd_ssccx_lvl, - [SDM660_SSCCX_VFL] = &RWLC0_vdd_ssccx_vfl, - [SDM660_SSCMX] = &RWLM0_vdd_sscmx_lvl, - [SDM660_SSCMX_VFL] = &RWLM0_vdd_sscmx_vfl, + [SDM660_VDDCX] = &RWCX0_LEVEL_cx, + [SDM660_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [SDM660_VDDCX_VFL] = &RWCX0_cx_vfl, + [SDM660_VDDMX] = &RWMX0_LEVEL_mx, + [SDM660_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [SDM660_VDDMX_VFL] = &RWMX0_mx_vfl, + [SDM660_SSCCX] = &RWLC0_ssccx_lvl, + [SDM660_SSCCX_VFL] = &RWLC0_ssccx_vfl, + [SDM660_SSCMX] = &RWLM0_sscmx_lvl, + [SDM660_SSCMX_VFL] = &RWLM0_sscmx_vfl, }; static const struct rpmpd_desc sdm660_desc = { @@ -356,14 +356,14 @@ static const struct rpmpd_desc sdm660_desc = { /* sm4250/6115 RPM Power domains */ static struct rpmpd *sm6115_rpmpds[] = { - [SM6115_VDDCX] = &RWCX0_LEVEL_vddcx, - [SM6115_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [SM6115_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [SM6115_VDDMX] = &RWMX0_LEVEL_vddmx, - [SM6115_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [SM6115_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [SM6115_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, - [SM6115_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, + [SM6115_VDDCX] = &RWCX0_LEVEL_cx, + [SM6115_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [SM6115_VDDCX_VFL] = &RWCX0_cx_vfl, + [SM6115_VDDMX] = &RWMX0_LEVEL_mx, + [SM6115_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [SM6115_VDDMX_VFL] = &RWMX0_mx_vfl, + [SM6115_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, + [SM6115_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, }; static const struct rpmpd_desc sm6115_desc = { @@ -374,12 +374,12 @@ static const struct rpmpd_desc sm6115_desc = { /* sm6125 RPM Power domains */ static struct rpmpd *sm6125_rpmpds[] = { - [SM6125_VDDCX] = &RWCX0_LEVEL_vddcx, - [SM6125_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [SM6125_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [SM6125_VDDMX] = &RWMX0_LEVEL_vddmx, - [SM6125_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [SM6125_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [SM6125_VDDCX] = &RWCX0_LEVEL_cx, + [SM6125_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [SM6125_VDDCX_VFL] = &RWCX0_cx_vfl, + [SM6125_VDDMX] = &RWMX0_LEVEL_mx, + [SM6125_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [SM6125_VDDMX_VFL] = &RWMX0_mx_vfl, }; static const struct rpmpd_desc sm6125_desc = { @@ -389,16 +389,16 @@ static const struct rpmpd_desc sm6125_desc = { }; static struct rpmpd *sm6375_rpmpds[] = { - [SM6375_VDDCX] = &RWCX0_LEVEL_vddcx, - [SM6375_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [SM6375_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [SM6375_VDDMX] = &RWMX0_LEVEL_vddmx, - [SM6375_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [SM6375_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [SM6375_VDDGX] = &RWGX0_LEVEL_vddgx, - [SM6375_VDDGX_AO] = &RWGX0_LEVEL_vddgx_ao, - [SM6375_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, - [SM6375_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, + [SM6375_VDDCX] = &RWCX0_LEVEL_cx, + [SM6375_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [SM6375_VDDCX_VFL] = &RWCX0_cx_vfl, + [SM6375_VDDMX] = &RWMX0_LEVEL_mx, + [SM6375_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [SM6375_VDDMX_VFL] = &RWMX0_mx_vfl, + [SM6375_VDDGX] = &RWGX0_LEVEL_gx, + [SM6375_VDDGX_AO] = &RWGX0_LEVEL_gx_ao, + [SM6375_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, + [SM6375_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, }; static const struct rpmpd_desc sm6375_desc = { @@ -408,14 +408,14 @@ static const struct rpmpd_desc sm6375_desc = { }; static struct rpmpd *qcm2290_rpmpds[] = { - [QCM2290_VDDCX] = &RWCX0_LEVEL_vddcx, - [QCM2290_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [QCM2290_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [QCM2290_VDDMX] = &RWMX0_LEVEL_vddmx, - [QCM2290_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [QCM2290_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [QCM2290_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, - [QCM2290_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, + [QCM2290_VDDCX] = &RWCX0_LEVEL_cx, + [QCM2290_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [QCM2290_VDDCX_VFL] = &RWCX0_cx_vfl, + [QCM2290_VDDMX] = &RWMX0_LEVEL_mx, + [QCM2290_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [QCM2290_VDDMX_VFL] = &RWMX0_mx_vfl, + [QCM2290_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, + [QCM2290_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, }; static const struct rpmpd_desc qcm2290_desc = { From 91c0bcef25f985fd974b6f1ba3d3d7383ac032d2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:03 +0100 Subject: [PATCH 27/51] soc: qcom: rpmpd: Expand struct definition macros Expand the struct definition macros to make things easier to see and maintain. Now that the macros are unnecessary, remove them. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-5-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 523 ++++++++++++++++++++++++++++++++------- 1 file changed, 433 insertions(+), 90 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 8f145663af9a..df4e0d8a2aa9 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -40,56 +40,6 @@ #define MAX_CORNER_RPMPD_STATE 6 -#define DEFINE_RPMPD_PAIR(_name, _active, r_type, r_key, r_id) \ - static struct rpmpd r_type##r_id##_##r_key##_##_active; \ - static struct rpmpd r_type##r_id##_##r_key##_##_name = { \ - .pd = { .name = #_name, }, \ - .peer = &r_type##r_id##_##r_key##_##_active, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_##r_key, \ - }; \ - static struct rpmpd r_type##r_id##_##r_key##_##_active = { \ - .pd = { .name = #_active, }, \ - .peer = &r_type##r_id##_##r_key##_##_name, \ - .active_only = true, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_##r_key, \ - } - -#define DEFINE_RPMPD_CORNER(_name, r_type, r_id) \ - static struct rpmpd r_type##r_id##_##_name##_corner = { \ - .pd = { .name = #_name, }, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_CORNER, \ - } - -#define DEFINE_RPMPD_LEVEL(_name, r_type, r_id) \ - static struct rpmpd r_type##r_id##_##_name##_lvl = { \ - .pd = { .name = #_name, }, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_LEVEL, \ - } - -#define DEFINE_RPMPD_VFC(_name, r_type, r_id) \ - static struct rpmpd r_type##r_id##_##_name = { \ - .pd = { .name = #_name, }, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_FLOOR_CORNER, \ - } - -#define DEFINE_RPMPD_VFL(_name, r_type, r_id) \ - static struct rpmpd r_type##r_id##_##_name = { \ - .pd = { .name = #_name, }, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_FLOOR_LEVEL, \ - } - struct rpmpd_req { __le32 key; __le32 nbytes; @@ -117,54 +67,447 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); -DEFINE_RPMPD_PAIR(cx, cx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, LEVEL, 2); -DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, LEVEL, 3); -DEFINE_RPMPD_VFL(cx_vfl, RWCX, 0); -DEFINE_RPMPD_VFL(cx_vfl, RWSC, 2); -DEFINE_RPMPD_VFC(cx_vfc, SMPA, 1); -DEFINE_RPMPD_VFC(cx_vfc, SMPA, 2); -DEFINE_RPMPD_VFL(cx_vfl, SMPA, 2); -DEFINE_RPMPD_VFL(cx_vfl, SMPA, 3); +/* CX */ +static struct rpmpd RWCX0_LEVEL_cx_ao; +static struct rpmpd RWCX0_LEVEL_cx = { + .pd = { .name = "cx", }, + .peer = &RWCX0_LEVEL_cx_ao, + .res_type = RPMPD_RWCX, + .res_id = 0, + .key = KEY_LEVEL, +}; -DEFINE_RPMPD_CORNER(gfx, SMPB, 2); -DEFINE_RPMPD_VFC(gfx_vfc, SMPB, 2); +static struct rpmpd RWCX0_LEVEL_cx_ao = { + .pd = { .name = "cx_ao", }, + .peer = &RWCX0_LEVEL_cx, + .active_only = true, + .res_type = RPMPD_RWCX, + .res_id = 0, + .key = KEY_LEVEL, +}; -DEFINE_RPMPD_PAIR(gx, gx_ao, RWGX, LEVEL, 0); +static struct rpmpd SMPA1_CORNER_cx_ao; +static struct rpmpd SMPA1_CORNER_cx = { + .pd = { .name = "cx", }, + .peer = &SMPA1_CORNER_cx_ao, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_CORNER, +}; -DEFINE_RPMPD_PAIR(mx, mx_ao, LDOA, CORNER, 3); -DEFINE_RPMPD_PAIR(mx, mx_ao, LDOA, LEVEL, 12); -DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_PAIR(mx, mx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, LEVEL, 6); -DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, LEVEL, 7); -DEFINE_RPMPD_VFL(mx_vfl, LDOA, 12); -DEFINE_RPMPD_VFL(mx_vfl, RWMX, 0); -DEFINE_RPMPD_VFL(mx_vfl, RWSM, 6); +static struct rpmpd SMPA1_CORNER_cx_ao = { + .pd = { .name = "cx_ao", }, + .peer = &SMPA1_CORNER_cx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_CORNER, +}; -DEFINE_RPMPD_PAIR(md, md_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(md, md_ao, SMPA, LEVEL, 1); -DEFINE_RPMPD_VFC(md_vfc, SMPA, 1); +static struct rpmpd SMPA2_CORNER_cx_ao; +static struct rpmpd SMPA2_CORNER_cx = { + .pd = { .name = "cx", }, + .peer = &SMPA2_CORNER_cx_ao, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_CORNER, +}; -DEFINE_RPMPD_LEVEL(lpi_cx, RWLC, 0); -DEFINE_RPMPD_VFL(lpicx_vfl, RWLC, 0); +static struct rpmpd SMPA2_CORNER_cx_ao = { + .pd = { .name = "cx_ao", }, + .peer = &SMPA2_CORNER_cx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_CORNER, +}; -DEFINE_RPMPD_LEVEL(lpi_mx, RWLM, 0); -DEFINE_RPMPD_VFL(lpimx_vfl, RWLM, 0); +static struct rpmpd SMPA2_LEVEL_cx_ao; +static struct rpmpd SMPA2_LEVEL_cx = { + .pd = { .name = "cx", }, + .peer = &SMPA2_LEVEL_cx_ao, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_LEVEL, +}; -DEFINE_RPMPD_CORNER(sscx, LDOA, 26); -DEFINE_RPMPD_LEVEL(ssccx, RWLC, 0); -DEFINE_RPMPD_LEVEL(ssccx, RWSC, 0); -DEFINE_RPMPD_VFC(sscx_vfc, LDOA, 26); -DEFINE_RPMPD_VFL(ssccx_vfl, RWLC, 0); -DEFINE_RPMPD_VFL(ssccx_vfl, RWSC, 0); +static struct rpmpd SMPA2_LEVEL_cx_ao = { + .pd = { .name = "cx_ao", }, + .peer = &SMPA2_LEVEL_cx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_LEVEL, +}; -DEFINE_RPMPD_LEVEL(sscmx, RWLM, 0); -DEFINE_RPMPD_LEVEL(sscmx, RWSM, 0); -DEFINE_RPMPD_VFL(sscmx_vfl, RWLM, 0); -DEFINE_RPMPD_VFL(sscmx_vfl, RWSM, 0); +static struct rpmpd SMPA3_LEVEL_cx_ao; +static struct rpmpd SMPA3_LEVEL_cx = { + .pd = { .name = "cx", }, + .peer = &SMPA3_LEVEL_cx_ao, + .res_type = RPMPD_SMPA, + .res_id = 3, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA3_LEVEL_cx_ao = { + .pd = { .name = "cx_ao", }, + .peer = &SMPA3_LEVEL_cx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 3, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWCX0_cx_vfl = { + .pd = { .name = "cx_vfl", }, + .res_type = RPMPD_RWCX, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd RWSC2_cx_vfl = { + .pd = { .name = "cx_vfl", }, + .res_type = RPMPD_RWSC, + .res_id = 2, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd SMPA1_cx_vfc = { + .pd = { .name = "cx_vfc", }, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_FLOOR_CORNER, +}; + +static struct rpmpd SMPA2_cx_vfc = { + .pd = { .name = "cx_vfc", }, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_FLOOR_CORNER, +}; + +static struct rpmpd SMPA2_cx_vfl = { + .pd = { .name = "cx_vfl", }, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd SMPA3_cx_vfl = { + .pd = { .name = "cx_vfl", }, + .res_type = RPMPD_SMPA, + .res_id = 3, + .key = KEY_FLOOR_LEVEL, +}; + +/* G(F)X */ +static struct rpmpd SMPB2_gfx_corner = { + .pd = { .name = "gfx", }, + .res_type = RPMPD_SMPB, + .res_id = 2, + .key = KEY_CORNER, +}; + +static struct rpmpd SMPB2_gfx_vfc = { + .pd = { .name = "gfx_vfc", }, + .res_type = RPMPD_SMPB, + .res_id = 2, + .key = KEY_FLOOR_CORNER, +}; + +static struct rpmpd RWGX0_LEVEL_gx_ao; +static struct rpmpd RWGX0_LEVEL_gx = { + .pd = { .name = "gx", }, + .peer = &RWGX0_LEVEL_gx_ao, + .res_type = RPMPD_RWGX, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWGX0_LEVEL_gx_ao = { + .pd = { .name = "gx_ao", }, + .peer = &RWGX0_LEVEL_gx, + .active_only = true, + .res_type = RPMPD_RWGX, + .res_id = 0, + .key = KEY_LEVEL, +}; + +/* MX */ +static struct rpmpd LDOA3_CORNER_mx_ao; +static struct rpmpd LDOA3_CORNER_mx = { + .pd = { .name = "mx", }, + .peer = &LDOA3_CORNER_mx_ao, + .res_type = RPMPD_LDOA, + .res_id = 3, + .key = KEY_CORNER, +}; + +static struct rpmpd LDOA3_CORNER_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &LDOA3_CORNER_mx, + .active_only = true, + .res_type = RPMPD_LDOA, + .res_id = 3, + .key = KEY_CORNER, +}; + +static struct rpmpd LDOA12_LEVEL_mx_ao; +static struct rpmpd LDOA12_LEVEL_mx = { + .pd = { .name = "mx", }, + .peer = &LDOA12_LEVEL_mx_ao, + .res_type = RPMPD_LDOA, + .res_id = 12, + .key = KEY_LEVEL, +}; + +static struct rpmpd LDOA12_LEVEL_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &LDOA12_LEVEL_mx, + .active_only = true, + .res_type = RPMPD_LDOA, + .res_id = 12, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA2_CORNER_mx_ao; +static struct rpmpd SMPA2_CORNER_mx = { + .pd = { .name = "mx", }, + .peer = &SMPA2_CORNER_mx_ao, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_CORNER, +}; + +static struct rpmpd SMPA2_CORNER_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &SMPA2_CORNER_mx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_CORNER, +}; + +static struct rpmpd RWMX0_LEVEL_mx_ao; +static struct rpmpd RWMX0_LEVEL_mx = { + .pd = { .name = "mx", }, + .peer = &RWMX0_LEVEL_mx_ao, + .res_type = RPMPD_RWMX, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWMX0_LEVEL_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &RWMX0_LEVEL_mx, + .active_only = true, + .res_type = RPMPD_RWMX, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA6_LEVEL_mx_ao; +static struct rpmpd SMPA6_LEVEL_mx = { + .pd = { .name = "mx", }, + .peer = &SMPA6_LEVEL_mx_ao, + .res_type = RPMPD_SMPA, + .res_id = 6, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA6_LEVEL_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &SMPA6_LEVEL_mx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 6, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA7_LEVEL_mx_ao; +static struct rpmpd SMPA7_LEVEL_mx = { + .pd = { .name = "mx", }, + .peer = &SMPA7_LEVEL_mx_ao, + .res_type = RPMPD_SMPA, + .res_id = 7, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA7_LEVEL_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &SMPA7_LEVEL_mx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 7, + .key = KEY_LEVEL, +}; + +static struct rpmpd LDOA12_mx_vfl = { + .pd = { .name = "mx_vfl", }, + .res_type = RPMPD_LDOA, + .res_id = 12, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd RWMX0_mx_vfl = { + .pd = { .name = "mx_vfl", }, + .res_type = RPMPD_RWMX, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd RWSM6_mx_vfl = { + .pd = { .name = "mx_vfl", }, + .res_type = RPMPD_RWSM, + .res_id = 6, + .key = KEY_FLOOR_LEVEL, +}; + +/* MD */ +static struct rpmpd SMPA1_CORNER_md_ao; +static struct rpmpd SMPA1_CORNER_md = { + .pd = { .name = "md", }, + .peer = &SMPA1_CORNER_md_ao, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_CORNER, +}; + +static struct rpmpd SMPA1_CORNER_md_ao = { + .pd = { .name = "md_ao", }, + .peer = &SMPA1_CORNER_md, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_CORNER, +}; + +static struct rpmpd SMPA1_LEVEL_md_ao; +static struct rpmpd SMPA1_LEVEL_md = { + .pd = { .name = "md", }, + .peer = &SMPA1_LEVEL_md_ao, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA1_LEVEL_md_ao = { + .pd = { .name = "md_ao", }, + .peer = &SMPA1_LEVEL_md, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA1_md_vfc = { + .pd = { .name = "md_vfc", }, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_FLOOR_CORNER, +}; + +/* LPI_CX */ +static struct rpmpd RWLC0_lpi_cx_lvl = { + .pd = { .name = "lpi_cx", }, + .res_type = RPMPD_RWLC, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWLC0_lpicx_vfl = { + .pd = { .name = "lpicx_vfl", }, + .res_type = RPMPD_RWLC, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +/* LPI_MX */ +static struct rpmpd RWLM0_lpi_mx_lvl = { + .pd = { .name = "lpi_mx", }, + .res_type = RPMPD_RWLM, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWLM0_lpimx_vfl = { + .pd = { .name = "lpimx_vfl", }, + .res_type = RPMPD_RWLM, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +/* SSC_CX */ +static struct rpmpd LDOA26_sscx_corner = { + .pd = { .name = "sscx", }, + .res_type = RPMPD_LDOA, + .res_id = 26, + .key = KEY_CORNER, +}; + +static struct rpmpd RWLC0_ssccx_lvl = { + .pd = { .name = "ssccx", }, + .res_type = RPMPD_RWLC, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWSC0_ssccx_lvl = { + .pd = { .name = "ssccx", }, + .res_type = RPMPD_RWSC, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd LDOA26_sscx_vfc = { + .pd = { .name = "sscx_vfc", }, + .res_type = RPMPD_LDOA, + .res_id = 26, + .key = KEY_FLOOR_CORNER, +}; + +static struct rpmpd RWLC0_ssccx_vfl = { + .pd = { .name = "ssccx_vfl", }, + .res_type = RPMPD_RWLC, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd RWSC0_ssccx_vfl = { + .pd = { .name = "ssccx_vfl", }, + .res_type = RPMPD_RWSC, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +/* SSC_MX */ +static struct rpmpd RWLM0_sscmx_lvl = { + .pd = { .name = "sscmx", }, + .res_type = RPMPD_RWLM, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWSM0_sscmx_lvl = { + .pd = { .name = "sscmx", }, + .res_type = RPMPD_RWSM, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWLM0_sscmx_vfl = { + .pd = { .name = "sscmx_vfl", }, + .res_type = RPMPD_RWLM, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd RWSM0_sscmx_vfl = { + .pd = { .name = "sscmx_vfl", }, + .res_type = RPMPD_RWSM, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; /* mdm9607 RPM Power Domains */ static struct rpmpd *mdm9607_rpmpds[] = { From 07df05025eb4cb65c1549d392f988aa5eeb9e758 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:04 +0100 Subject: [PATCH 28/51] soc: qcom: rpmpd: Improve the naming Now that we aren't bound by the preprocessor macros, improve the naming to be a bit less preprocessor-y and touch up some rpmpd.pd.name fields while at it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-6-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 432 +++++++++++++++++++-------------------- 1 file changed, 216 insertions(+), 216 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index df4e0d8a2aa9..695b2fc56f40 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -68,132 +68,132 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); /* CX */ -static struct rpmpd RWCX0_LEVEL_cx_ao; -static struct rpmpd RWCX0_LEVEL_cx = { +static struct rpmpd cx_rwcx0_lvl_ao; +static struct rpmpd cx_rwcx0_lvl = { .pd = { .name = "cx", }, - .peer = &RWCX0_LEVEL_cx_ao, + .peer = &cx_rwcx0_lvl_ao, .res_type = RPMPD_RWCX, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWCX0_LEVEL_cx_ao = { +static struct rpmpd cx_rwcx0_lvl_ao = { .pd = { .name = "cx_ao", }, - .peer = &RWCX0_LEVEL_cx, + .peer = &cx_rwcx0_lvl, .active_only = true, .res_type = RPMPD_RWCX, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd SMPA1_CORNER_cx_ao; -static struct rpmpd SMPA1_CORNER_cx = { +static struct rpmpd cx_s1a_corner_ao; +static struct rpmpd cx_s1a_corner = { .pd = { .name = "cx", }, - .peer = &SMPA1_CORNER_cx_ao, + .peer = &cx_s1a_corner_ao, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_CORNER, }; -static struct rpmpd SMPA1_CORNER_cx_ao = { +static struct rpmpd cx_s1a_corner_ao = { .pd = { .name = "cx_ao", }, - .peer = &SMPA1_CORNER_cx, + .peer = &cx_s1a_corner, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_CORNER, }; -static struct rpmpd SMPA2_CORNER_cx_ao; -static struct rpmpd SMPA2_CORNER_cx = { +static struct rpmpd cx_s2a_corner_ao; +static struct rpmpd cx_s2a_corner = { .pd = { .name = "cx", }, - .peer = &SMPA2_CORNER_cx_ao, + .peer = &cx_s2a_corner_ao, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_CORNER, }; -static struct rpmpd SMPA2_CORNER_cx_ao = { +static struct rpmpd cx_s2a_corner_ao = { .pd = { .name = "cx_ao", }, - .peer = &SMPA2_CORNER_cx, + .peer = &cx_s2a_corner, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_CORNER, }; -static struct rpmpd SMPA2_LEVEL_cx_ao; -static struct rpmpd SMPA2_LEVEL_cx = { +static struct rpmpd cx_s2a_lvl_ao; +static struct rpmpd cx_s2a_lvl = { .pd = { .name = "cx", }, - .peer = &SMPA2_LEVEL_cx_ao, + .peer = &cx_s2a_lvl_ao, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_LEVEL, }; -static struct rpmpd SMPA2_LEVEL_cx_ao = { +static struct rpmpd cx_s2a_lvl_ao = { .pd = { .name = "cx_ao", }, - .peer = &SMPA2_LEVEL_cx, + .peer = &cx_s2a_lvl, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_LEVEL, }; -static struct rpmpd SMPA3_LEVEL_cx_ao; -static struct rpmpd SMPA3_LEVEL_cx = { +static struct rpmpd cx_s3a_lvl_ao; +static struct rpmpd cx_s3a_lvl = { .pd = { .name = "cx", }, - .peer = &SMPA3_LEVEL_cx_ao, + .peer = &cx_s3a_lvl_ao, .res_type = RPMPD_SMPA, .res_id = 3, .key = KEY_LEVEL, }; -static struct rpmpd SMPA3_LEVEL_cx_ao = { +static struct rpmpd cx_s3a_lvl_ao = { .pd = { .name = "cx_ao", }, - .peer = &SMPA3_LEVEL_cx, + .peer = &cx_s3a_lvl, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 3, .key = KEY_LEVEL, }; -static struct rpmpd RWCX0_cx_vfl = { +static struct rpmpd cx_rwcx0_vfl = { .pd = { .name = "cx_vfl", }, .res_type = RPMPD_RWCX, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd RWSC2_cx_vfl = { +static struct rpmpd cx_rwsc2_vfl = { .pd = { .name = "cx_vfl", }, .res_type = RPMPD_RWSC, .res_id = 2, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd SMPA1_cx_vfc = { +static struct rpmpd cx_s1a_vfc = { .pd = { .name = "cx_vfc", }, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_FLOOR_CORNER, }; -static struct rpmpd SMPA2_cx_vfc = { +static struct rpmpd cx_s2a_vfc = { .pd = { .name = "cx_vfc", }, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_FLOOR_CORNER, }; -static struct rpmpd SMPA2_cx_vfl = { +static struct rpmpd cx_s2a_vfl = { .pd = { .name = "cx_vfl", }, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd SMPA3_cx_vfl = { +static struct rpmpd cx_s3a_vfl = { .pd = { .name = "cx_vfl", }, .res_type = RPMPD_SMPA, .res_id = 3, @@ -201,32 +201,32 @@ static struct rpmpd SMPA3_cx_vfl = { }; /* G(F)X */ -static struct rpmpd SMPB2_gfx_corner = { +static struct rpmpd gfx_s2b_corner = { .pd = { .name = "gfx", }, .res_type = RPMPD_SMPB, .res_id = 2, .key = KEY_CORNER, }; -static struct rpmpd SMPB2_gfx_vfc = { +static struct rpmpd gfx_s2b_vfc = { .pd = { .name = "gfx_vfc", }, .res_type = RPMPD_SMPB, .res_id = 2, .key = KEY_FLOOR_CORNER, }; -static struct rpmpd RWGX0_LEVEL_gx_ao; -static struct rpmpd RWGX0_LEVEL_gx = { +static struct rpmpd gx_rwgx0_lvl_ao; +static struct rpmpd gx_rwgx0_lvl = { .pd = { .name = "gx", }, - .peer = &RWGX0_LEVEL_gx_ao, + .peer = &gx_rwgx0_lvl_ao, .res_type = RPMPD_RWGX, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWGX0_LEVEL_gx_ao = { +static struct rpmpd gx_rwgx0_lvl_ao = { .pd = { .name = "gx_ao", }, - .peer = &RWGX0_LEVEL_gx, + .peer = &gx_rwgx0_lvl, .active_only = true, .res_type = RPMPD_RWGX, .res_id = 0, @@ -234,129 +234,129 @@ static struct rpmpd RWGX0_LEVEL_gx_ao = { }; /* MX */ -static struct rpmpd LDOA3_CORNER_mx_ao; -static struct rpmpd LDOA3_CORNER_mx = { +static struct rpmpd mx_l3a_corner_ao; +static struct rpmpd mx_l3a_corner = { .pd = { .name = "mx", }, - .peer = &LDOA3_CORNER_mx_ao, + .peer = &mx_l3a_corner_ao, .res_type = RPMPD_LDOA, .res_id = 3, .key = KEY_CORNER, }; -static struct rpmpd LDOA3_CORNER_mx_ao = { +static struct rpmpd mx_l3a_corner_ao = { .pd = { .name = "mx_ao", }, - .peer = &LDOA3_CORNER_mx, + .peer = &mx_l3a_corner, .active_only = true, .res_type = RPMPD_LDOA, .res_id = 3, .key = KEY_CORNER, }; -static struct rpmpd LDOA12_LEVEL_mx_ao; -static struct rpmpd LDOA12_LEVEL_mx = { +static struct rpmpd mx_l12a_lvl_ao; +static struct rpmpd mx_l12a_lvl = { .pd = { .name = "mx", }, - .peer = &LDOA12_LEVEL_mx_ao, + .peer = &mx_l12a_lvl_ao, .res_type = RPMPD_LDOA, .res_id = 12, .key = KEY_LEVEL, }; -static struct rpmpd LDOA12_LEVEL_mx_ao = { +static struct rpmpd mx_l12a_lvl_ao = { .pd = { .name = "mx_ao", }, - .peer = &LDOA12_LEVEL_mx, + .peer = &mx_l12a_lvl, .active_only = true, .res_type = RPMPD_LDOA, .res_id = 12, .key = KEY_LEVEL, }; -static struct rpmpd SMPA2_CORNER_mx_ao; -static struct rpmpd SMPA2_CORNER_mx = { +static struct rpmpd mx_s2a_corner_ao; +static struct rpmpd mx_s2a_corner = { .pd = { .name = "mx", }, - .peer = &SMPA2_CORNER_mx_ao, + .peer = &mx_s2a_corner_ao, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_CORNER, }; -static struct rpmpd SMPA2_CORNER_mx_ao = { +static struct rpmpd mx_s2a_corner_ao = { .pd = { .name = "mx_ao", }, - .peer = &SMPA2_CORNER_mx, + .peer = &mx_s2a_corner, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_CORNER, }; -static struct rpmpd RWMX0_LEVEL_mx_ao; -static struct rpmpd RWMX0_LEVEL_mx = { +static struct rpmpd mx_rwmx0_lvl_ao; +static struct rpmpd mx_rwmx0_lvl = { .pd = { .name = "mx", }, - .peer = &RWMX0_LEVEL_mx_ao, + .peer = &mx_rwmx0_lvl_ao, .res_type = RPMPD_RWMX, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWMX0_LEVEL_mx_ao = { +static struct rpmpd mx_rwmx0_lvl_ao = { .pd = { .name = "mx_ao", }, - .peer = &RWMX0_LEVEL_mx, + .peer = &mx_rwmx0_lvl, .active_only = true, .res_type = RPMPD_RWMX, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd SMPA6_LEVEL_mx_ao; -static struct rpmpd SMPA6_LEVEL_mx = { +static struct rpmpd mx_s6a_lvl_ao; +static struct rpmpd mx_s6a_lvl = { .pd = { .name = "mx", }, - .peer = &SMPA6_LEVEL_mx_ao, + .peer = &mx_s6a_lvl_ao, .res_type = RPMPD_SMPA, .res_id = 6, .key = KEY_LEVEL, }; -static struct rpmpd SMPA6_LEVEL_mx_ao = { +static struct rpmpd mx_s6a_lvl_ao = { .pd = { .name = "mx_ao", }, - .peer = &SMPA6_LEVEL_mx, + .peer = &mx_s6a_lvl, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 6, .key = KEY_LEVEL, }; -static struct rpmpd SMPA7_LEVEL_mx_ao; -static struct rpmpd SMPA7_LEVEL_mx = { +static struct rpmpd mx_s7a_lvl_ao; +static struct rpmpd mx_s7a_lvl = { .pd = { .name = "mx", }, - .peer = &SMPA7_LEVEL_mx_ao, + .peer = &mx_s7a_lvl_ao, .res_type = RPMPD_SMPA, .res_id = 7, .key = KEY_LEVEL, }; -static struct rpmpd SMPA7_LEVEL_mx_ao = { +static struct rpmpd mx_s7a_lvl_ao = { .pd = { .name = "mx_ao", }, - .peer = &SMPA7_LEVEL_mx, + .peer = &mx_s7a_lvl, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 7, .key = KEY_LEVEL, }; -static struct rpmpd LDOA12_mx_vfl = { +static struct rpmpd mx_l12a_vfl = { .pd = { .name = "mx_vfl", }, .res_type = RPMPD_LDOA, .res_id = 12, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd RWMX0_mx_vfl = { +static struct rpmpd mx_rwmx0_vfl = { .pd = { .name = "mx_vfl", }, .res_type = RPMPD_RWMX, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd RWSM6_mx_vfl = { +static struct rpmpd mx_rwsm6_vfl = { .pd = { .name = "mx_vfl", }, .res_type = RPMPD_RWSM, .res_id = 6, @@ -364,43 +364,43 @@ static struct rpmpd RWSM6_mx_vfl = { }; /* MD */ -static struct rpmpd SMPA1_CORNER_md_ao; -static struct rpmpd SMPA1_CORNER_md = { +static struct rpmpd md_s1a_corner_ao; +static struct rpmpd md_s1a_corner = { .pd = { .name = "md", }, - .peer = &SMPA1_CORNER_md_ao, + .peer = &md_s1a_corner_ao, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_CORNER, }; -static struct rpmpd SMPA1_CORNER_md_ao = { +static struct rpmpd md_s1a_corner_ao = { .pd = { .name = "md_ao", }, - .peer = &SMPA1_CORNER_md, + .peer = &md_s1a_corner, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_CORNER, }; -static struct rpmpd SMPA1_LEVEL_md_ao; -static struct rpmpd SMPA1_LEVEL_md = { +static struct rpmpd md_s1a_lvl_ao; +static struct rpmpd md_s1a_lvl = { .pd = { .name = "md", }, - .peer = &SMPA1_LEVEL_md_ao, + .peer = &md_s1a_lvl_ao, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_LEVEL, }; -static struct rpmpd SMPA1_LEVEL_md_ao = { +static struct rpmpd md_s1a_lvl_ao = { .pd = { .name = "md_ao", }, - .peer = &SMPA1_LEVEL_md, + .peer = &md_s1a_lvl, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_LEVEL, }; -static struct rpmpd SMPA1_md_vfc = { +static struct rpmpd md_s1a_vfc = { .pd = { .name = "md_vfc", }, .res_type = RPMPD_SMPA, .res_id = 1, @@ -408,102 +408,102 @@ static struct rpmpd SMPA1_md_vfc = { }; /* LPI_CX */ -static struct rpmpd RWLC0_lpi_cx_lvl = { +static struct rpmpd lpi_cx_rwlc0_lvl = { .pd = { .name = "lpi_cx", }, .res_type = RPMPD_RWLC, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWLC0_lpicx_vfl = { - .pd = { .name = "lpicx_vfl", }, +static struct rpmpd lpi_cx_rwlc0_vfl = { + .pd = { .name = "lpi_cx_vfl", }, .res_type = RPMPD_RWLC, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; /* LPI_MX */ -static struct rpmpd RWLM0_lpi_mx_lvl = { +static struct rpmpd lpi_mx_rwlm0_lvl = { .pd = { .name = "lpi_mx", }, .res_type = RPMPD_RWLM, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWLM0_lpimx_vfl = { - .pd = { .name = "lpimx_vfl", }, +static struct rpmpd lpi_mx_rwlm0_vfl = { + .pd = { .name = "lpi_mx_vfl", }, .res_type = RPMPD_RWLM, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; /* SSC_CX */ -static struct rpmpd LDOA26_sscx_corner = { - .pd = { .name = "sscx", }, +static struct rpmpd ssc_cx_l26a_corner = { + .pd = { .name = "ssc_cx", }, .res_type = RPMPD_LDOA, .res_id = 26, .key = KEY_CORNER, }; -static struct rpmpd RWLC0_ssccx_lvl = { - .pd = { .name = "ssccx", }, +static struct rpmpd ssc_cx_rwlc0_lvl = { + .pd = { .name = "ssc_cx", }, .res_type = RPMPD_RWLC, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWSC0_ssccx_lvl = { - .pd = { .name = "ssccx", }, +static struct rpmpd ssc_cx_rwsc0_lvl = { + .pd = { .name = "ssc_cx", }, .res_type = RPMPD_RWSC, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd LDOA26_sscx_vfc = { - .pd = { .name = "sscx_vfc", }, +static struct rpmpd ssc_cx_l26a_vfc = { + .pd = { .name = "ssc_cx_vfc", }, .res_type = RPMPD_LDOA, .res_id = 26, .key = KEY_FLOOR_CORNER, }; -static struct rpmpd RWLC0_ssccx_vfl = { - .pd = { .name = "ssccx_vfl", }, +static struct rpmpd ssc_cx_rwlc0_vfl = { + .pd = { .name = "ssc_cx_vfl", }, .res_type = RPMPD_RWLC, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd RWSC0_ssccx_vfl = { - .pd = { .name = "ssccx_vfl", }, +static struct rpmpd ssc_cx_rwsc0_vfl = { + .pd = { .name = "ssc_cx_vfl", }, .res_type = RPMPD_RWSC, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; /* SSC_MX */ -static struct rpmpd RWLM0_sscmx_lvl = { - .pd = { .name = "sscmx", }, +static struct rpmpd ssc_mx_rwlm0_lvl = { + .pd = { .name = "ssc_mx", }, .res_type = RPMPD_RWLM, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWSM0_sscmx_lvl = { - .pd = { .name = "sscmx", }, +static struct rpmpd ssc_mx_rwsm0_lvl = { + .pd = { .name = "ssc_mx", }, .res_type = RPMPD_RWSM, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWLM0_sscmx_vfl = { - .pd = { .name = "sscmx_vfl", }, +static struct rpmpd ssc_mx_rwlm0_vfl = { + .pd = { .name = "ssc_mx_vfl", }, .res_type = RPMPD_RWLM, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd RWSM0_sscmx_vfl = { - .pd = { .name = "sscmx_vfl", }, +static struct rpmpd ssc_mx_rwsm0_vfl = { + .pd = { .name = "ssc_mx_vfl", }, .res_type = RPMPD_RWSM, .res_id = 0, .key = KEY_FLOOR_LEVEL, @@ -511,12 +511,12 @@ static struct rpmpd RWSM0_sscmx_vfl = { /* mdm9607 RPM Power Domains */ static struct rpmpd *mdm9607_rpmpds[] = { - [MDM9607_VDDCX] = &SMPA3_LEVEL_cx, - [MDM9607_VDDCX_AO] = &SMPA3_LEVEL_cx_ao, - [MDM9607_VDDCX_VFL] = &SMPA3_cx_vfl, - [MDM9607_VDDMX] = &LDOA12_LEVEL_mx, - [MDM9607_VDDMX_AO] = &LDOA12_LEVEL_mx_ao, - [MDM9607_VDDMX_VFL] = &LDOA12_mx_vfl, + [MDM9607_VDDCX] = &cx_s3a_lvl, + [MDM9607_VDDCX_AO] = &cx_s3a_lvl_ao, + [MDM9607_VDDCX_VFL] = &cx_s3a_vfl, + [MDM9607_VDDMX] = &mx_l12a_lvl, + [MDM9607_VDDMX_AO] = &mx_l12a_lvl_ao, + [MDM9607_VDDMX_VFL] = &mx_l12a_vfl, }; static const struct rpmpd_desc mdm9607_desc = { @@ -527,9 +527,9 @@ static const struct rpmpd_desc mdm9607_desc = { /* msm8226 RPM Power Domains */ static struct rpmpd *msm8226_rpmpds[] = { - [MSM8226_VDDCX] = &SMPA1_CORNER_cx, - [MSM8226_VDDCX_AO] = &SMPA1_CORNER_cx_ao, - [MSM8226_VDDCX_VFC] = &SMPA1_cx_vfc, + [MSM8226_VDDCX] = &cx_s1a_corner, + [MSM8226_VDDCX_AO] = &cx_s1a_corner_ao, + [MSM8226_VDDCX_VFC] = &cx_s1a_vfc, }; static const struct rpmpd_desc msm8226_desc = { @@ -540,14 +540,14 @@ static const struct rpmpd_desc msm8226_desc = { /* msm8939 RPM Power Domains */ static struct rpmpd *msm8939_rpmpds[] = { - [MSM8939_VDDMDCX] = &SMPA1_CORNER_md, - [MSM8939_VDDMDCX_AO] = &SMPA1_CORNER_md_ao, - [MSM8939_VDDMDCX_VFC] = &SMPA1_md_vfc, - [MSM8939_VDDCX] = &SMPA2_CORNER_cx, - [MSM8939_VDDCX_AO] = &SMPA2_CORNER_cx_ao, - [MSM8939_VDDCX_VFC] = &SMPA2_cx_vfc, - [MSM8939_VDDMX] = &LDOA3_CORNER_mx, - [MSM8939_VDDMX_AO] = &LDOA3_CORNER_mx_ao, + [MSM8939_VDDMDCX] = &md_s1a_corner, + [MSM8939_VDDMDCX_AO] = &md_s1a_corner_ao, + [MSM8939_VDDMDCX_VFC] = &md_s1a_vfc, + [MSM8939_VDDCX] = &cx_s2a_corner, + [MSM8939_VDDCX_AO] = &cx_s2a_corner_ao, + [MSM8939_VDDCX_VFC] = &cx_s2a_vfc, + [MSM8939_VDDMX] = &mx_l3a_corner, + [MSM8939_VDDMX_AO] = &mx_l3a_corner_ao, }; static const struct rpmpd_desc msm8939_desc = { @@ -558,11 +558,11 @@ static const struct rpmpd_desc msm8939_desc = { /* msm8916 RPM Power Domains */ static struct rpmpd *msm8916_rpmpds[] = { - [MSM8916_VDDCX] = &SMPA1_CORNER_cx, - [MSM8916_VDDCX_AO] = &SMPA1_CORNER_cx_ao, - [MSM8916_VDDCX_VFC] = &SMPA1_cx_vfc, - [MSM8916_VDDMX] = &LDOA3_CORNER_mx, - [MSM8916_VDDMX_AO] = &LDOA3_CORNER_mx_ao, + [MSM8916_VDDCX] = &cx_s1a_corner, + [MSM8916_VDDCX_AO] = &cx_s1a_corner_ao, + [MSM8916_VDDCX_VFC] = &cx_s1a_vfc, + [MSM8916_VDDMX] = &mx_l3a_corner, + [MSM8916_VDDMX_AO] = &mx_l3a_corner_ao, }; static const struct rpmpd_desc msm8916_desc = { @@ -573,13 +573,13 @@ static const struct rpmpd_desc msm8916_desc = { /* msm8953 RPM Power Domains */ static struct rpmpd *msm8953_rpmpds[] = { - [MSM8953_VDDMD] = &SMPA1_LEVEL_md, - [MSM8953_VDDMD_AO] = &SMPA1_LEVEL_md_ao, - [MSM8953_VDDCX] = &SMPA2_LEVEL_cx, - [MSM8953_VDDCX_AO] = &SMPA2_LEVEL_cx_ao, - [MSM8953_VDDCX_VFL] = &SMPA2_cx_vfl, - [MSM8953_VDDMX] = &SMPA7_LEVEL_mx, - [MSM8953_VDDMX_AO] = &SMPA7_LEVEL_mx_ao, + [MSM8953_VDDMD] = &md_s1a_lvl, + [MSM8953_VDDMD_AO] = &md_s1a_lvl_ao, + [MSM8953_VDDCX] = &cx_s2a_lvl, + [MSM8953_VDDCX_AO] = &cx_s2a_lvl_ao, + [MSM8953_VDDCX_VFL] = &cx_s2a_vfl, + [MSM8953_VDDMX] = &mx_s7a_lvl, + [MSM8953_VDDMX_AO] = &mx_s7a_lvl_ao, }; static const struct rpmpd_desc msm8953_desc = { @@ -590,12 +590,12 @@ static const struct rpmpd_desc msm8953_desc = { /* msm8976 RPM Power Domains */ static struct rpmpd *msm8976_rpmpds[] = { - [MSM8976_VDDCX] = &SMPA2_LEVEL_cx, - [MSM8976_VDDCX_AO] = &SMPA2_LEVEL_cx_ao, - [MSM8976_VDDCX_VFL] = &RWSC2_cx_vfl, - [MSM8976_VDDMX] = &SMPA6_LEVEL_mx, - [MSM8976_VDDMX_AO] = &SMPA6_LEVEL_mx_ao, - [MSM8976_VDDMX_VFL] = &RWSM6_mx_vfl, + [MSM8976_VDDCX] = &cx_s2a_lvl, + [MSM8976_VDDCX_AO] = &cx_s2a_lvl_ao, + [MSM8976_VDDCX_VFL] = &cx_rwsc2_vfl, + [MSM8976_VDDMX] = &mx_s6a_lvl, + [MSM8976_VDDMX_AO] = &mx_s6a_lvl_ao, + [MSM8976_VDDMX_VFL] = &mx_rwsm6_vfl, }; static const struct rpmpd_desc msm8976_desc = { @@ -606,15 +606,15 @@ static const struct rpmpd_desc msm8976_desc = { /* msm8994 RPM Power domains */ static struct rpmpd *msm8994_rpmpds[] = { - [MSM8994_VDDCX] = &SMPA1_CORNER_cx, - [MSM8994_VDDCX_AO] = &SMPA1_CORNER_cx_ao, - [MSM8994_VDDCX_VFC] = &SMPA1_cx_vfc, - [MSM8994_VDDMX] = &SMPA2_CORNER_mx, - [MSM8994_VDDMX_AO] = &SMPA2_CORNER_mx_ao, + [MSM8994_VDDCX] = &cx_s1a_corner, + [MSM8994_VDDCX_AO] = &cx_s1a_corner_ao, + [MSM8994_VDDCX_VFC] = &cx_s1a_vfc, + [MSM8994_VDDMX] = &mx_s2a_corner, + [MSM8994_VDDMX_AO] = &mx_s2a_corner_ao, /* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */ - [MSM8994_VDDGFX] = &SMPB2_gfx_corner, - [MSM8994_VDDGFX_VFC] = &SMPB2_gfx_vfc, + [MSM8994_VDDGFX] = &gfx_s2b_corner, + [MSM8994_VDDGFX_VFC] = &gfx_s2b_vfc, }; static const struct rpmpd_desc msm8994_desc = { @@ -625,13 +625,13 @@ static const struct rpmpd_desc msm8994_desc = { /* msm8996 RPM Power domains */ static struct rpmpd *msm8996_rpmpds[] = { - [MSM8996_VDDCX] = &SMPA1_CORNER_cx, - [MSM8996_VDDCX_AO] = &SMPA1_CORNER_cx_ao, - [MSM8996_VDDCX_VFC] = &SMPA1_cx_vfc, - [MSM8996_VDDMX] = &SMPA2_CORNER_mx, - [MSM8996_VDDMX_AO] = &SMPA2_CORNER_mx_ao, - [MSM8996_VDDSSCX] = &LDOA26_sscx_corner, - [MSM8996_VDDSSCX_VFC] = &LDOA26_sscx_vfc, + [MSM8996_VDDCX] = &cx_s1a_corner, + [MSM8996_VDDCX_AO] = &cx_s1a_corner_ao, + [MSM8996_VDDCX_VFC] = &cx_s1a_vfc, + [MSM8996_VDDMX] = &mx_s2a_corner, + [MSM8996_VDDMX_AO] = &mx_s2a_corner_ao, + [MSM8996_VDDSSCX] = &ssc_cx_l26a_corner, + [MSM8996_VDDSSCX_VFC] = &ssc_cx_l26a_vfc, }; static const struct rpmpd_desc msm8996_desc = { @@ -642,16 +642,16 @@ static const struct rpmpd_desc msm8996_desc = { /* msm8998 RPM Power domains */ static struct rpmpd *msm8998_rpmpds[] = { - [MSM8998_VDDCX] = &RWCX0_LEVEL_cx, - [MSM8998_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [MSM8998_VDDCX_VFL] = &RWCX0_cx_vfl, - [MSM8998_VDDMX] = &RWMX0_LEVEL_mx, - [MSM8998_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [MSM8998_VDDMX_VFL] = &RWMX0_mx_vfl, - [MSM8998_SSCCX] = &RWSC0_ssccx_lvl, - [MSM8998_SSCCX_VFL] = &RWSC0_ssccx_vfl, - [MSM8998_SSCMX] = &RWSM0_sscmx_lvl, - [MSM8998_SSCMX_VFL] = &RWSM0_sscmx_vfl, + [MSM8998_VDDCX] = &cx_rwcx0_lvl, + [MSM8998_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [MSM8998_VDDCX_VFL] = &cx_rwcx0_vfl, + [MSM8998_VDDMX] = &mx_rwmx0_lvl, + [MSM8998_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [MSM8998_VDDMX_VFL] = &mx_rwmx0_vfl, + [MSM8998_SSCCX] = &ssc_cx_rwsc0_lvl, + [MSM8998_SSCCX_VFL] = &ssc_cx_rwsc0_vfl, + [MSM8998_SSCMX] = &ssc_mx_rwsm0_lvl, + [MSM8998_SSCMX_VFL] = &ssc_mx_rwsm0_vfl, }; static const struct rpmpd_desc msm8998_desc = { @@ -662,13 +662,13 @@ static const struct rpmpd_desc msm8998_desc = { /* qcs404 RPM Power domains */ static struct rpmpd *qcs404_rpmpds[] = { - [QCS404_VDDMX] = &RWMX0_LEVEL_mx, - [QCS404_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [QCS404_VDDMX_VFL] = &RWMX0_mx_vfl, - [QCS404_LPICX] = &RWLC0_lpi_cx_lvl, - [QCS404_LPICX_VFL] = &RWLC0_lpicx_vfl, - [QCS404_LPIMX] = &RWLM0_lpi_mx_lvl, - [QCS404_LPIMX_VFL] = &RWLM0_lpimx_vfl, + [QCS404_VDDMX] = &mx_rwmx0_lvl, + [QCS404_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [QCS404_VDDMX_VFL] = &mx_rwmx0_vfl, + [QCS404_LPICX] = &lpi_cx_rwlc0_lvl, + [QCS404_LPICX_VFL] = &lpi_cx_rwlc0_vfl, + [QCS404_LPIMX] = &lpi_mx_rwlm0_lvl, + [QCS404_LPIMX_VFL] = &lpi_mx_rwlm0_vfl, }; static const struct rpmpd_desc qcs404_desc = { @@ -679,16 +679,16 @@ static const struct rpmpd_desc qcs404_desc = { /* sdm660 RPM Power domains */ static struct rpmpd *sdm660_rpmpds[] = { - [SDM660_VDDCX] = &RWCX0_LEVEL_cx, - [SDM660_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [SDM660_VDDCX_VFL] = &RWCX0_cx_vfl, - [SDM660_VDDMX] = &RWMX0_LEVEL_mx, - [SDM660_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [SDM660_VDDMX_VFL] = &RWMX0_mx_vfl, - [SDM660_SSCCX] = &RWLC0_ssccx_lvl, - [SDM660_SSCCX_VFL] = &RWLC0_ssccx_vfl, - [SDM660_SSCMX] = &RWLM0_sscmx_lvl, - [SDM660_SSCMX_VFL] = &RWLM0_sscmx_vfl, + [SDM660_VDDCX] = &cx_rwcx0_lvl, + [SDM660_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SDM660_VDDCX_VFL] = &cx_rwcx0_vfl, + [SDM660_VDDMX] = &mx_rwmx0_lvl, + [SDM660_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SDM660_VDDMX_VFL] = &mx_rwmx0_vfl, + [SDM660_SSCCX] = &ssc_cx_rwlc0_lvl, + [SDM660_SSCCX_VFL] = &ssc_cx_rwlc0_vfl, + [SDM660_SSCMX] = &ssc_mx_rwlm0_lvl, + [SDM660_SSCMX_VFL] = &ssc_mx_rwlm0_vfl, }; static const struct rpmpd_desc sdm660_desc = { @@ -699,14 +699,14 @@ static const struct rpmpd_desc sdm660_desc = { /* sm4250/6115 RPM Power domains */ static struct rpmpd *sm6115_rpmpds[] = { - [SM6115_VDDCX] = &RWCX0_LEVEL_cx, - [SM6115_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [SM6115_VDDCX_VFL] = &RWCX0_cx_vfl, - [SM6115_VDDMX] = &RWMX0_LEVEL_mx, - [SM6115_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [SM6115_VDDMX_VFL] = &RWMX0_mx_vfl, - [SM6115_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, - [SM6115_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, + [SM6115_VDDCX] = &cx_rwcx0_lvl, + [SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6115_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6115_VDDMX] = &mx_rwmx0_lvl, + [SM6115_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6115_VDDMX_VFL] = &mx_rwmx0_vfl, + [SM6115_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [SM6115_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc sm6115_desc = { @@ -717,12 +717,12 @@ static const struct rpmpd_desc sm6115_desc = { /* sm6125 RPM Power domains */ static struct rpmpd *sm6125_rpmpds[] = { - [SM6125_VDDCX] = &RWCX0_LEVEL_cx, - [SM6125_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [SM6125_VDDCX_VFL] = &RWCX0_cx_vfl, - [SM6125_VDDMX] = &RWMX0_LEVEL_mx, - [SM6125_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [SM6125_VDDMX_VFL] = &RWMX0_mx_vfl, + [SM6125_VDDCX] = &cx_rwcx0_lvl, + [SM6125_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6125_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6125_VDDMX] = &mx_rwmx0_lvl, + [SM6125_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6125_VDDMX_VFL] = &mx_rwmx0_vfl, }; static const struct rpmpd_desc sm6125_desc = { @@ -732,16 +732,16 @@ static const struct rpmpd_desc sm6125_desc = { }; static struct rpmpd *sm6375_rpmpds[] = { - [SM6375_VDDCX] = &RWCX0_LEVEL_cx, - [SM6375_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [SM6375_VDDCX_VFL] = &RWCX0_cx_vfl, - [SM6375_VDDMX] = &RWMX0_LEVEL_mx, - [SM6375_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [SM6375_VDDMX_VFL] = &RWMX0_mx_vfl, - [SM6375_VDDGX] = &RWGX0_LEVEL_gx, - [SM6375_VDDGX_AO] = &RWGX0_LEVEL_gx_ao, - [SM6375_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, - [SM6375_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, + [SM6375_VDDCX] = &cx_rwcx0_lvl, + [SM6375_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6375_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6375_VDDMX] = &mx_rwmx0_lvl, + [SM6375_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6375_VDDMX_VFL] = &mx_rwmx0_vfl, + [SM6375_VDDGX] = &gx_rwgx0_lvl, + [SM6375_VDDGX_AO] = &gx_rwgx0_lvl_ao, + [SM6375_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [SM6375_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc sm6375_desc = { @@ -751,14 +751,14 @@ static const struct rpmpd_desc sm6375_desc = { }; static struct rpmpd *qcm2290_rpmpds[] = { - [QCM2290_VDDCX] = &RWCX0_LEVEL_cx, - [QCM2290_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [QCM2290_VDDCX_VFL] = &RWCX0_cx_vfl, - [QCM2290_VDDMX] = &RWMX0_LEVEL_mx, - [QCM2290_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [QCM2290_VDDMX_VFL] = &RWMX0_mx_vfl, - [QCM2290_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, - [QCM2290_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, + [QCM2290_VDDCX] = &cx_rwcx0_lvl, + [QCM2290_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [QCM2290_VDDCX_VFL] = &cx_rwcx0_vfl, + [QCM2290_VDDMX] = &mx_rwmx0_lvl, + [QCM2290_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [QCM2290_VDDMX_VFL] = &mx_rwmx0_vfl, + [QCM2290_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [QCM2290_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc qcm2290_desc = { From d338fe40cf37c3f326b5cb743c6436369d452094 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:05 +0100 Subject: [PATCH 29/51] soc: qcom: rpmpd: Make bindings assignments consistent Currently the whitespace between [DT_BINDING] = &struct is all over the place.. some SoC structs have a space, others have a tab, others have N tabs.. Make that a single tab for everybody to keep things coherent. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-7-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 118 +++++++++++++++++++-------------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 695b2fc56f40..946630d82b3d 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -642,16 +642,16 @@ static const struct rpmpd_desc msm8996_desc = { /* msm8998 RPM Power domains */ static struct rpmpd *msm8998_rpmpds[] = { - [MSM8998_VDDCX] = &cx_rwcx0_lvl, - [MSM8998_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [MSM8998_VDDCX_VFL] = &cx_rwcx0_vfl, - [MSM8998_VDDMX] = &mx_rwmx0_lvl, - [MSM8998_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [MSM8998_VDDMX_VFL] = &mx_rwmx0_vfl, - [MSM8998_SSCCX] = &ssc_cx_rwsc0_lvl, - [MSM8998_SSCCX_VFL] = &ssc_cx_rwsc0_vfl, - [MSM8998_SSCMX] = &ssc_mx_rwsm0_lvl, - [MSM8998_SSCMX_VFL] = &ssc_mx_rwsm0_vfl, + [MSM8998_VDDCX] = &cx_rwcx0_lvl, + [MSM8998_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [MSM8998_VDDCX_VFL] = &cx_rwcx0_vfl, + [MSM8998_VDDMX] = &mx_rwmx0_lvl, + [MSM8998_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [MSM8998_VDDMX_VFL] = &mx_rwmx0_vfl, + [MSM8998_SSCCX] = &ssc_cx_rwsc0_lvl, + [MSM8998_SSCCX_VFL] = &ssc_cx_rwsc0_vfl, + [MSM8998_SSCMX] = &ssc_mx_rwsm0_lvl, + [MSM8998_SSCMX_VFL] = &ssc_mx_rwsm0_vfl, }; static const struct rpmpd_desc msm8998_desc = { @@ -662,13 +662,13 @@ static const struct rpmpd_desc msm8998_desc = { /* qcs404 RPM Power domains */ static struct rpmpd *qcs404_rpmpds[] = { - [QCS404_VDDMX] = &mx_rwmx0_lvl, - [QCS404_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [QCS404_VDDMX_VFL] = &mx_rwmx0_vfl, - [QCS404_LPICX] = &lpi_cx_rwlc0_lvl, - [QCS404_LPICX_VFL] = &lpi_cx_rwlc0_vfl, - [QCS404_LPIMX] = &lpi_mx_rwlm0_lvl, - [QCS404_LPIMX_VFL] = &lpi_mx_rwlm0_vfl, + [QCS404_VDDMX] = &mx_rwmx0_lvl, + [QCS404_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [QCS404_VDDMX_VFL] = &mx_rwmx0_vfl, + [QCS404_LPICX] = &lpi_cx_rwlc0_lvl, + [QCS404_LPICX_VFL] = &lpi_cx_rwlc0_vfl, + [QCS404_LPIMX] = &lpi_mx_rwlm0_lvl, + [QCS404_LPIMX_VFL] = &lpi_mx_rwlm0_vfl, }; static const struct rpmpd_desc qcs404_desc = { @@ -679,16 +679,16 @@ static const struct rpmpd_desc qcs404_desc = { /* sdm660 RPM Power domains */ static struct rpmpd *sdm660_rpmpds[] = { - [SDM660_VDDCX] = &cx_rwcx0_lvl, - [SDM660_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [SDM660_VDDCX_VFL] = &cx_rwcx0_vfl, - [SDM660_VDDMX] = &mx_rwmx0_lvl, - [SDM660_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [SDM660_VDDMX_VFL] = &mx_rwmx0_vfl, - [SDM660_SSCCX] = &ssc_cx_rwlc0_lvl, - [SDM660_SSCCX_VFL] = &ssc_cx_rwlc0_vfl, - [SDM660_SSCMX] = &ssc_mx_rwlm0_lvl, - [SDM660_SSCMX_VFL] = &ssc_mx_rwlm0_vfl, + [SDM660_VDDCX] = &cx_rwcx0_lvl, + [SDM660_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SDM660_VDDCX_VFL] = &cx_rwcx0_vfl, + [SDM660_VDDMX] = &mx_rwmx0_lvl, + [SDM660_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SDM660_VDDMX_VFL] = &mx_rwmx0_vfl, + [SDM660_SSCCX] = &ssc_cx_rwlc0_lvl, + [SDM660_SSCCX_VFL] = &ssc_cx_rwlc0_vfl, + [SDM660_SSCMX] = &ssc_mx_rwlm0_lvl, + [SDM660_SSCMX_VFL] = &ssc_mx_rwlm0_vfl, }; static const struct rpmpd_desc sdm660_desc = { @@ -699,14 +699,14 @@ static const struct rpmpd_desc sdm660_desc = { /* sm4250/6115 RPM Power domains */ static struct rpmpd *sm6115_rpmpds[] = { - [SM6115_VDDCX] = &cx_rwcx0_lvl, - [SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [SM6115_VDDCX_VFL] = &cx_rwcx0_vfl, - [SM6115_VDDMX] = &mx_rwmx0_lvl, - [SM6115_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [SM6115_VDDMX_VFL] = &mx_rwmx0_vfl, - [SM6115_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, - [SM6115_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, + [SM6115_VDDCX] = &cx_rwcx0_lvl, + [SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6115_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6115_VDDMX] = &mx_rwmx0_lvl, + [SM6115_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6115_VDDMX_VFL] = &mx_rwmx0_vfl, + [SM6115_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [SM6115_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc sm6115_desc = { @@ -717,12 +717,12 @@ static const struct rpmpd_desc sm6115_desc = { /* sm6125 RPM Power domains */ static struct rpmpd *sm6125_rpmpds[] = { - [SM6125_VDDCX] = &cx_rwcx0_lvl, - [SM6125_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [SM6125_VDDCX_VFL] = &cx_rwcx0_vfl, - [SM6125_VDDMX] = &mx_rwmx0_lvl, - [SM6125_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [SM6125_VDDMX_VFL] = &mx_rwmx0_vfl, + [SM6125_VDDCX] = &cx_rwcx0_lvl, + [SM6125_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6125_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6125_VDDMX] = &mx_rwmx0_lvl, + [SM6125_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6125_VDDMX_VFL] = &mx_rwmx0_vfl, }; static const struct rpmpd_desc sm6125_desc = { @@ -732,16 +732,16 @@ static const struct rpmpd_desc sm6125_desc = { }; static struct rpmpd *sm6375_rpmpds[] = { - [SM6375_VDDCX] = &cx_rwcx0_lvl, - [SM6375_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [SM6375_VDDCX_VFL] = &cx_rwcx0_vfl, - [SM6375_VDDMX] = &mx_rwmx0_lvl, - [SM6375_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [SM6375_VDDMX_VFL] = &mx_rwmx0_vfl, - [SM6375_VDDGX] = &gx_rwgx0_lvl, - [SM6375_VDDGX_AO] = &gx_rwgx0_lvl_ao, - [SM6375_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, - [SM6375_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, + [SM6375_VDDCX] = &cx_rwcx0_lvl, + [SM6375_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6375_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6375_VDDMX] = &mx_rwmx0_lvl, + [SM6375_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6375_VDDMX_VFL] = &mx_rwmx0_vfl, + [SM6375_VDDGX] = &gx_rwgx0_lvl, + [SM6375_VDDGX_AO] = &gx_rwgx0_lvl_ao, + [SM6375_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [SM6375_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc sm6375_desc = { @@ -751,14 +751,14 @@ static const struct rpmpd_desc sm6375_desc = { }; static struct rpmpd *qcm2290_rpmpds[] = { - [QCM2290_VDDCX] = &cx_rwcx0_lvl, - [QCM2290_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [QCM2290_VDDCX_VFL] = &cx_rwcx0_vfl, - [QCM2290_VDDMX] = &mx_rwmx0_lvl, - [QCM2290_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [QCM2290_VDDMX_VFL] = &mx_rwmx0_vfl, - [QCM2290_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, - [QCM2290_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, + [QCM2290_VDDCX] = &cx_rwcx0_lvl, + [QCM2290_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [QCM2290_VDDCX_VFL] = &cx_rwcx0_vfl, + [QCM2290_VDDMX] = &mx_rwmx0_lvl, + [QCM2290_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [QCM2290_VDDMX_VFL] = &mx_rwmx0_vfl, + [QCM2290_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [QCM2290_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc qcm2290_desc = { From decd6e77e02eff517efe11dfc181ce1b5bef3405 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:06 +0100 Subject: [PATCH 30/51] soc: qcom: rpmpd: Add parent PD support In some cases (like with the GPU core clock on GMU-less SoCs) it's required that we scale more than one voltage domain. This can be achieved by linking them in a parent-child relationship. Add support for specifying a parent PD, similarly to what has been done in the RPMhPD driver. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-8-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 946630d82b3d..2027c820caa7 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -48,6 +48,7 @@ struct rpmpd_req { struct rpmpd { struct generic_pm_domain pd; + struct generic_pm_domain *parent; struct rpmpd *peer; const bool active_only; unsigned int corner; @@ -969,6 +970,15 @@ static int rpmpd_probe(struct platform_device *pdev) data->domains[i] = &rpmpds[i]->pd; } + /* Add subdomains */ + for (i = 0; i < num; i++) { + if (!rpmpds[i]) + continue; + + if (rpmpds[i]->parent) + pm_genpd_add_subdomain(rpmpds[i]->parent, &rpmpds[i]->pd); + } + return of_genpd_add_provider_onecell(pdev->dev.of_node, data); } From ec90637c9946cc8e37afa4c1feb33fdb1fa15b68 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:07 +0100 Subject: [PATCH 31/51] soc: qcom: rpmpd: Hook up VDDMX as parent of SM6375 VDDGX The GPU core clock requires that both VDDGX and VDDMX domains are scaled at the same rate at the same time (well, MX just before GX but you get the idea). Set MX as parent of GX to take care of that. Suggested-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-9-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 2027c820caa7..84283719853c 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -216,18 +216,22 @@ static struct rpmpd gfx_s2b_vfc = { .key = KEY_FLOOR_CORNER, }; +static struct rpmpd mx_rwmx0_lvl; static struct rpmpd gx_rwgx0_lvl_ao; static struct rpmpd gx_rwgx0_lvl = { .pd = { .name = "gx", }, .peer = &gx_rwgx0_lvl_ao, .res_type = RPMPD_RWGX, + .parent = &mx_rwmx0_lvl.pd, .res_id = 0, .key = KEY_LEVEL, }; +static struct rpmpd mx_rwmx0_lvl_ao; static struct rpmpd gx_rwgx0_lvl_ao = { .pd = { .name = "gx_ao", }, .peer = &gx_rwgx0_lvl, + .parent = &mx_rwmx0_lvl_ao.pd, .active_only = true, .res_type = RPMPD_RWGX, .res_id = 0, From e556c94e8c20bcfb6c910e93a0cfd2d0cce5adc8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:08 +0100 Subject: [PATCH 32/51] soc: qcom: rpmpd: Remove useless comments It goes without saying that socname_rpmpds[] is the array of the RPM power domains associated with socname. Remove these comments. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-10-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 84283719853c..f8397dcb146c 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -514,7 +514,6 @@ static struct rpmpd ssc_mx_rwsm0_vfl = { .key = KEY_FLOOR_LEVEL, }; -/* mdm9607 RPM Power Domains */ static struct rpmpd *mdm9607_rpmpds[] = { [MDM9607_VDDCX] = &cx_s3a_lvl, [MDM9607_VDDCX_AO] = &cx_s3a_lvl_ao, @@ -530,7 +529,6 @@ static const struct rpmpd_desc mdm9607_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; -/* msm8226 RPM Power Domains */ static struct rpmpd *msm8226_rpmpds[] = { [MSM8226_VDDCX] = &cx_s1a_corner, [MSM8226_VDDCX_AO] = &cx_s1a_corner_ao, @@ -543,7 +541,6 @@ static const struct rpmpd_desc msm8226_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; -/* msm8939 RPM Power Domains */ static struct rpmpd *msm8939_rpmpds[] = { [MSM8939_VDDMDCX] = &md_s1a_corner, [MSM8939_VDDMDCX_AO] = &md_s1a_corner_ao, @@ -561,7 +558,6 @@ static const struct rpmpd_desc msm8939_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; -/* msm8916 RPM Power Domains */ static struct rpmpd *msm8916_rpmpds[] = { [MSM8916_VDDCX] = &cx_s1a_corner, [MSM8916_VDDCX_AO] = &cx_s1a_corner_ao, @@ -576,7 +572,6 @@ static const struct rpmpd_desc msm8916_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; -/* msm8953 RPM Power Domains */ static struct rpmpd *msm8953_rpmpds[] = { [MSM8953_VDDMD] = &md_s1a_lvl, [MSM8953_VDDMD_AO] = &md_s1a_lvl_ao, @@ -593,7 +588,6 @@ static const struct rpmpd_desc msm8953_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; -/* msm8976 RPM Power Domains */ static struct rpmpd *msm8976_rpmpds[] = { [MSM8976_VDDCX] = &cx_s2a_lvl, [MSM8976_VDDCX_AO] = &cx_s2a_lvl_ao, @@ -609,7 +603,6 @@ static const struct rpmpd_desc msm8976_desc = { .max_state = RPM_SMD_LEVEL_TURBO_HIGH, }; -/* msm8994 RPM Power domains */ static struct rpmpd *msm8994_rpmpds[] = { [MSM8994_VDDCX] = &cx_s1a_corner, [MSM8994_VDDCX_AO] = &cx_s1a_corner_ao, @@ -628,7 +621,6 @@ static const struct rpmpd_desc msm8994_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; -/* msm8996 RPM Power domains */ static struct rpmpd *msm8996_rpmpds[] = { [MSM8996_VDDCX] = &cx_s1a_corner, [MSM8996_VDDCX_AO] = &cx_s1a_corner_ao, @@ -645,7 +637,6 @@ static const struct rpmpd_desc msm8996_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; -/* msm8998 RPM Power domains */ static struct rpmpd *msm8998_rpmpds[] = { [MSM8998_VDDCX] = &cx_rwcx0_lvl, [MSM8998_VDDCX_AO] = &cx_rwcx0_lvl_ao, @@ -665,7 +656,6 @@ static const struct rpmpd_desc msm8998_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; -/* qcs404 RPM Power domains */ static struct rpmpd *qcs404_rpmpds[] = { [QCS404_VDDMX] = &mx_rwmx0_lvl, [QCS404_VDDMX_AO] = &mx_rwmx0_lvl_ao, @@ -682,7 +672,6 @@ static const struct rpmpd_desc qcs404_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; -/* sdm660 RPM Power domains */ static struct rpmpd *sdm660_rpmpds[] = { [SDM660_VDDCX] = &cx_rwcx0_lvl, [SDM660_VDDCX_AO] = &cx_rwcx0_lvl_ao, @@ -702,7 +691,6 @@ static const struct rpmpd_desc sdm660_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; -/* sm4250/6115 RPM Power domains */ static struct rpmpd *sm6115_rpmpds[] = { [SM6115_VDDCX] = &cx_rwcx0_lvl, [SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao, @@ -720,7 +708,6 @@ static const struct rpmpd_desc sm6115_desc = { .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, }; -/* sm6125 RPM Power domains */ static struct rpmpd *sm6125_rpmpds[] = { [SM6125_VDDCX] = &cx_rwcx0_lvl, [SM6125_VDDCX_AO] = &cx_rwcx0_lvl_ao, From 81ac39144bf65c5f8ee00e61308fe1f3399b347c Mon Sep 17 00:00:00 2001 From: Poovendhan Selvaraj Date: Thu, 16 Feb 2023 17:30:08 +0530 Subject: [PATCH 33/51] dt-bindings: scm: Add compatible for IPQ9574 Add the scm compatible string for IPQ9574 SoC Acked-by: Krzysztof Kozlowski Signed-off-by: Poovendhan Selvaraj Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216120012.28357-2-quic_poovendh@quicinc.com --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index a66e99812b1f..868fc7e555a6 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -27,6 +27,7 @@ properties: - qcom,scm-ipq6018 - qcom,scm-ipq806x - qcom,scm-ipq8074 + - qcom,scm-ipq9574 - qcom,scm-mdm9607 - qcom,scm-msm8226 - qcom,scm-msm8660 From 9e4a7652d7028d40b2dd6636d400ca6266d641ef Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 7 Mar 2023 11:52:30 +0530 Subject: [PATCH 34/51] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM Document the compatible for IPQ5332 SCM. Acked-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307062232.4889-8-quic_kathirav@quicinc.com --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 868fc7e555a6..ddda28bddde5 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -24,6 +24,7 @@ properties: - qcom,scm-apq8064 - qcom,scm-apq8084 - qcom,scm-ipq4019 + - qcom,scm-ipq5332 - qcom,scm-ipq6018 - qcom,scm-ipq806x - qcom,scm-ipq8074 From 968a26a07f75377afbd4f7bb18ef587a1443c244 Mon Sep 17 00:00:00 2001 From: Elliot Berman Date: Mon, 13 Feb 2023 10:18:29 -0800 Subject: [PATCH 35/51] firmware: qcom_scm: Use fixed width src vm bitmap The maximum VMID for assign_mem is 63. Use a u64 to represent this bitmap instead of architecture-dependent "unsigned int" which varies in size on 32-bit and 64-bit platforms. Acked-by: Kalle Valo (ath10k) Tested-by: Gokul krishna Krishnakumar Signed-off-by: Elliot Berman Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230213181832.3489174-1-quic_eberman@quicinc.com --- drivers/firmware/qcom_scm.c | 12 +++++++----- drivers/misc/fastrpc.c | 2 +- drivers/net/wireless/ath/ath10k/qmi.c | 4 ++-- drivers/remoteproc/qcom_q6v5_mss.c | 8 ++++---- drivers/remoteproc/qcom_q6v5_pas.c | 2 +- drivers/soc/qcom/rmtfs_mem.c | 2 +- include/linux/firmware/qcom/qcom_scm.h | 2 +- 7 files changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 468d4d5ab550..b95616b35bff 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -905,7 +905,7 @@ static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, * Return negative errno on failure or 0 on success with @srcvm updated. */ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, - unsigned int *srcvm, + u64 *srcvm, const struct qcom_scm_vmperm *newvm, unsigned int dest_cnt) { @@ -922,9 +922,9 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, __le32 *src; void *ptr; int ret, i, b; - unsigned long srcvm_bits = *srcvm; + u64 srcvm_bits = *srcvm; - src_sz = hweight_long(srcvm_bits) * sizeof(*src); + src_sz = hweight64(srcvm_bits) * sizeof(*src); mem_to_map_sz = sizeof(*mem_to_map); dest_sz = dest_cnt * sizeof(*destvm); ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) + @@ -937,8 +937,10 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, /* Fill source vmid detail */ src = ptr; i = 0; - for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG) - src[i++] = cpu_to_le32(b); + for (b = 0; b < BITS_PER_TYPE(u64); b++) { + if (srcvm_bits & BIT(b)) + src[i++] = cpu_to_le32(b); + } /* Fill details of mem buff to map */ mem_to_map = ptr + ALIGN(src_sz, SZ_64); diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index a701132638cf..f48466960f1b 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -262,7 +262,7 @@ struct fastrpc_channel_ctx { int domain_id; int sesscount; int vmcount; - u32 perms; + u64 perms; struct qcom_scm_vmperm vmperms[FASTRPC_MAX_VMIDS]; struct rpmsg_device *rpdev; struct fastrpc_session_ctx session[FASTRPC_MAX_SESSIONS]; diff --git a/drivers/net/wireless/ath/ath10k/qmi.c b/drivers/net/wireless/ath/ath10k/qmi.c index 90f457b8e1fe..038c5903c0dc 100644 --- a/drivers/net/wireless/ath/ath10k/qmi.c +++ b/drivers/net/wireless/ath/ath10k/qmi.c @@ -33,7 +33,7 @@ static int ath10k_qmi_map_msa_permission(struct ath10k_qmi *qmi, { struct qcom_scm_vmperm dst_perms[3]; struct ath10k *ar = qmi->ar; - unsigned int src_perms; + u64 src_perms; u32 perm_count; int ret; @@ -65,7 +65,7 @@ static int ath10k_qmi_unmap_msa_permission(struct ath10k_qmi *qmi, { struct qcom_scm_vmperm dst_perms; struct ath10k *ar = qmi->ar; - unsigned int src_perms; + u64 src_perms; int ret; src_perms = BIT(QCOM_SCM_VMID_MSS_MSA) | BIT(QCOM_SCM_VMID_WLAN); diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index ab053084f7a2..1ba711bc0100 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -235,8 +235,8 @@ struct q6v5 { bool has_qaccept_regs; bool has_ext_cntl_regs; bool has_vq6; - int mpss_perm; - int mba_perm; + u64 mpss_perm; + u64 mba_perm; const char *hexagon_mdt_image; int version; }; @@ -414,7 +414,7 @@ static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds, } } -static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm, +static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, u64 *current_perm, bool local, bool remote, phys_addr_t addr, size_t size) { @@ -967,7 +967,7 @@ static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw, unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; dma_addr_t phys; void *metadata; - int mdata_perm; + u64 mdata_perm; int xferop_ret; size_t size; void *ptr; diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 0871108fb4dc..c99a20542685 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -94,7 +94,7 @@ struct qcom_adsp { size_t region_assign_size; int region_assign_idx; - int region_assign_perms; + u64 region_assign_perms; struct qcom_rproc_glink glink_subdev; struct qcom_rproc_subdev smd_subdev; diff --git a/drivers/soc/qcom/rmtfs_mem.c b/drivers/soc/qcom/rmtfs_mem.c index 2d3ee22b9249..2657c6105bb7 100644 --- a/drivers/soc/qcom/rmtfs_mem.c +++ b/drivers/soc/qcom/rmtfs_mem.c @@ -31,7 +31,7 @@ struct qcom_rmtfs_mem { unsigned int client_id; - unsigned int perms; + u64 perms; }; static ssize_t qcom_rmtfs_mem_show(struct device *dev, diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 1e449a5d7f5c..250ea4efb7cb 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -94,7 +94,7 @@ extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, u32 cp_nonpixel_start, u32 cp_nonpixel_size); extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, - unsigned int *src, + u64 *src, const struct qcom_scm_vmperm *newvm, unsigned int dest_cnt); From 56d2156e7c298ecad5a113a81e5550631bcf7fd5 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Fri, 17 Feb 2023 19:50:25 +0530 Subject: [PATCH 36/51] dt-bindings: soc: qcom: smd-rpm: Add IPQ9574 compatible Document the compatible for RPM communication over SMD for IPQ9574 SoC Signed-off-by: Devi Priya Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217142030.16012-2-quic_devipriy@quicinc.com --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 16fd67c0bd1f..2a5791ebc8dd 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -33,6 +33,7 @@ properties: enum: - qcom,rpm-apq8084 - qcom,rpm-ipq6018 + - qcom,rpm-ipq9574 - qcom,rpm-msm8226 - qcom,rpm-msm8909 - qcom,rpm-msm8916 From bbf97c274da60fcfbb8ebde70a1c3abc6102c709 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 6 Mar 2023 15:11:56 -0800 Subject: [PATCH 37/51] dt-bindings: firmware: qcom,scm: Update QDU1000/QRU1000 compatible Update compatible for QDU1000 and QRU1000 to include the interconnect these devices have. Signed-off-by: Melody Olvera Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306231202.12223-2-quic_molvera@quicinc.com --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index ddda28bddde5..543feb3b6c58 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -168,6 +168,7 @@ allOf: compatible: contains: enum: + - qcom,scm-qdu1000 - qcom,scm-sm8450 - qcom,scm-sm8550 then: From 9559342891be54d9ffd13061022d9e5d24b2577a Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 6 Mar 2023 15:11:57 -0800 Subject: [PATCH 38/51] dt-bindings: soc: qcom: aoss: Document QDU1000/QRU1000 compatible Add compatible for QDU1000 and QRU1000 aoss devices. Signed-off-by: Melody Olvera Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306231202.12223-3-quic_molvera@quicinc.com --- Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index ab607efbb64c..798f15588ee2 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -25,6 +25,7 @@ properties: compatible: items: - enum: + - qcom,qdu1000-aoss-qmp - qcom,sc7180-aoss-qmp - qcom,sc7280-aoss-qmp - qcom,sc8180x-aoss-qmp From 781d32d1c9709fd25655c4e3e3e15370ae4ae4db Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 16 Mar 2023 20:44:26 +0530 Subject: [PATCH 39/51] firmware: qcom_scm: Clear download bit during reboot During normal restart of a system download bit should be cleared irrespective of whether download mode is set or not. Fixes: 8c1b7dc9ba22 ("firmware: qcom: scm: Expose download-mode control") Signed-off-by: Mukesh Ojha Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1678979666-551-1-git-send-email-quic_mojha@quicinc.com --- drivers/firmware/qcom_scm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index b95616b35bff..ce76f5263aa3 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1508,8 +1508,7 @@ static int qcom_scm_probe(struct platform_device *pdev) static void qcom_scm_shutdown(struct platform_device *pdev) { /* Clean shutdown, disable download mode to allow normal restart */ - if (download_mode) - qcom_scm_set_download_mode(false); + qcom_scm_set_download_mode(false); } static const struct of_device_id qcom_scm_dt_match[] = { From 14bc45c4e72da1a80311cd82815867f36599f698 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:42 +0100 Subject: [PATCH 40/51] dt-bindings: soc: qcom: qcom,pmic-glink: document SM8450 compatible Document the SM8450 compatible used to describe the pmic glink on this platform. Acked-by: Rob Herring Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-2-552f3b721f9e@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index cf863683c21a..a85bc14de065 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -25,6 +25,7 @@ properties: - qcom,sc8180x-pmic-glink - qcom,sc8280xp-pmic-glink - qcom,sm8350-pmic-glink + - qcom,sm8450-pmic-glink - const: qcom,pmic-glink '#address-cells': From 84a334131f091d83239f54cc40627d9b28324b45 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:43 +0100 Subject: [PATCH 41/51] dt-bindings: soc: qcom: qcom,pmic-glink: document SM8550 compatible Document the SM8550 compatible used to describe the pmic glink on this platform. Acked-by: Rob Herring Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-3-552f3b721f9e@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index a85bc14de065..6440dc801387 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -26,6 +26,7 @@ properties: - qcom,sc8280xp-pmic-glink - qcom,sm8350-pmic-glink - qcom,sm8450-pmic-glink + - qcom,sm8550-pmic-glink - const: qcom,pmic-glink '#address-cells': From ff642773b6b5b801f2f3bbdabe22c3d02656981e Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:44 +0100 Subject: [PATCH 42/51] soc: qcom: pmic_glink: register ucsi aux device Only register UCSI on know working devices, like on the SM8450 or SM8550 which requires UCSI to get USB mode switch events. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-4-552f3b721f9e@linaro.org --- drivers/soc/qcom/pmic_glink.c | 65 +++++++++++++++++++++++++++++------ 1 file changed, 54 insertions(+), 11 deletions(-) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index bb3fb57abcc6..8bf95df0a56a 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -4,6 +4,7 @@ * Copyright (c) 2022, Linaro Ltd */ #include +#include #include #include #include @@ -11,12 +12,23 @@ #include #include +enum { + PMIC_GLINK_CLIENT_BATT = 0, + PMIC_GLINK_CLIENT_ALTMODE, + PMIC_GLINK_CLIENT_UCSI, +}; + +#define PMIC_GLINK_CLIENT_DEFAULT (BIT(PMIC_GLINK_CLIENT_BATT) | \ + BIT(PMIC_GLINK_CLIENT_ALTMODE)) + struct pmic_glink { struct device *dev; struct pdr_handle *pdr; struct rpmsg_endpoint *ept; + unsigned long client_mask; + struct auxiliary_device altmode_aux; struct auxiliary_device ps_aux; struct auxiliary_device ucsi_aux; @@ -233,6 +245,7 @@ static struct rpmsg_driver pmic_glink_rpmsg_driver = { static int pmic_glink_probe(struct platform_device *pdev) { + const unsigned long *match_data; struct pdr_service *service; struct pmic_glink *pg; int ret; @@ -249,12 +262,27 @@ static int pmic_glink_probe(struct platform_device *pdev) mutex_init(&pg->client_lock); mutex_init(&pg->state_lock); - ret = pmic_glink_add_aux_device(pg, &pg->altmode_aux, "altmode"); - if (ret) - return ret; - ret = pmic_glink_add_aux_device(pg, &pg->ps_aux, "power-supply"); - if (ret) - goto out_release_altmode_aux; + match_data = (unsigned long *)of_device_get_match_data(&pdev->dev); + if (match_data) + pg->client_mask = *match_data; + else + pg->client_mask = PMIC_GLINK_CLIENT_DEFAULT; + + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) { + ret = pmic_glink_add_aux_device(pg, &pg->ucsi_aux, "ucsi"); + if (ret) + return ret; + } + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) { + ret = pmic_glink_add_aux_device(pg, &pg->altmode_aux, "altmode"); + if (ret) + goto out_release_ucsi_aux; + } + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) { + ret = pmic_glink_add_aux_device(pg, &pg->ps_aux, "power-supply"); + if (ret) + goto out_release_altmode_aux; + } pg->pdr = pdr_handle_alloc(pmic_glink_pdr_callback, pg); if (IS_ERR(pg->pdr)) { @@ -278,9 +306,14 @@ static int pmic_glink_probe(struct platform_device *pdev) out_release_pdr_handle: pdr_handle_release(pg->pdr); out_release_aux_devices: - pmic_glink_del_aux_device(pg, &pg->ps_aux); + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) + pmic_glink_del_aux_device(pg, &pg->ps_aux); out_release_altmode_aux: - pmic_glink_del_aux_device(pg, &pg->altmode_aux); + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) + pmic_glink_del_aux_device(pg, &pg->altmode_aux); +out_release_ucsi_aux: + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) + pmic_glink_del_aux_device(pg, &pg->ucsi_aux); return ret; } @@ -291,8 +324,12 @@ static int pmic_glink_remove(struct platform_device *pdev) pdr_handle_release(pg->pdr); - pmic_glink_del_aux_device(pg, &pg->ps_aux); - pmic_glink_del_aux_device(pg, &pg->altmode_aux); + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) + pmic_glink_del_aux_device(pg, &pg->ps_aux); + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) + pmic_glink_del_aux_device(pg, &pg->altmode_aux); + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) + pmic_glink_del_aux_device(pg, &pg->ucsi_aux); mutex_lock(&__pmic_glink_lock); __pmic_glink = NULL; @@ -301,8 +338,14 @@ static int pmic_glink_remove(struct platform_device *pdev) return 0; } +/* Do not handle altmode for now on those platforms */ +static const unsigned long pmic_glink_sm8450_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | + BIT(PMIC_GLINK_CLIENT_UCSI); + static const struct of_device_id pmic_glink_of_match[] = { - { .compatible = "qcom,pmic-glink", }, + { .compatible = "qcom,sm8450-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, + { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, + { .compatible = "qcom,pmic-glink" }, {} }; MODULE_DEVICE_TABLE(of, pmic_glink_of_match); From 34d84c3b0f63978efcb5136a6fd2e7e9d889da70 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Mar 2023 13:24:28 +0100 Subject: [PATCH 43/51] dt-bindings: soc: qcom: smd-rpm: re-add missing qcom,rpm-msm8994 Re-add the qcom,rpm-msm8994 compatible, dropped during conversion from TXT to DT schema: apq8094-sony-xperia-kitakami-karin_windy.dtb: smd: rpm:rpm-requests:compatible:0: 'qcom,rpm-msm8994' is not one of ['qcom,rpm-apq8084' ...] Fixes: f935a752f229 ("dt-bindings: soc: qcom: smd-rpm: Convert binding to YAML schema") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Petr Vorel Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305122428.167580-1-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 2a5791ebc8dd..94765fbc868e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -41,6 +41,7 @@ properties: - qcom,rpm-msm8953 - qcom,rpm-msm8974 - qcom,rpm-msm8976 + - qcom,rpm-msm8994 - qcom,rpm-msm8996 - qcom,rpm-msm8998 - qcom,rpm-sdm660 @@ -85,6 +86,7 @@ if: - qcom,rpm-msm8974 - qcom,rpm-msm8976 - qcom,rpm-msm8953 + - qcom,rpm-msm8994 then: properties: qcom,glink-channels: false From 1e0952e7b978eb4a182c4a9c003f9313d30d00df Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 Mar 2023 23:26:26 +0300 Subject: [PATCH 44/51] dt-bindings: arm: msm: Add LLCC for SM7150 Add LLCC compatible for SM7150 SoC. Signed-off-by: Danila Tikhonov Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305202627.402386-2-danila@jiaxyga.com --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 93b977428a14..02cc6894eb13 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -26,6 +26,7 @@ properties: - qcom,sc8280xp-llcc - qcom,sdm845-llcc - qcom,sm6350-llcc + - qcom,sm7150-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc - qcom,sm8350-llcc From 92b9d86252c1d76faf06f155c2a73b0c673bf59d Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 Mar 2023 23:26:27 +0300 Subject: [PATCH 45/51] soc: qcom: llcc: Add configuration data for SM7150 Add LLCC configuration data for SM7150 SoC. Signed-off-by: Danila Tikhonov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305202627.402386-3-danila@jiaxyga.com --- drivers/soc/qcom/llcc-qcom.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index a5140f19f200..97c0908c689c 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -226,6 +226,14 @@ static const struct llcc_slice_config sm6350_data[] = { { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, }; +static const struct llcc_slice_config sm7150_data[] = { + { LLCC_CPUSS, 1, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 1 }, + { LLCC_MDM, 8, 128, 2, 0, 0xF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_GPUHTW, 11, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_GPU, 12, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_NPU, 23, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 0 }, +}; + static const struct llcc_slice_config sm8150_data[] = { { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, @@ -464,6 +472,14 @@ static const struct qcom_llcc_config sm6350_cfg = { .edac_reg_offset = &llcc_v1_edac_reg_offset, }; +static const struct qcom_llcc_config sm7150_cfg = { + .sct_data = sm7150_data, + .size = ARRAY_SIZE(sm7150_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, +}; + static const struct qcom_llcc_config sm8150_cfg = { .sct_data = sm8150_data, .size = ARRAY_SIZE(sm8150_data), @@ -1041,6 +1057,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, + { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, From fb1eb0b5dcf6f214479e853ee466958190785ab4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 7 Mar 2023 02:22:47 +0100 Subject: [PATCH 46/51] firmware: qcom_scm: Add SM6375 compatible While it was introduced in bindings, requiring a core clock, and added into the DT, this compatible was apparently forgotten about on the driver side of things. Fix it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307012247.3655547-1-konrad.dybcio@linaro.org --- drivers/firmware/qcom_scm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index ce76f5263aa3..280d6a4ac71a 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1543,6 +1543,7 @@ static const struct of_device_id qcom_scm_dt_match[] = { }, { .compatible = "qcom,scm-msm8994" }, { .compatible = "qcom,scm-msm8996" }, + { .compatible = "qcom,scm-sm6375", .data = (void *)SCM_HAS_CORE_CLK }, { .compatible = "qcom,scm" }, {} }; From 74f9d27ac7591e0df05c85ca5eb538253f39919d Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Fri, 24 Mar 2023 10:18:53 +0800 Subject: [PATCH 47/51] soc: qcom: smsm: Use dev_err_probe() Replace the open-code with dev_err_probe() to simplify the code. Signed-off-by: Ye Xingchen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/202303241018532824420@zte.com.cn --- drivers/soc/qcom/smsm.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index 8c137dff7dac..c58cfff64856 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -452,11 +452,10 @@ static int smsm_get_size_info(struct qcom_smsm *smsm) } *info; info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SIZE_INFO, &size); - if (IS_ERR(info) && PTR_ERR(info) != -ENOENT) { - if (PTR_ERR(info) != -EPROBE_DEFER) - dev_err(smsm->dev, "unable to retrieve smsm size info\n"); - return PTR_ERR(info); - } else if (IS_ERR(info) || size != sizeof(*info)) { + if (IS_ERR(info) && PTR_ERR(info) != -ENOENT) + return dev_err_probe(smsm->dev, PTR_ERR(info), + "unable to retrieve smsm size info\n"); + else if (IS_ERR(info) || size != sizeof(*info)) { dev_warn(smsm->dev, "no smsm size info, using defaults\n"); smsm->num_entries = SMSM_DEFAULT_NUM_ENTRIES; smsm->num_hosts = SMSM_DEFAULT_NUM_HOSTS; From 452c165e3597691a953e3f4c4c0442c41c8e02f4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:20 +0100 Subject: [PATCH 48/51] soc: qcom: icc-bwmon: Remove unused struct member bwmon->regmap was never used, as the regmap for bwmon is registered through devres and accessed through bwmon's regmap_field members. Remove it Fixes: ec63dcd3c863 ("soc: qcom: icc-bwmon: use regmap and prepare for BWMON v5") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-2-77a050c2fbda@linaro.org --- drivers/soc/qcom/icc-bwmon.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index d07be3700db6..d45caf512e2d 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -164,7 +164,6 @@ struct icc_bwmon { const struct icc_bwmon_data *data; int irq; - struct regmap *regmap; struct regmap_field *regs[F_NUM_FIELDS]; unsigned int max_bw_kbps; From b6e9fb7ac236bc48cc2c667e0b51153d2daa5268 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:21 +0100 Subject: [PATCH 49/51] soc: qcom: icc-bwmon: Handle global registers correctly The BWMON hardware has two sets of registers: one for the monitor itself and one called "global". It has what seems to be some kind of a head switch and an interrupt control register. It's usually 0x200 in size. On fairly recent SoCs (with the starting point seemingly being moving the OSM programming to the firmware) these two register sets are contiguous and overlapping, like this (on sm8450): /* notice how base.start == global_base.start+0x100 */ reg = <0x90b6400 0x300>, <0x90b6300 0x200>; reg-names = "base", "global_base"; Which led to some confusion and the assumption that since the "interesting" global registers begin right after global_base+0x100, there's no need to map two separate regions and one can simply subtract 0x100 from the offsets. This is however not the case for anything older than SDM845, as the global region can appear in seemingly random spots on the register map. Handle the case where the global registers are mapped separately to allow proper functioning of BWMONv4 on MSM8998 and older. Add specific compatibles for 845, 8280xp, 7280 and 8550 (all of which use the single reg space scheme) to keep backwards compatibility with old DTs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-3-77a050c2fbda@linaro.org --- drivers/soc/qcom/icc-bwmon.c | 230 +++++++++++++++++++++++++++++++---- 1 file changed, 209 insertions(+), 21 deletions(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index d45caf512e2d..fd58c5b69897 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -34,14 +34,27 @@ /* Internal sampling clock frequency */ #define HW_TIMER_HZ 19200000 -#define BWMON_V4_GLOBAL_IRQ_CLEAR 0x008 -#define BWMON_V4_GLOBAL_IRQ_ENABLE 0x00c +#define BWMON_V4_GLOBAL_IRQ_CLEAR 0x108 +#define BWMON_V4_GLOBAL_IRQ_ENABLE 0x10c /* * All values here and further are matching regmap fields, so without absolute * register offsets. */ #define BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE BIT(0) +/* + * Starting with SDM845, the BWMON4 register space has changed a bit: + * the global registers were jammed into the beginning of the monitor region. + * To keep the proper offsets, one would have to map and + * , which is straight up wrong. + * To facilitate for that, while allowing the older, arguably more proper + * implementations to work, offset the global registers by -0x100 to avoid + * having to map half of the global registers twice. + */ +#define BWMON_V4_845_OFFSET 0x100 +#define BWMON_V4_GLOBAL_IRQ_CLEAR_845 (BWMON_V4_GLOBAL_IRQ_CLEAR - BWMON_V4_845_OFFSET) +#define BWMON_V4_GLOBAL_IRQ_ENABLE_845 (BWMON_V4_GLOBAL_IRQ_ENABLE - BWMON_V4_845_OFFSET) + #define BWMON_V4_IRQ_STATUS 0x100 #define BWMON_V4_IRQ_CLEAR 0x108 @@ -118,9 +131,13 @@ #define BWMON_NEEDS_FORCE_CLEAR BIT(1) enum bwmon_fields { + /* Global region fields, keep them at the top */ F_GLOBAL_IRQ_CLEAR, F_GLOBAL_IRQ_ENABLE, - F_IRQ_STATUS, + F_NUM_GLOBAL_FIELDS, + + /* Monitor region fields */ + F_IRQ_STATUS = F_NUM_GLOBAL_FIELDS, F_IRQ_CLEAR, F_IRQ_ENABLE, F_ENABLE, @@ -157,6 +174,9 @@ struct icc_bwmon_data { const struct regmap_config *regmap_cfg; const struct reg_field *regmap_fields; + + const struct regmap_config *global_regmap_cfg; + const struct reg_field *global_regmap_fields; }; struct icc_bwmon { @@ -165,6 +185,7 @@ struct icc_bwmon { int irq; struct regmap_field *regs[F_NUM_FIELDS]; + struct regmap_field *global_regs[F_NUM_GLOBAL_FIELDS]; unsigned int max_bw_kbps; unsigned int min_bw_kbps; @@ -174,8 +195,8 @@ struct icc_bwmon { /* BWMON v4 */ static const struct reg_field msm8998_bwmon_reg_fields[] = { - [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0), - [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0), + [F_GLOBAL_IRQ_CLEAR] = {}, + [F_GLOBAL_IRQ_ENABLE] = {}, [F_IRQ_STATUS] = REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7), [F_IRQ_CLEAR] = REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7), [F_IRQ_ENABLE] = REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7), @@ -201,7 +222,6 @@ static const struct reg_field msm8998_bwmon_reg_fields[] = { }; static const struct regmap_range msm8998_bwmon_reg_noread_ranges[] = { - regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR), regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR), regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR), }; @@ -221,16 +241,33 @@ static const struct regmap_access_table msm8998_bwmon_reg_volatile_table = { .n_yes_ranges = ARRAY_SIZE(msm8998_bwmon_reg_volatile_ranges), }; +static const struct reg_field msm8998_bwmon_global_reg_fields[] = { + [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0), + [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0), +}; + +static const struct regmap_range msm8998_bwmon_global_reg_noread_ranges[] = { + regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR), +}; + +static const struct regmap_access_table msm8998_bwmon_global_reg_read_table = { + .no_ranges = msm8998_bwmon_global_reg_noread_ranges, + .n_no_ranges = ARRAY_SIZE(msm8998_bwmon_global_reg_noread_ranges), +}; + /* * Fill the cache for non-readable registers only as rest does not really * matter and can be read from the device. */ static const struct reg_default msm8998_bwmon_reg_defaults[] = { - { BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 }, { BWMON_V4_IRQ_CLEAR, 0x0 }, { BWMON_V4_CLEAR, 0x0 }, }; +static const struct reg_default msm8998_bwmon_global_reg_defaults[] = { + { BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 }, +}; + static const struct regmap_config msm8998_bwmon_regmap_cfg = { .reg_bits = 32, .reg_stride = 4, @@ -251,6 +288,93 @@ static const struct regmap_config msm8998_bwmon_regmap_cfg = { .cache_type = REGCACHE_RBTREE, }; +static const struct regmap_config msm8998_bwmon_global_regmap_cfg = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + /* + * No concurrent access expected - driver has one interrupt handler, + * regmap is not shared, no driver or user-space API. + */ + .disable_locking = true, + .rd_table = &msm8998_bwmon_global_reg_read_table, + .reg_defaults = msm8998_bwmon_global_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(msm8998_bwmon_global_reg_defaults), + /* + * Cache is necessary for using regmap fields with non-readable + * registers. + */ + .cache_type = REGCACHE_RBTREE, +}; + +static const struct reg_field sdm845_cpu_bwmon_reg_fields[] = { + [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR_845, 0, 0), + [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE_845, 0, 0), + [F_IRQ_STATUS] = REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7), + [F_IRQ_CLEAR] = REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7), + [F_IRQ_ENABLE] = REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7), + /* F_ENABLE covers entire register to disable other features */ + [F_ENABLE] = REG_FIELD(BWMON_V4_ENABLE, 0, 31), + [F_CLEAR] = REG_FIELD(BWMON_V4_CLEAR, 0, 1), + [F_SAMPLE_WINDOW] = REG_FIELD(BWMON_V4_SAMPLE_WINDOW, 0, 23), + [F_THRESHOLD_HIGH] = REG_FIELD(BWMON_V4_THRESHOLD_HIGH, 0, 11), + [F_THRESHOLD_MED] = REG_FIELD(BWMON_V4_THRESHOLD_MED, 0, 11), + [F_THRESHOLD_LOW] = REG_FIELD(BWMON_V4_THRESHOLD_LOW, 0, 11), + [F_ZONE_ACTIONS_ZONE0] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 0, 7), + [F_ZONE_ACTIONS_ZONE1] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 8, 15), + [F_ZONE_ACTIONS_ZONE2] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 16, 23), + [F_ZONE_ACTIONS_ZONE3] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 24, 31), + [F_THRESHOLD_COUNT_ZONE0] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 0, 7), + [F_THRESHOLD_COUNT_ZONE1] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 8, 15), + [F_THRESHOLD_COUNT_ZONE2] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 16, 23), + [F_THRESHOLD_COUNT_ZONE3] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 24, 31), + [F_ZONE0_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(0), 0, 11), + [F_ZONE1_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(1), 0, 11), + [F_ZONE2_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(2), 0, 11), + [F_ZONE3_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(3), 0, 11), +}; + +static const struct regmap_range sdm845_cpu_bwmon_reg_noread_ranges[] = { + regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR_845, BWMON_V4_GLOBAL_IRQ_CLEAR_845), + regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR), + regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR), +}; + +static const struct regmap_access_table sdm845_cpu_bwmon_reg_read_table = { + .no_ranges = sdm845_cpu_bwmon_reg_noread_ranges, + .n_no_ranges = ARRAY_SIZE(sdm845_cpu_bwmon_reg_noread_ranges), +}; + +/* + * Fill the cache for non-readable registers only as rest does not really + * matter and can be read from the device. + */ +static const struct reg_default sdm845_cpu_bwmon_reg_defaults[] = { + { BWMON_V4_GLOBAL_IRQ_CLEAR_845, 0x0 }, + { BWMON_V4_IRQ_CLEAR, 0x0 }, + { BWMON_V4_CLEAR, 0x0 }, +}; + +static const struct regmap_config sdm845_cpu_bwmon_regmap_cfg = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + /* + * No concurrent access expected - driver has one interrupt handler, + * regmap is not shared, no driver or user-space API. + */ + .disable_locking = true, + .rd_table = &sdm845_cpu_bwmon_reg_read_table, + .volatile_table = &msm8998_bwmon_reg_volatile_table, + .reg_defaults = sdm845_cpu_bwmon_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(sdm845_cpu_bwmon_reg_defaults), + /* + * Cache is necessary for using regmap fields with non-readable + * registers. + */ + .cache_type = REGCACHE_RBTREE, +}; + /* BWMON v5 */ static const struct reg_field sdm845_llcc_bwmon_reg_fields[] = { [F_GLOBAL_IRQ_CLEAR] = {}, @@ -349,6 +473,13 @@ static void bwmon_clear_counters(struct icc_bwmon *bwmon, bool clear_all) static void bwmon_clear_irq(struct icc_bwmon *bwmon) { + struct regmap_field *global_irq_clr; + + if (bwmon->data->global_regmap_fields) + global_irq_clr = bwmon->global_regs[F_GLOBAL_IRQ_CLEAR]; + else + global_irq_clr = bwmon->regs[F_GLOBAL_IRQ_CLEAR]; + /* * Clear zone and global interrupts. The order and barriers are * important. Quoting downstream Qualcomm msm-4.9 tree: @@ -369,15 +500,22 @@ static void bwmon_clear_irq(struct icc_bwmon *bwmon) if (bwmon->data->quirks & BWMON_NEEDS_FORCE_CLEAR) regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], 0); if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_force_write(bwmon->regs[F_GLOBAL_IRQ_CLEAR], + regmap_field_force_write(global_irq_clr, BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); } static void bwmon_disable(struct icc_bwmon *bwmon) { + struct regmap_field *global_irq_en; + + if (bwmon->data->global_regmap_fields) + global_irq_en = bwmon->global_regs[F_GLOBAL_IRQ_ENABLE]; + else + global_irq_en = bwmon->regs[F_GLOBAL_IRQ_ENABLE]; + /* Disable interrupts. Strict ordering, see bwmon_clear_irq(). */ if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], 0x0); + regmap_field_write(global_irq_en, 0x0); regmap_field_write(bwmon->regs[F_IRQ_ENABLE], 0x0); /* @@ -389,10 +527,18 @@ static void bwmon_disable(struct icc_bwmon *bwmon) static void bwmon_enable(struct icc_bwmon *bwmon, unsigned int irq_enable) { + struct regmap_field *global_irq_en; + + if (bwmon->data->global_regmap_fields) + global_irq_en = bwmon->global_regs[F_GLOBAL_IRQ_ENABLE]; + else + global_irq_en = bwmon->regs[F_GLOBAL_IRQ_ENABLE]; + /* Enable interrupts */ if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], + regmap_field_write(global_irq_en, BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); + regmap_field_write(bwmon->regs[F_IRQ_ENABLE], irq_enable); /* Enable bwmon */ @@ -555,7 +701,9 @@ static int bwmon_init_regmap(struct platform_device *pdev, struct device *dev = &pdev->dev; void __iomem *base; struct regmap *map; + int ret; + /* Map the monitor base */ base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return dev_err_probe(dev, PTR_ERR(base), @@ -566,12 +714,35 @@ static int bwmon_init_regmap(struct platform_device *pdev, return dev_err_probe(dev, PTR_ERR(map), "failed to initialize regmap\n"); + BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_global_reg_fields) != F_NUM_GLOBAL_FIELDS); BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_reg_fields) != F_NUM_FIELDS); + BUILD_BUG_ON(ARRAY_SIZE(sdm845_cpu_bwmon_reg_fields) != F_NUM_FIELDS); BUILD_BUG_ON(ARRAY_SIZE(sdm845_llcc_bwmon_reg_fields) != F_NUM_FIELDS); - return devm_regmap_field_bulk_alloc(dev, map, bwmon->regs, + ret = devm_regmap_field_bulk_alloc(dev, map, bwmon->regs, bwmon->data->regmap_fields, F_NUM_FIELDS); + if (ret) + return ret; + + if (bwmon->data->global_regmap_cfg) { + /* Map the global base, if separate */ + base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "failed to map bwmon global registers\n"); + + map = devm_regmap_init_mmio(dev, base, bwmon->data->global_regmap_cfg); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), + "failed to initialize global regmap\n"); + + ret = devm_regmap_field_bulk_alloc(dev, map, bwmon->global_regs, + bwmon->data->global_regmap_fields, + F_NUM_GLOBAL_FIELDS); + } + + return ret; } static int bwmon_probe(struct platform_device *pdev) @@ -644,6 +815,21 @@ static const struct icc_bwmon_data msm8998_bwmon_data = { .quirks = BWMON_HAS_GLOBAL_IRQ, .regmap_fields = msm8998_bwmon_reg_fields, .regmap_cfg = &msm8998_bwmon_regmap_cfg, + .global_regmap_fields = msm8998_bwmon_global_reg_fields, + .global_regmap_cfg = &msm8998_bwmon_global_regmap_cfg, +}; + +static const struct icc_bwmon_data sdm845_cpu_bwmon_data = { + .sample_ms = 4, + .count_unit_kb = 64, + .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */ + .default_medbw_kbps = 512 * 1024, /* 512 MBps */ + .default_lowbw_kbps = 0, + .zone1_thres_count = 16, + .zone3_thres_count = 1, + .quirks = BWMON_HAS_GLOBAL_IRQ, + .regmap_fields = sdm845_cpu_bwmon_reg_fields, + .regmap_cfg = &sdm845_cpu_bwmon_regmap_cfg, }; static const struct icc_bwmon_data sdm845_llcc_bwmon_data = { @@ -672,16 +858,18 @@ static const struct icc_bwmon_data sc7280_llcc_bwmon_data = { }; static const struct of_device_id bwmon_of_match[] = { - { - .compatible = "qcom,msm8998-bwmon", - .data = &msm8998_bwmon_data - }, { - .compatible = "qcom,sdm845-llcc-bwmon", - .data = &sdm845_llcc_bwmon_data - }, { - .compatible = "qcom,sc7280-llcc-bwmon", - .data = &sc7280_llcc_bwmon_data - }, + /* BWMONv4, separate monitor and global register spaces */ + { .compatible = "qcom,msm8998-bwmon", .data = &msm8998_bwmon_data }, + /* BWMONv4, unified register space */ + { .compatible = "qcom,sdm845-bwmon", .data = &sdm845_cpu_bwmon_data }, + /* BWMONv5 */ + { .compatible = "qcom,sdm845-llcc-bwmon", .data = &sdm845_llcc_bwmon_data }, + { .compatible = "qcom,sc7280-llcc-bwmon", .data = &sc7280_llcc_bwmon_data }, + + /* Compatibles kept for legacy reasons */ + { .compatible = "qcom,sc7280-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, + { .compatible = "qcom,sc8280xp-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, + { .compatible = "qcom,sm8550-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, {} }; MODULE_DEVICE_TABLE(of, bwmon_of_match); From df90ded69043400c01c552d672f198a99bd531e6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:52 +0100 Subject: [PATCH 50/51] dt-bindings: sram: qcom,imem: document SM6375 IMEM Add a compatible for SM6375 IMEM. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-3-708b8191f7eb@linaro.org --- Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index ba694ce4a037..0548e8e0d30b 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm845-imem - qcom,sdx55-imem - qcom,sdx65-imem + - qcom,sm6375-imem - qcom,sm8450-imem - const: syscon - const: simple-mfd From c78ad8597ed961e822bf86ce7f1916dbfba255ef Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Sat, 25 Mar 2023 17:54:33 +0530 Subject: [PATCH 51/51] dt-bindings: firmware: document Qualcomm SC8180X SCM Document the compatible for Qualcomm sc8180x SCM. Acked-by: Krzysztof Kozlowski Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230325122444.249507-2-vkoul@kernel.org --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 543feb3b6c58..c3851b13cd5a 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -44,6 +44,7 @@ properties: - qcom,scm-sa8775p - qcom,scm-sc7180 - qcom,scm-sc7280 + - qcom,scm-sc8180x - qcom,scm-sc8280xp - qcom,scm-sdm670 - qcom,scm-sdm845