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Merge branch 'net-dsa-yt921x-add-acl-support'
David Yang says: ==================== net: dsa: yt921x: Add ACL support ==================== Link: https://patch.msgid.link/20260606130011.307812-1-mmyangfl@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
1225253dc5
File diff suppressed because it is too large
Load Diff
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@ -24,6 +24,7 @@
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#define YT921X_RST_SW BIT(1)
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#define YT921X_FUNC 0x80004
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#define YT921X_FUNC_METER BIT(4)
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#define YT921X_FUNC_ACL BIT(2)
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#define YT921X_FUNC_MIB BIT(1)
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#define YT921X_CHIP_ID 0x80008
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#define YT921X_CHIP_ID_MAJOR GENMASK(31, 16)
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@ -420,6 +421,10 @@ enum yt921x_app_selector {
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#define YT921X_CPU_COPY_FORCE_INT_PORT BIT(2)
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#define YT921X_CPU_COPY_TO_INT_CPU BIT(1)
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#define YT921X_CPU_COPY_TO_EXT_CPU BIT(0)
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#define YT921X_ACL_PERMIT_UNMATCH 0x1806a0
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#define YT921X_ACL_PERMIT_UNMATCH_PORTS_M GENMASK(10, 0)
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#define YT921X_ACL_PERMIT_UNMATCH_PORTS(x) FIELD_PREP(YT921X_ACL_PERMIT_UNMATCH_PORTS_M, (x))
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#define YT921X_ACL_PERMIT_UNMATCH_PORTn(port) BIT(port)
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#define YT921X_ACT_UNK_UCAST 0x180734
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#define YT921X_ACT_UNK_MCAST 0x180738
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#define YT921X_ACT_UNK_MCAST_BYPASS_DROP_RMA BIT(23)
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@ -454,6 +459,249 @@ enum yt921x_app_selector {
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#define YT921X_VLAN_CTRLa_METER_EN BIT(5)
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#define YT921X_VLAN_CTRLa_METER_ID_M GENMASK(4, 0)
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#define YT921X_ACLn_ACT(n) (0x1c0000 + 0x10 * (n))
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#define YT921X_ACL_ACTc_STAG_M GENMASK(26, 25)
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#define YT921X_ACL_ACTc_STAG(x) FIELD_PREP(YT921X_ACL_ACTc_STAG_M, (x))
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#define YT921X_ACL_ACTc_STAG_DONTCARE YT921X_ACL_ACTc_STAG(0)
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#define YT921X_ACL_ACTc_STAG_UNTAG YT921X_ACL_ACTc_STAG(1)
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#define YT921X_ACL_ACTc_STAG_TAG YT921X_ACL_ACTc_STAG(2)
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#define YT921X_ACL_ACTc_STAG_KEEP YT921X_ACL_ACTc_STAG(3)
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#define YT921X_ACL_ACTc_CTAG_M GENMASK(24, 23)
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#define YT921X_ACL_ACTc_CTAG(x) FIELD_PREP(YT921X_ACL_ACTc_CTAG_M, (x))
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#define YT921X_ACL_ACTc_CTAG_DONTCARE YT921X_ACL_ACTc_CTAG(0)
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#define YT921X_ACL_ACTc_CTAG_UNTAG YT921X_ACL_ACTc_CTAG(1)
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#define YT921X_ACL_ACTc_CTAG_TAG YT921X_ACL_ACTc_CTAG(2)
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#define YT921X_ACL_ACTc_CTAG_KEEP YT921X_ACL_ACTc_CTAG(3)
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#define YT921X_ACL_ACTc_FWD_M GENMASK(22, 21)
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#define YT921X_ACL_ACTc_FWD(x) FIELD_PREP(YT921X_ACL_ACTc_FWD_M, (x))
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#define YT921X_ACL_ACTc_FWD_FWD YT921X_ACL_ACTc_FWD(0)
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#define YT921X_ACL_ACTc_FWD_COPY YT921X_ACL_ACTc_FWD(1)
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#define YT921X_ACL_ACTc_FWD_REDIR YT921X_ACL_ACTc_FWD(2)
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#define YT921X_ACL_ACTc_FWD_TRAP YT921X_ACL_ACTc_FWD(3)
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#define YT921X_ACL_ACTc_FWD_REDIR_DPORTS_M GENMASK(20, 10)
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#define YT921X_ACL_ACTc_FWD_REDIR_DPORTS(x) FIELD_PREP(YT921X_ACL_ACTc_FWD_REDIR_DPORTS_M, (x))
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#define YT921X_ACL_ACTc_FWD_REDIR_DPORTn(port) BIT((port) + 10)
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#define YT921X_ACL_ACTc_FWD_EN BIT(9)
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#define YT921X_ACL_ACTc_SDEI BIT(8)
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#define YT921X_ACL_ACTc_SDEI_REPLACE BIT(7)
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#define YT921X_ACL_ACTc_SPRI_M GENMASK(6, 4)
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#define YT921X_ACL_ACTc_SPRI(x) FIELD_PREP(YT921X_ACL_ACTc_SPRI_M, (x))
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#define YT921X_ACL_ACTc_SPRI_REPLACE BIT(3)
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#define YT921X_ACL_ACTbc_SVID_M GENMASK_ULL(34, 23)
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#define YT921X_ACL_ACTbc_SVID(x) FIELD_PREP(YT921X_ACL_ACTbc_SVID_M, (x))
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#define YT921X_ACL_ACTb_SVID_REPLACE BIT(22)
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#define YT921X_ACL_ACTb_CDEI BIT(21)
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#define YT921X_ACL_ACTb_CDEI_REPLACE BIT(20)
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#define YT921X_ACL_ACTb_CPRI_M GENMASK(19, 17)
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#define YT921X_ACL_ACTb_CPRI(x) FIELD_PREP(YT921X_ACL_ACTb_CPRI_M, (x))
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#define YT921X_ACL_ACTb_CPRI_REPLACE BIT(16)
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#define YT921X_ACL_ACTb_CVID_M GENMASK(15, 4)
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#define YT921X_ACL_ACTb_CVID(x) FIELD_PREP(YT921X_ACL_ACTb_CVID_M, (x))
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#define YT921X_ACL_ACTb_CVID_REPLACE BIT(3)
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#define YT921X_ACL_ACTb_PRIO_M GENMASK(2, 0)
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#define YT921X_ACL_ACTb_PRIO(x) FIELD_PREP(YT921X_ACL_ACTb_PRIO_M, (x))
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#define YT921X_ACL_ACTa_PRIO_EN BIT(31)
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#define YT921X_ACL_ACTa_COLOR_M GENMASK(30, 29)
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#define YT921X_ACL_ACTa_COLOR(x) FIELD_PREP(YT921X_ACL_ACTa_COLOR_M, (x))
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#define YT921X_ACL_ACTa_COLOR_GREEN YT921X_ACL_ACTa_COLOR(0)
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#define YT921X_ACL_ACTa_COLOR_YELLOW YT921X_ACL_ACTa_COLOR(1)
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#define YT921X_ACL_ACTa_COLOR_RED YT921X_ACL_ACTa_COLOR(2)
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#define YT921X_ACL_ACTa_COLOR_EN BIT(28)
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#define YT921X_ACL_ACTa_DSCP_M GENMASK(27, 22)
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#define YT921X_ACL_ACTa_DSCP(x) FIELD_PREP(YT921X_ACL_ACTa_DSCP_M, (x))
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#define YT921X_ACL_ACTa_DSCP_REPLACE BIT(21)
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#define YT921X_ACL_ACTa_METER_ID_M GENMASK(20, 15)
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#define YT921X_ACL_ACTa_METER_ID(x) FIELD_PREP(YT921X_ACL_ACTa_METER_ID_M, (x))
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#define YT921X_ACL_ACTa_METER_EN BIT(14)
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#define YT921X_ACL_ACTa_MIRROR_EN BIT(13)
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#define YT921X_ACL_ACTa_FLOWSTAT_EN BIT(12)
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#define YT921X_ACL_ACTa_FLOWSTAT_ID_M GENMASK(11, 6)
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#define YT921X_ACL_ACTa_FLOWSTAT_ID(x) FIELD_PREP(YT921X_ACL_ACTa_FLOWSTAT_ID_M, (x))
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#define YT921X_ACL_ACTa_GPIO_EN BIT(5)
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#define YT921X_ACL_ACTa_GPIO_PIN_M GENMASK(4, 1)
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#define YT921X_ACL_ACTa_GPIO_PIN(x) FIELD_PREP(YT921X_ACL_ACTa_GPIO_PIN_M, (x))
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#define YT921X_ACL_ACTa_INTR_EN BIT(0)
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#define YT921X_ACL_BLK_KEEP 0x201000
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#define YT921X_ACL_BLK_KEEP_GRPIDn_M(bin) (7 << (4 * (bin) + 1))
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#define YT921X_ACL_BLK_KEEP_GRPIDn(bin, x) ((x) << (4 * (bin) + 1))
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#define YT921X_ACL_BLK_KEEP_KEEPn(bin) BIT(4 * (bin))
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#define YT921X_ACL_PORT 0x202000
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#define YT921X_ACL_PORT_PORTS_M GENMASK(10, 0)
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#define YT921X_ACL_PORT_PORTS(x) FIELD_PREP(YT921X_ACL_PORT_PORTS_M, (x))
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#define YT921X_ACL_PORT_PORTn(port) BIT(port)
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#define YT921X_ACL_BLK_CMD 0x202004
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#define YT921X_ACL_BLK_CMD_BLKID_M GENMASK(6, 1)
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#define YT921X_ACL_BLK_CMD_BLKID(x) FIELD_PREP(YT921X_ACL_BLK_CMD_BLKID_M, (x))
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#define YT921X_ACL_BLK_CMD_MODIFY BIT(0)
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#define YT921X_ACLn_ENTRY(blk) (0x203000 + 4 * (blk))
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#define YT921X_ACL_ENTRY_GRPIDm_M(bin) (7 << (4 * (bin) + 1))
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#define YT921X_ACL_ENTRY_GRPIDm(bin, x) ((x) << (4 * (bin) + 1))
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#define YT921X_ACL_ENTRY_ENm(bin) BIT(4 * (bin))
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#define YT921X_ACLn_KEYm(blk, bin) (0x204000 + 0x200 * (bin) + 8 * (blk))
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#define YT921X_ACL_KEYb_ORD_M GENMASK(29, 21)
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#define YT921X_ACL_KEYb_ORD(x) FIELD_PREP(YT921X_ACL_KEYb_ORD_M, (x))
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#define YT921X_ACL_KEYb_SPORTS_M GENMASK(20, 10)
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#define YT921X_ACL_KEYb_SPORTS(x) FIELD_PREP(YT921X_ACL_KEYb_SPORTS_M, (x))
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#define YT921X_ACL_KEYb_SPORTn(port) BIT((port) + 10)
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#define YT921X_ACL_KEYb_REVERSE BIT(9) /* reverse match */
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#define YT921X_ACL_KEYb_TYPE_M GENMASK(8, 4)
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#define YT921X_ACL_KEYb_TYPE(x) FIELD_PREP(YT921X_ACL_KEYb_TYPE_M, (x))
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/* KEY_* fields need no masks */
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#define YT921X_ACLn_MASKm(blk, bin) (0x205000 + 0x200 * (bin) + 8 * (blk))
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enum yt921x_acl_type {
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YT921X_ACL_TYPE_NA,
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YT921X_ACL_TYPE_MAC_DA0,
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YT921X_ACL_TYPE_MAC_SA0,
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YT921X_ACL_TYPE_MAC_DA1_SA1,
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YT921X_ACL_TYPE_VLAN,
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YT921X_ACL_TYPE_VTAG,
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YT921X_ACL_TYPE_IPV4_DA,
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YT921X_ACL_TYPE_IPV4_SA,
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YT921X_ACL_TYPE_IPV6_DA0,
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YT921X_ACL_TYPE_IPV6_DA1,
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YT921X_ACL_TYPE_IPV6_DA2,
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YT921X_ACL_TYPE_IPV6_DA3,
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YT921X_ACL_TYPE_IPV6_SA0,
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YT921X_ACL_TYPE_IPV6_SA1,
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YT921X_ACL_TYPE_IPV6_SA2,
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YT921X_ACL_TYPE_IPV6_SA3,
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YT921X_ACL_TYPE_MISC,
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YT921X_ACL_TYPE_L4,
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YT921X_ACL_TYPE_UDF0,
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YT921X_ACL_TYPE_UDF1,
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YT921X_ACL_TYPE_UDF2,
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YT921X_ACL_TYPE_UDF3,
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YT921X_ACL_TYPE_UDF4,
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YT921X_ACL_TYPE_UDF5,
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YT921X_ACL_TYPE_UDF6,
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YT921X_ACL_TYPE_UDF7,
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YT921X_ACL_TYPE_ETHERTYPE,
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YT921X_ACL_TYPE_NUM
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};
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/* Range: turn KEY:MASK into MIN:MAX */
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#define YT921X_ACL_BINb_MAC_xA0_L3_TYPE_M GENMASK(3, 0)
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#define YT921X_ACL_BINb_MAC_xA0_L3_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MAC_xA0_L3_TYPE_M, (x))
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#define YT921X_ACL_BINa_MAC_xA0_MAC_xA0_M GENMASK(31, 0)
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#define YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE_M GENMASK(2, 0)
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#define YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE_M, (x))
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#define YT921X_ACL_BINa_MAC_DA1_SA1_MAC_DA1_M GENMASK(31, 16)
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#define YT921X_ACL_BINa_MAC_DA1_SA1_MAC_SA1_M GENMASK(15, 0)
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#define YT921X_ACL_KEYb_VLAN_SVID_RANGE_EN BIT(31)
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#define YT921X_ACL_KEYb_VLAN_CVID_RANGE_EN BIT(30)
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#define YT921X_ACL_BINb_VLAN_CDEI BIT(3)
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#define YT921X_ACL_BINb_VLAN_CPRI_M GENMASK(2, 0)
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#define YT921X_ACL_BINb_VLAN_CPRI(x) FIELD_PREP(YT921X_ACL_BINb_VLAN_CPRI_M, (x))
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#define YT921X_ACL_BINa_VLAN_CTAG_FMT_M GENMASK(31, 30)
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#define YT921X_ACL_BINa_VLAN_CTAG_FMT(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_CTAG_FMT_M, (x))
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#define YT921X_ACL_BINa_VLAN_SDEI BIT(29)
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#define YT921X_ACL_BINa_VLAN_SPRI_M GENMASK(28, 26)
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#define YT921X_ACL_BINa_VLAN_SPRI(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_SPRI_M, (x))
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#define YT921X_ACL_BINa_VLAN_STAG_FMT_M GENMASK(25, 24)
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#define YT921X_ACL_BINa_VLAN_STAG_FMT(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_STAG_FMT_M, (x))
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#define YT921X_ACL_BINa_VLAN_SVID_M GENMASK(23, 12)
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#define YT921X_ACL_BINa_VLAN_SVID(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_SVID_M, (x))
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#define YT921X_ACL_BINa_VLAN_CVID_M GENMASK(11, 0)
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#define YT921X_ACL_BINa_VLAN_CVID(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_CVID_M, (x))
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#define YT921X_ACL_KEYb_VTAG_SVID_RANGE_EN BIT(31)
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#define YT921X_ACL_KEYb_VTAG_CVID_RANGE_EN BIT(30)
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#define YT921X_ACL_BINa_VTAG_CDEI BIT(31)
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#define YT921X_ACL_BINa_VTAG_CPRI_M GENMASK(30, 28)
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#define YT921X_ACL_BINa_VTAG_CPRI(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_CPRI_M, (x))
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#define YT921X_ACL_BINa_VTAG_SDEI BIT(27)
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#define YT921X_ACL_BINa_VTAG_SPRI_M GENMASK(26, 24)
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#define YT921X_ACL_BINa_VTAG_SPRI(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_SPRI_M, (x))
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#define YT921X_ACL_BINa_VTAG_SVID_M GENMASK(23, 12)
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#define YT921X_ACL_BINa_VTAG_SVID(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_SVID_M, (x))
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#define YT921X_ACL_BINa_VTAG_CVID_M GENMASK(11, 0)
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#define YT921X_ACL_BINa_VTAG_CVID(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_CVID_M, (x))
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#define YT921X_ACL_KEYb_IPV4_ADDR_RANGE_EN BIT(30)
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#define YT921X_ACL_BINb_IPV4_FRAG BIT(3)
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#define YT921X_ACL_BINb_IPV4_L4_TYPE_M GENMASK(2, 0)
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#define YT921X_ACL_BINb_IPV4_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_IPV4_L4_TYPE_M, (x))
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#define YT921X_ACL_BINa_IPV4_ADDR_M GENMASK(31, 0)
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#define YT921X_ACL_BINb_IPV6_L4_TYPE_M GENMASK(2, 0)
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#define YT921X_ACL_BINb_IPV6_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_IPV6_L4_TYPE_M, (x))
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#define YT921X_ACL_BINa_IPV6_ADDRx_M GENMASK(31, 0)
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#define YT921X_ACL_BINb_IPV6_xA1_IP_OPTION BIT(3)
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#define YT921X_ACL_BINb_IPV6_xA2_FIRST_FRAG BIT(3)
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#define YT921X_ACL_KEYb_IPV6_xA3_ADDR_RANGE_EN BIT(30)
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#define YT921X_ACL_BINb_IPV6_xA3_FRAG BIT(3)
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#define YT921X_ACL_BINb_MISC_FRAG BIT(3)
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#define YT921X_ACL_BINb_MISC_L4_TYPE_M GENMASK(2, 0)
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#define YT921X_ACL_BINb_MISC_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MISC_L4_TYPE_M, (x))
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#define YT921X_ACL_BINa_MISC_PPPOE_FLAG BIT(30)
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#define YT921X_ACL_BINa_MISC_FIRST_FRAG BIT(29)
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#define YT921X_ACL_BINa_MISC_IP_OPTION BIT(28)
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#define YT921X_ACL_BINa_MISC_TCP_FLAGS_M GENMASK(27, 20)
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#define YT921X_ACL_BINa_MISC_TCP_FLAGS(x) FIELD_PREP(YT921X_ACL_BINa_MISC_TCP_FLAGS_M, (x))
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#define YT921X_ACL_BINa_MISC_IP_PROTO_M GENMASK(19, 12)
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#define YT921X_ACL_BINa_MISC_IP_PROTO(x) FIELD_PREP(YT921X_ACL_BINa_MISC_IP_PROTO_M, (x))
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#define YT921X_ACL_BINa_MISC_TOS_M GENMASK(11, 4)
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#define YT921X_ACL_BINa_MISC_TOS(x) FIELD_PREP(YT921X_ACL_BINa_MISC_TOS_M, (x))
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#define YT921X_ACL_BINa_MISC_L3_TYPE_M GENMASK(3, 0)
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#define YT921X_ACL_BINa_MISC_L3_TYPE(x) FIELD_PREP(YT921X_ACL_BINa_MISC_L3_TYPE_M, (x))
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#define YT921X_ACL_KEYb_L4_DPORT_RANGE_EN BIT(31)
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#define YT921X_ACL_KEYb_L4_SPORT_RANGE_EN BIT(30)
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#define YT921X_ACL_BINb_L4_FRAG BIT(3)
|
||||
#define YT921X_ACL_BINb_L4_TYPE_M GENMASK(2, 0)
|
||||
#define YT921X_ACL_BINb_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_L4_TYPE_M, (x))
|
||||
#define YT921X_ACL_BINa_L4_DPORT_M GENMASK(31, 16)
|
||||
#define YT921X_ACL_BINa_L4_SPORT_M GENMASK(15, 0)
|
||||
|
||||
#define YT921X_ACL_BINb_UDF_IS_IGMP BIT(0)
|
||||
#define YT921X_ACL_BINa_UDF_UDF0_M GENMASK(31, 16)
|
||||
#define YT921X_ACL_BINa_UDF_UDF0(x) FIELD_PREP(YT921X_ACL_BINa_UDF_UDF0_M, (x))
|
||||
#define YT921X_ACL_BINa_UDF_UDF1_M GENMASK(15, 0)
|
||||
#define YT921X_ACL_BINa_UDF_UDF1(x) FIELD_PREP(YT921X_ACL_BINa_UDF_UDF1_M, (x))
|
||||
|
||||
#define YT921X_ACL_KEYb_ETHERTYPE_ETHERTYPE_RANGE_EN BIT(30)
|
||||
#define YT921X_ACL_BINb_ETHERTYPE_L4_TYPE_M GENMASK(2, 0)
|
||||
#define YT921X_ACL_BINb_ETHERTYPE_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_ETHERTYPE_L4_TYPE_M, (x))
|
||||
#define YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE_M GENMASK(15, 0)
|
||||
#define YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE(x) FIELD_PREP(YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE_M, (x))
|
||||
|
||||
enum yt921x_l2_type {
|
||||
YT921X_L2_TYPE_ETH,
|
||||
YT921X_L2_TYPE_ETHV2,
|
||||
YT921X_L2_TYPE_ETHSAP,
|
||||
YT921X_L2_TYPE_ETHSNAP,
|
||||
};
|
||||
|
||||
enum yt921x_l3_type {
|
||||
YT921X_L3_TYPE_OTHER,
|
||||
YT921X_L3_TYPE_IPV4,
|
||||
YT921X_L3_TYPE_IPV6,
|
||||
YT921X_L3_TYPE_ARP,
|
||||
YT921X_L3_TYPE_LLDP,
|
||||
YT921X_L3_TYPE_PAE,
|
||||
YT921X_L3_TYPE_ERP,
|
||||
YT921X_L3_TYPE_SLOW_PROTOCOL,
|
||||
};
|
||||
|
||||
enum yt921x_l4_type {
|
||||
YT921X_L4_TYPE_OTHER,
|
||||
YT921X_L4_TYPE_TCP,
|
||||
YT921X_L4_TYPE_UDP,
|
||||
YT921X_L4_TYPE_UDPLITE,
|
||||
YT921X_L4_TYPE_ICMP,
|
||||
YT921X_L4_TYPE_IGMP,
|
||||
YT921X_L4_TYPE_MLD,
|
||||
YT921X_L4_TYPE_ND,
|
||||
};
|
||||
|
||||
#define YT921X_TPID_IGRn(x) (0x210000 + 4 * (x)) /* [0, 3] */
|
||||
#define YT921X_TPID_IGR_TPID_M GENMASK(15, 0)
|
||||
#define YT921X_PORTn_IGR_TPID(port) (0x210010 + 4 * (port))
|
||||
|
|
@ -470,6 +718,14 @@ enum yt921x_app_selector {
|
|||
#define YT921X_LAG_HASH_MAC_SA BIT(2)
|
||||
#define YT921X_LAG_HASH_MAC_DA BIT(1)
|
||||
#define YT921X_LAG_HASH_SRC_PORT BIT(0)
|
||||
#define YT921X_UDFn_CTRL(x) (0x210094 + 4 * (x))
|
||||
#define YT921X_UDF_CTRL_UDF_TYPE_M GENMASK(8, 7)
|
||||
#define YT921X_UDF_CTRL_UDF_TYPE(x) FIELD_PREP(YT921X_UDF_CTRL_UDF_TYPE_M, (x))
|
||||
#define YT921X_UDF_CTRL_UDF_TYPE_ETH YT921X_UDF_CTRL_UDF_TYPE(0)
|
||||
#define YT921X_UDF_CTRL_UDF_TYPE_L3 YT921X_UDF_CTRL_UDF_TYPE(1)
|
||||
#define YT921X_UDF_CTRL_UDF_TYPE_L4 YT921X_UDF_CTRL_UDF_TYPE(2)
|
||||
#define YT921X_UDF_CTRL_UDF_OFFSET_M GENMASK(6, 0)
|
||||
#define YT921X_UDF_CTRL_UDF_OFFSET(x) FIELD_PREP(YT921X_UDF_CTRL_UDF_OFFSET_M, (x))
|
||||
|
||||
#define YT921X_PORTn_RATE(port) (0x220000 + 4 * (port))
|
||||
#define YT921X_PORT_RATE_GAP_VALUE GENMASK(4, 0) /* default 20 */
|
||||
|
|
@ -589,6 +845,11 @@ enum yt921x_fdb_entry_status {
|
|||
|
||||
#define YT921X_TAG_LEN 8
|
||||
|
||||
#define YT921X_ACL_BLK_NUM 48
|
||||
#define YT921X_ACL_ENT_PER_BLK 8
|
||||
#define YT921X_ACL_NUM (YT921X_ACL_BLK_NUM * YT921X_ACL_ENT_PER_BLK)
|
||||
#define YT921X_UDF_NUM 8
|
||||
|
||||
/* 8 internal + 2 external + 1 mcu */
|
||||
#define YT921X_PORT_NUM 11
|
||||
|
||||
|
|
@ -647,6 +908,26 @@ struct yt921x_mib {
|
|||
u64 tx_oam;
|
||||
};
|
||||
|
||||
struct yt921x_acl_entry {
|
||||
u32 key[2];
|
||||
u32 mask[2];
|
||||
};
|
||||
|
||||
struct yt921x_acl_rule {
|
||||
unsigned long tag;
|
||||
enum tc_setup_type type;
|
||||
|
||||
u32 action[3];
|
||||
bool sw_assisted;
|
||||
|
||||
u8 mask;
|
||||
struct yt921x_acl_entry entries[YT921X_ACL_ENT_PER_BLK];
|
||||
};
|
||||
|
||||
struct yt921x_acl_blk {
|
||||
struct yt921x_acl_rule *rules[YT921X_ACL_ENT_PER_BLK];
|
||||
};
|
||||
|
||||
struct yt921x_port {
|
||||
unsigned char index;
|
||||
|
||||
|
|
@ -686,6 +967,11 @@ struct yt921x_priv {
|
|||
struct yt921x_port ports[YT921X_PORT_NUM];
|
||||
|
||||
u16 eee_ports_mask;
|
||||
|
||||
DECLARE_BITMAP(meters_map, YT921X_METER_NUM);
|
||||
|
||||
u8 acl_masks[YT921X_ACL_BLK_NUM];
|
||||
struct yt921x_acl_blk *acl_blks[YT921X_ACL_BLK_NUM];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
*/
|
||||
enum yt921x_tag_code {
|
||||
YT921X_TAG_CODE_FORWARD = 0,
|
||||
YT921X_TAG_CODE_ACL = 0x17,
|
||||
YT921X_TAG_CODE_UNK_UCAST = 0x19,
|
||||
YT921X_TAG_CODE_UNK_MCAST = 0x1a,
|
||||
YT921X_TAG_CODE_PORT_COPY = 0x1b,
|
||||
|
|
@ -129,6 +130,7 @@ yt921x_tag_rcv(struct sk_buff *skb, struct net_device *netdev)
|
|||
/* Already forwarded by hardware */
|
||||
dsa_default_offload_fwd_mark(skb);
|
||||
break;
|
||||
case YT921X_TAG_CODE_ACL:
|
||||
case YT921X_TAG_CODE_UNK_UCAST:
|
||||
case YT921X_TAG_CODE_UNK_MCAST:
|
||||
/* NOTE: hardware doesn't distinguish between TRAP (copy
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user