From 120e4243625690ee8bd3d6a8a6e2eac4269ba40d Mon Sep 17 00:00:00 2001 From: Jing Zhou Date: Thu, 16 Apr 2026 13:47:52 +0800 Subject: [PATCH] drm/amd/display: fix root clock disabled when DSC power gate disabled for DCN314 [Why] When set debug.disable_dsc_power_gate = true, the original code uses an early return to skip the power gate sequence and root clock enable and disable. For this case, install new driver without uninstall old driver. The sequence like below: 1. On the power-off path, the old driver will power gate dsc and disable_dsc() (root clock disable) due to debug.disable_dsc_power_gate = false. 2. On the power-on path, the new driver will force power on dsc but skip enable_dsc() (root clock enable) due to debug.disable_dsc_power_gate = true. Finally, when mode needs DSC but the root clock is disabled, underflow happened. [How] - Moving enable_dsc() before the disable_dsc_power_gate check so the root clock is always enabled on the power-on path. - Replacing the early return with a goto that skips only the power gate register writes, allowing disable_dsc() to still execute on the power-off path. Reviewed-by: Aric Cyr Signed-off-by: Jing Zhou Signed-off-by: Tom Chung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 82 +++++++++---------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 1e856ee508f1..408d417318c2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -232,60 +232,60 @@ void dcn314_dsc_pg_control( uint32_t pwr_status = power_on ? 0 : 2; uint32_t org_ip_request_cntl = 0; - if (hws->ctx->dc->debug.disable_dsc_power_gate) - return; - if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( hws->ctx->dc->res_pool->dccg, dsc_inst); - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + if (!hws->ctx->dc->debug.disable_dsc_power_gate) { - switch (dsc_inst) { - case 0: /* DSC0 */ - REG_UPDATE(DOMAIN16_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); - REG_WAIT(DOMAIN16_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 1: /* DSC1 */ - REG_UPDATE(DOMAIN17_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + switch (dsc_inst) { + case 0: /* DSC0 */ + REG_UPDATE(DOMAIN16_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN17_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 2: /* DSC2 */ - REG_UPDATE(DOMAIN18_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN16_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 1: /* DSC1 */ + REG_UPDATE(DOMAIN17_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN18_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 3: /* DSC3 */ - REG_UPDATE(DOMAIN19_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN17_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 2: /* DSC2 */ + REG_UPDATE(DOMAIN18_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN19_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - default: - BREAK_TO_DEBUGGER(); - break; + REG_WAIT(DOMAIN18_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 3: /* DSC3 */ + REG_UPDATE(DOMAIN19_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN19_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); - if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(