From 58d0379d29db10cf382d0b368c8da183f43e612b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 23 Apr 2026 19:36:08 +0200 Subject: [PATCH 1/8] cpufreq: qcom: Unify user-visible "Qualcomm" name Various names for Qualcomm as a company are used in user-visible config options. Switch to unified "Qualcomm" so it will be easier for users to identify the options when for example running menuconfig. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Viresh Kumar --- drivers/cpufreq/Kconfig.arm | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 47c9b031f1b3..a441668f9e0c 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -153,7 +153,7 @@ config ARM_QCOM_CPUFREQ_NVMEM If in doubt, say N. config ARM_QCOM_CPUFREQ_HW - tristate "QCOM CPUFreq HW driver" + tristate "Qualcomm CPUFreq HW driver" depends on ARCH_QCOM || COMPILE_TEST depends on COMMON_CLK help From 08a64b9bfc1c099ede2c881adfd7a49fd285e79f Mon Sep 17 00:00:00 2001 From: Hans Zhang <18255117159@163.com> Date: Fri, 1 May 2026 00:32:12 +0800 Subject: [PATCH 2/8] cpufreq/amd-pstate: Use FIELD_MODIFY() Use FIELD_MODIFY() to remove open-coded bit manipulation. No functional change intended. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: K Prateek Nayak Signed-off-by: Viresh Kumar --- drivers/cpufreq/amd-pstate.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 453084c67327..1037d1722263 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -246,12 +246,10 @@ static int msr_update_perf(struct cpufreq_policy *policy, u8 min_perf, value = prev = READ_ONCE(cpudata->cppc_req_cached); - value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | - AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); - value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); - value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); - value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); - value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_MAX_PERF_MASK, &value, max_perf); + FIELD_MODIFY(AMD_CPPC_DES_PERF_MASK, &value, des_perf); + FIELD_MODIFY(AMD_CPPC_MIN_PERF_MASK, &value, min_perf); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); if (trace_amd_pstate_epp_perf_enabled()) { union perf_cached perf = READ_ONCE(cpudata->perf); @@ -300,8 +298,7 @@ static int msr_set_epp(struct cpufreq_policy *policy, u8 epp) int ret; value = prev = READ_ONCE(cpudata->cppc_req_cached); - value &= ~AMD_CPPC_EPP_PERF_MASK; - value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); if (trace_amd_pstate_epp_perf_enabled()) { union perf_cached perf = cpudata->perf; @@ -441,8 +438,7 @@ static int shmem_set_epp(struct cpufreq_policy *policy, u8 epp) } value = READ_ONCE(cpudata->cppc_req_cached); - value &= ~AMD_CPPC_EPP_PERF_MASK; - value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); return ret; @@ -575,12 +571,10 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf, value = prev = READ_ONCE(cpudata->cppc_req_cached); - value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | - AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); - value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); - value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); - value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); - value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_MAX_PERF_MASK, &value, max_perf); + FIELD_MODIFY(AMD_CPPC_DES_PERF_MASK, &value, des_perf); + FIELD_MODIFY(AMD_CPPC_MIN_PERF_MASK, &value, min_perf); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); if (trace_amd_pstate_epp_perf_enabled()) { union perf_cached perf = READ_ONCE(cpudata->perf); From 88e8df5904007ea53232237acf9ad02aeb992ece Mon Sep 17 00:00:00 2001 From: Hans Zhang <18255117159@163.com> Date: Fri, 1 May 2026 00:32:13 +0800 Subject: [PATCH 3/8] cpufreq: apple-soc: Use FIELD_MODIFY() Use FIELD_MODIFY() to remove open-coded bit manipulation. No functional change intended. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Joshua Peisach Signed-off-by: Viresh Kumar --- drivers/cpufreq/apple-soc-cpufreq.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/apple-soc-cpufreq.c b/drivers/cpufreq/apple-soc-cpufreq.c index 9396034167e5..638e5bf72185 100644 --- a/drivers/cpufreq/apple-soc-cpufreq.c +++ b/drivers/cpufreq/apple-soc-cpufreq.c @@ -187,10 +187,8 @@ static int apple_soc_cpufreq_set_target(struct cpufreq_policy *policy, reg &= ~priv->info->ps1_mask; reg |= pstate << priv->info->ps1_shift; - if (priv->info->has_ps2) { - reg &= ~APPLE_DVFS_CMD_PS2; - reg |= FIELD_PREP(APPLE_DVFS_CMD_PS2, pstate); - } + if (priv->info->has_ps2) + FIELD_MODIFY(APPLE_DVFS_CMD_PS2, ®, pstate); reg |= APPLE_DVFS_CMD_SET; writeq_relaxed(reg, priv->reg_base + APPLE_DVFS_CMD); From bcb8889c4981fdde42d4fd2c29a77d510fe21da2 Mon Sep 17 00:00:00 2001 From: Guangshuo Li Date: Sat, 2 May 2026 03:00:05 +0800 Subject: [PATCH 4/8] cpufreq: qcom-cpufreq-hw: Fix possible double free qcom_cpufreq.data is allocated with devm_kzalloc() in probe() as an array of per-domain data. qcom_cpufreq_hw_cpu_init() stores a pointer to one element of this array in policy->driver_data. qcom_cpufreq_hw_cpu_exit() currently calls kfree() on policy->driver_data. This is not valid because the memory is devm-managed. For the first domain, this can free the devm-managed allocation while the devres entry is still active, leading to a possible double free when the platform device is later detached. For other domains, the pointer may refer to an element inside the array rather than the allocation base. Remove the kfree(data) call and let devres release qcom_cpufreq.data. This issue was found by a static analysis tool I am developing. Fixes: 054a3ef683a1 ("cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe") Cc: stable@vger.kernel.org Signed-off-by: Guangshuo Li Reviewed-by: Zhongqiu Han Signed-off-by: Viresh Kumar --- drivers/cpufreq/qcom-cpufreq-hw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index ea9a20d27b8f..ef19faedbfec 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -578,7 +578,6 @@ static void qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); qcom_cpufreq_hw_lmh_exit(data); kfree(policy->freq_table); - kfree(data); } static void qcom_cpufreq_ready(struct cpufreq_policy *policy) From 9a303892acac58e77704d336418fa9ae92e3f70f Mon Sep 17 00:00:00 2001 From: Xueqin Luo Date: Fri, 15 May 2026 10:42:42 +0800 Subject: [PATCH 5/8] cpufreq: cppc: mask Desired_Excursion when autonomous selection is enabled According to the ACPI 6.6 specification, the Desired_Excursion field is not utilized when autonomous selection is enabled. In this mode, the bit is architecturally ignored and does not carry meaningful information. Currently, the kernel exposes the raw Performance Limited register value to userspace through the cpufreq sysfs interface. This may lead to misinterpretation, as userspace may assume Desired_Excursion is valid even when autonomous selection is active. To provide a stable and semantically correct ABI, mask out the Desired_Excursion bit when autonomous selection is enabled, so that userspace does not observe undefined or misleading values. Writes are left unchanged, as the field is architecturally ignored in this mode and write attempts are harmless. Signed-off-by: Xueqin Luo Reviewed-by: Pierre Gondois Reviewed-by: Sumit Gupta Signed-off-by: Viresh Kumar --- drivers/cpufreq/cppc_cpufreq.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 7e7f9dfb7a24..bf5175f7551c 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -982,7 +982,34 @@ store_energy_performance_preference_val(struct cpufreq_policy *policy, return count; } -CPPC_CPUFREQ_ATTR_RW_U64(perf_limited, cppc_get_perf_limited, +static int cppc_get_perf_limited_filtered(int cpu, u64 *perf_limited) +{ + struct cpufreq_policy *policy; + struct cppc_cpudata *cpu_data; + int ret; + + ret = cppc_get_perf_limited(cpu, perf_limited); + if (ret) + return ret; + + policy = cpufreq_cpu_get_raw(cpu); + if (!policy) + return -EINVAL; + + cpu_data = policy->driver_data; + + /* + * Desired Excursion is ignored when autonomous selection is + * enabled. Clear the bit to avoid exposing meaningless state + * to userspace. + */ + if (cpu_data && cpu_data->perf_ctrls.auto_sel) + *perf_limited &= ~CPPC_PERF_LIMITED_DESIRED_EXCURSION; + + return 0; +} + +CPPC_CPUFREQ_ATTR_RW_U64(perf_limited, cppc_get_perf_limited_filtered, cppc_set_perf_limited) cpufreq_freq_attr_ro(freqdomain_cpus); From ef92354d0e6261e0ed792666972ef0b257cc0d8f Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Fri, 22 May 2026 20:46:22 +0530 Subject: [PATCH 6/8] dt-bindings: cpufreq: Document Qualcomm Shikra SoC EPSS The Qualcomm Shikra cpufreq hardware is functionally identical to EPSS, but supports only up to 12 frequency lookup table (LUT) entries. Introduce Shikra specific bindings to represent this constrained EPSS variant. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Imran Shaik Signed-off-by: Viresh Kumar --- .../bindings/cpufreq/qcom,shikra-epss.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml b/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml new file mode 100644 index 000000000000..1a3105e86980 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/qcom,shikra-epss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shikra SoC EPSS + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + EPSS is a hardware engine used by some Qualcomm SoCs to manage + frequency in hardware. It is capable of controlling frequency for + multiple clusters. + + The Qualcomm Shikra SoC EPSS supports up to 12 frequency lookup table + (LUT) entries. + +properties: + compatible: + enum: + - qcom,shikra-epss + + reg: + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + + reg-names: + items: + - const: freq-domain0 + - const: freq-domain1 + + clocks: + items: + - description: XO Clock + - description: GPLL0 Clock + + clock-names: + items: + - const: xo + - const: alternate + + interrupts: + items: + - description: IRQ line for DCVSH 0 + - description: IRQ line for DCVSH 1 + + interrupt-names: + items: + - const: dcvsh-irq-0 + - const: dcvsh-irq-1 + + '#freq-domain-cells': + const: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - '#freq-domain-cells' + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + cpufreq@fd91000 { + compatible = "qcom,shikra-epss"; + reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gpll0>; + clock-names = "xo", "alternate"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; +... From 4b5d3b847218b466527fb98990e193874081e0c7 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 22 May 2026 20:46:23 +0530 Subject: [PATCH 7/8] cpufreq: qcom: Add cpufreq scaling support for Qualcomm Shikra SoC The Qualcomm Shikra cpufreq hardware is functionally identical to EPSS, but supports only up to 12 frequency lookup table (LUT) entries. When all 12 entries are populated, the existing repetitive LUT entry check may read beyond valid entries and expose incorrect frequencies. Hence, introduce shikra_epss_soc_data that reuses EPSS configuration with appropriate LUT entries limit. Signed-off-by: Taniya Das Reviewed-by: Konrad Dybcio Signed-off-by: Imran Shaik Signed-off-by: Viresh Kumar --- drivers/cpufreq/qcom-cpufreq-hw.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index ef19faedbfec..874ff3fb9d97 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include @@ -40,6 +41,7 @@ struct qcom_cpufreq_soc_data { u32 reg_intr_clr; u32 reg_current_vote; u32 reg_perf_state; + u32 lut_max_entries; u8 lut_row_size; }; @@ -156,7 +158,7 @@ static unsigned int qcom_cpufreq_get_freq(struct cpufreq_policy *policy) soc_data = qcom_cpufreq.soc_data; index = readl_relaxed(data->base + soc_data->reg_perf_state); - index = min(index, LUT_MAX_ENTRIES - 1); + index = min(index, soc_data->lut_max_entries - 1); return policy->freq_table[index].frequency; } @@ -211,7 +213,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, struct qcom_cpufreq_data *drv_data = policy->driver_data; const struct qcom_cpufreq_soc_data *soc_data = qcom_cpufreq.soc_data; - table = kzalloc_objs(*table, LUT_MAX_ENTRIES + 1); + table = kzalloc_objs(*table, soc_data->lut_max_entries + 1); if (!table) return -ENOMEM; @@ -236,7 +238,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, icc_scaling_enabled = false; } - for (i = 0; i < LUT_MAX_ENTRIES; i++) { + for (i = 0; i < soc_data->lut_max_entries; i++) { data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut + i * soc_data->lut_row_size); src = FIELD_GET(LUT_SRC, data); @@ -405,6 +407,7 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { .reg_current_vote = 0x704, .reg_perf_state = 0x920, .lut_row_size = 32, + .lut_max_entries = LUT_MAX_ENTRIES, }; static const struct qcom_cpufreq_soc_data epss_soc_data = { @@ -416,11 +419,25 @@ static const struct qcom_cpufreq_soc_data epss_soc_data = { .reg_intr_clr = 0x308, .reg_perf_state = 0x320, .lut_row_size = 4, + .lut_max_entries = LUT_MAX_ENTRIES, +}; + +static const struct qcom_cpufreq_soc_data shikra_epss_soc_data = { + .reg_enable = 0x0, + .reg_domain_state = 0x20, + .reg_dcvs_ctrl = 0xb0, + .reg_freq_lut = 0x100, + .reg_volt_lut = 0x200, + .reg_intr_clr = 0x308, + .reg_perf_state = 0x320, + .lut_row_size = 4, + .lut_max_entries = 12, }; static const struct of_device_id qcom_cpufreq_hw_match[] = { { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data }, + { .compatible = "qcom,shikra-epss", .data = &shikra_epss_soc_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); From b7a76f38ef3500d53ec87489c445fec8100c7a6b Mon Sep 17 00:00:00 2001 From: Akashdeep Kaur Date: Wed, 3 Jun 2026 12:54:38 +0530 Subject: [PATCH 8/8] cpufreq: ti: Add EPROBE_DEFER for K3 SoCs On K3 SoCs, ti-cpufreq relies on k3-socinfo to register the SoC device before soc_device_match() can return valid revision information. If ti-cpufreq probes before k3-socinfo, soc_device_match() returns NULL, leading to incorrect CPU frequency scaling behavior. Add a needs_k3_socinfo flag to ti_cpufreq_soc_data (similar to the existing multi_regulator pattern) to defer probe when k3-socinfo hasn't registered the SoC device yet. Signed-off-by: Akashdeep Kaur Reviewed-by: Zhongqiu Han Signed-off-by: Viresh Kumar --- drivers/cpufreq/ti-cpufreq.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index a01abc1622eb..0f96492341f2 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -99,6 +99,7 @@ struct ti_cpufreq_soc_data { unsigned long efuse_shift; unsigned long rev_offset; bool multi_regulator; + bool needs_k3_socinfo; /* Backward compatibility hack: Might have missing syscon */ #define TI_QUIRK_SYSCON_MAY_BE_MISSING 0x1 /* Backward compatibility hack: new syscon size is 1 register wide */ @@ -347,6 +348,7 @@ static struct ti_cpufreq_soc_data am625_soc_data = { .efuse_mask = 0x07c0, .efuse_shift = 0x6, .multi_regulator = false, + .needs_k3_socinfo = true, .quirks = TI_QUIRK_SYSCON_IS_SINGLE_REG, }; @@ -356,6 +358,7 @@ static struct ti_cpufreq_soc_data am62a7_soc_data = { .efuse_mask = 0x07c0, .efuse_shift = 0x6, .multi_regulator = false, + .needs_k3_socinfo = true, }; static struct ti_cpufreq_soc_data am62l3_soc_data = { @@ -364,6 +367,7 @@ static struct ti_cpufreq_soc_data am62l3_soc_data = { .efuse_mask = 0x07c0, .efuse_shift = 0x6, .multi_regulator = false, + .needs_k3_socinfo = true, }; static struct ti_cpufreq_soc_data am62p5_soc_data = { @@ -372,6 +376,7 @@ static struct ti_cpufreq_soc_data am62p5_soc_data = { .efuse_mask = 0x07c0, .efuse_shift = 0x6, .multi_regulator = false, + .needs_k3_socinfo = true, }; /** @@ -443,6 +448,11 @@ static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data, goto done; } + /* Defer if k3-socinfo hasn't registered the SoC device yet */ + if (opp_data->soc_data->needs_k3_socinfo) + return dev_err_probe(opp_data->cpu_dev, -EPROBE_DEFER, + "SoC device not registered by k3-socinfo\n"); + ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, &revision); if (opp_data->soc_data->quirks & TI_QUIRK_SYSCON_MAY_BE_MISSING && ret == -EIO) {