github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-27 16:44:58 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

Renesas DTS updates for v6.9 (take two)

Browse Source 
- Add pin control, I2C, GPIO, CA76 cluster, Ethernet, SD/MMC, DMA, and
     HyperFLASH/QSPI (RPC) support for the R-Car V4M SoC,
   - Add I2C EEPROM, Ethernet, eMMC, and QSPI FLASH support for the Gray
     Hawk Single development board,
   - Fix PCIe power on ULCB development boards equipped with the
     Shimafuji Kingfisher extension,
   - Add PSCI support for the RZ/G3S SoC,
   - Add camera support for the RZ/G2UL SMARC EVK development board,
   - Add display support for the RZ/G2L{,C} and RZ/V2L SoCs and SMARC EVK
     development boards,
   - Miscellaneous fixes and improvements,
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZdh7QwAKCRCKwlD9ZEnx
 cDxcAQDLIZaS/ODio5p/KmIGwi/5tuY1dK/FOMwkmOuOvlTSSwD+PsYBDEhr98of
 Mz7woOMUnMh0/SbCgggd69u4KLnbwAs=
 =IcGX
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXgtHIACgkQYKtH/8kJ
 UifE9Q/8Coa4FOLFWy9qzZAh1Fw/UZnUqp50vePr34xyhH5iOrajsQSP2ZAfRIoI
 jSk0DMr8WZEVvBa4YQ/nBCg6aJWtSrCAQcQ99FCtLnuId0XkfNNXgCWFNTadSCLQ
 lpDuMMCCEkkFn1AnRP8UcO4jC6uRn7nIKXaHRj/pVBwda+z34xEdsbYuIW7GPoVq
 385VCE0aLKqm/u6MpcuWlGwdKAAmO0FsnpFSZkoec71D2TmF1+miXTD4l/0Llhmh
 DBU6ms+WmQvpn5u8+RsVP2LawSoyok3vejXu2N6WhqIUozwVi6FWYBwaOnZD2EMa
 5FYhCosCpuJETBC3eh5/hT13onmZMiJqE056KKOB4oTFP7Mjr6HAQNPBZtmIF+Rh
 r3pgZ1p6QX1NrMie+jO6rsHxxJXvl/7Iy+4kH0tvzN2dPsmE36xbSnxA3CACA+66
 Ny17pwaVczLsp+FnbhEs8PVYVzfIPuzVq46aJTxVbNbfGK/mpex5ncoU2K6FkJCg
 0mKKjTeaf75jIYWCR395GeAdJ2DVl+IIEIXqE5me5I3Ug0FzVLDEWa+rPiKXAELf
 OC7HEWCoq2IZsiwvilv7v+OgRzX4EuRBy8Yf8IkDYxwMy7SDtmkfStIhrcCmuvsR
 jXK6L5fk9Z4yuhezNOXNJy5gb2KlRiO69tpnTdJyvR5x6nfwWzk=
 =fAmU
 -----END PGP SIGNATURE-----

Merge tag 'renesas-dts-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.9 (take two)

  - Add pin control, I2C, GPIO, CA76 cluster, Ethernet, SD/MMC, DMA, and
    HyperFLASH/QSPI (RPC) support for the R-Car V4M SoC,
  - Add I2C EEPROM, Ethernet, eMMC, and QSPI FLASH support for the Gray
    Hawk Single development board,
  - Fix PCIe power on ULCB development boards equipped with the
    Shimafuji Kingfisher extension,
  - Add PSCI support for the RZ/G3S SoC,
  - Add camera support for the RZ/G2UL SMARC EVK development board,
  - Add display support for the RZ/G2L{,C} and RZ/V2L SoCs and SMARC EVK
    development boards,
  - Miscellaneous fixes and improvements,

* tag 'renesas-dts-for-v6.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (31 commits)
  arm64: dts: renesas: rzg2l-smarc: Enable DU and link with DSI
  arm64: dts: renesas: r9a07g054: Add DU node
  arm64: dts: renesas: r9a07g044: Add DU node
  arm64: dts: renesas: gray-hawk-single: Add QSPI FLASH support
  arm64: dts: renesas: r8a779h0: Add RPC node
  arm64: dts: renesas: r8a779h0: Add DMA support
  arm64: dts: renesas: gray-hawk-single: Add eMMC support
  arm64: dts: renesas: r8a779h0: Add SD/MMC node
  ARM: dts: renesas: r8a7778: Add missing reg-names to sound node
  arm64: dts: renesas: rzg2ul-smarc: Enable CRU, CSI support
  arm64: dts: renesas: gray-hawk-single: Add Ethernet support
  arm64: dts: renesas: r8a779h0: Add Ethernet-AVB support
  arm64: dts: renesas: r8a779g0: Correct avb[01] reg sizes
  arm64: dts: renesas: r8a779a0: Correct avb[01] reg sizes
  arm64: dts: renesas: r9a08g045: Add PSCI support
  arm64: dts: renesas: rzg3s-smarc-som: Guard Ethernet IRQ GPIO hogs
  arm64: dts: renesas: r9a08g045: Add missing interrupts to IRQC node
  arm64: dts: renesas: rzg2l: Add missing interrupts to IRQC nodes
  arm64: dts: renesas: r8a779h0: Add CA76 operating points
  arm64: dts: renesas: r8a779h0: Add CPU core clocks
  ...

Link: https://lore.kernel.org/r/cover.1708687134.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-02-29 17:44:33 +01:00
commit 11e876b3c3
15 changed files with 940 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/renesas/r8a7778.dtsi
View File

@ -255,6 +255,8 @@ rcar_sound: sound@ffd90000 {
reg = <0xffd90000 0x1000>, /* SRU */
<0xffd91000 0x240>, /* SSI */
<0xfffe0000 0x24>; /* ADG */
reg-names = "sru", "ssi", "adg";
clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
<&mstp3_clks R8A7778_CLK_SSI7>,
<&mstp3_clks R8A7778_CLK_SSI6>,

3
arch/arm64/boot/dts/renesas/Makefile
View File

@ -108,7 +108,10 @@ r8a779m5-salvator-xs-panel-aa104xd12-dtbs := r8a779m5-salvator-xs.dtb salvator-p
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs-panel-aa104xd12.dtb
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo
r9a07g043u11-smarc-cru-csi-ov5645-dtbs := r9a07g043u11-smarc.dtb r9a07g043u11-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtb
r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb

4
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@ -667,7 +667,7 @@ channel7 {
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6800000 0 0x800>;
reg = <0 0xe6800000 0 0x1000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
@ -715,7 +715,7 @@ avb0: ethernet@e6800000 {
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6810000 0 0x800>;
reg = <0 0xe6810000 0 0x1000>;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,

4
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@ -776,7 +776,7 @@ channel7 {
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6800000 0 0x800>;
reg = <0 0xe6800000 0 0x1000>;
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
@ -823,7 +823,7 @@ avb0: ethernet@e6800000 {
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6810000 0 0x800>;
reg = <0 0xe6810000 0 0x1000>;
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,

173
arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts
View File

@ -7,6 +7,9 @@
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "r8a779h0.dtsi"
/ {
@ -15,6 +18,7 @@ / {
aliases {
serial0 = &hscif0;
ethernet0 = &avb0;
};
chosen {
@ -32,6 +36,42 @@ memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x1 0x80000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio7>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
};
};
&extal_clk {
@ -43,10 +83,143 @@ &extalr_clk {
};
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
reg = <0x50>;
pagesize = <8>;
};
eeprom@51 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "breakout-board";
reg = <0x51>;
pagesize = <8>;
};
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
reg = <0x52>;
pagesize = <8>;
};
eeprom@53 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "ethernet-sub-board-id";
reg = <0x53>;
pagesize = <8>;
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
"avb0_txcrefclk";
function = "avb0";
};
pins_mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins_mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
};
hscif0_pins: hscif0 {
groups = "hscif0_data", "hscif0_ctrl";
function = "hscif0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif_clk_pins: scif-clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0x1200000>;
read-only;
};
user@1200000 {
reg = <0x1200000 0x2e00000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";

532
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
View File

@ -14,15 +14,109 @@ / {
#address-cells = <2>;
#size-cells = <2>;
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <825000>;
clock-latency-ns = <500000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <825000>;
clock-latency-ns = <500000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&a76_0>;
};
core1 {
cpu = <&a76_1>;
};
core2 {
cpu = <&a76_2>;
};
core3 {
cpu = <&a76_3>;
};
};
};
a76_0: cpu@0 {
compatible = "arm,cortex-a76";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
next-level-cache = <&L3_CA76>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>;
operating-points-v2 = <&cluster0_opp>;
};
a76_1: cpu@100 {
compatible = "arm,cortex-a76";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A779H0_PD_A1E0D0C1>;
next-level-cache = <&L3_CA76>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>;
operating-points-v2 = <&cluster0_opp>;
};
a76_2: cpu@200 {
compatible = "arm,cortex-a76";
reg = <0x200>;
device_type = "cpu";
power-domains = <&sysc R8A779H0_PD_A1E0D0C2>;
next-level-cache = <&L3_CA76>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>;
operating-points-v2 = <&cluster0_opp>;
};
a76_3: cpu@300 {
compatible = "arm,cortex-a76";
reg = <0x300>;
device_type = "cpu";
power-domains = <&sysc R8A779H0_PD_A1E0D0C3>;
next-level-cache = <&L3_CA76>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>;
operating-points-v2 = <&cluster0_opp>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <500>;
min-residency-us = <4000>;
};
};
L3_CA76: cache-controller {
compatible = "cache";
power-domains = <&sysc R8A779H0_PD_A2E0D0>;
cache-unified;
cache-level = <3>;
};
};
@ -45,6 +139,11 @@ pmu-a76 {
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif-clk {
compatible = "fixed-clock";
@ -70,6 +169,134 @@ rwdt: watchdog@e6020000 {
status = "disabled";
};
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a779h0";
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
<0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
<0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
<0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
};
gpio0: gpio@e6050180 {
compatible = "renesas,gpio-r8a779h0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6050180 0 0x54>;
interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 19>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 915>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
};
gpio1: gpio@e6050980 {
compatible = "renesas,gpio-r8a779h0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6050980 0 0x54>;
interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 30>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 915>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
};
gpio2: gpio@e6058180 {
compatible = "renesas,gpio-r8a779h0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6058180 0 0x54>;
interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 20>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 916>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 916>;
};
gpio3: gpio@e6058980 {
compatible = "renesas,gpio-r8a779h0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6058980 0 0x54>;
interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 916>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 916>;
};
gpio4: gpio@e6060180 {
compatible = "renesas,gpio-r8a779h0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6060180 0 0x54>;
interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 25>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 917>;
};
gpio5: gpio@e6060980 {
compatible = "renesas,gpio-r8a779h0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6060980 0 0x54>;
interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 21>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 917>;
};
gpio6: gpio@e6061180 {
compatible = "renesas,gpio-r8a779h0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6061180 0 0x54>;
interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 192 21>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 917>;
};
gpio7: gpio@e6061980 {
compatible = "renesas,gpio-r8a779h0",
"renesas,rcar-gen4-gpio";
reg = <0 0xe6061980 0 0x54>;
interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 224 21>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 917>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779h0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
@ -91,6 +318,74 @@ sysc: system-controller@e6180000 {
#power-domain-cells = <1>;
};
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a779h0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 518>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@e6508000 {
compatible = "renesas,i2c-r8a779h0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 519>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
<&dmac2 0x93>, <&dmac2 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@e6510000 {
compatible = "renesas,i2c-r8a779h0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 520>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@e66d0000 {
compatible = "renesas,i2c-r8a779h0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 521>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 521>;
dmas = <&dmac1 0x97>, <&dmac1 0x96>,
<&dmac2 0x97>, <&dmac2 0x96>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a779h0",
"renesas,rcar-gen4-hscif", "renesas,hscif";
@ -102,6 +397,243 @@ hscif0: serial@e6540000 {
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 514>;
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx";
status = "disabled";
};
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779h0",
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6800000 0 0x1000>;
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 211>;
clock-names = "fck";
power-domains = <&sysc R8A779H0_PD_C4>;
resets = <&cpg 211>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779h0",
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6810000 0 0x1000>;
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 212>;
clock-names = "fck";
power-domains = <&sysc R8A779H0_PD_C4>;
resets = <&cpg 212>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
avb2: ethernet@e6820000 {
compatible = "renesas,etheravb-r8a779h0",
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6820000 0 0x1000>;
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 213>;
clock-names = "fck";
power-domains = <&sysc R8A779H0_PD_C4>;
resets = <&cpg 213>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dmac1: dma-controller@e7350000 {
compatible = "renesas,dmac-r8a779h0",
"renesas,rcar-gen4-dmac";
reg = <0 0xe7350000 0 0x1000>,
<0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch4",
"ch5", "ch6", "ch7", "ch8", "ch9",
"ch10", "ch11", "ch12", "ch13",
"ch14", "ch15";
clocks = <&cpg CPG_MOD 709>;
clock-names = "fck";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 709>;
#dma-cells = <1>;
dma-channels = <16>;
};
dmac2: dma-controller@e7351000 {
compatible = "renesas,dmac-r8a779h0",
"renesas,rcar-gen4-dmac";
reg = <0 0xe7351000 0 0x1000>,
<0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch4",
"ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 710>;
clock-names = "fck";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 710>;
#dma-cells = <1>;
dma-channels = <8>;
};
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a779h0",
"renesas,rcar-gen4-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 706>,
<&cpg CPG_CORE R8A779H0_CLK_SD0H>;
clock-names = "core", "clkh";
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 706>;
max-frequency = <200000000>;
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a779h0-rpc-if",
"renesas,rcar-gen4-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>;
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
resets = <&cpg 629>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};

12
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
View File

@ -178,7 +178,13 @@ irqc: interrupt-controller@110a0000 {
<SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>;
<SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
@ -190,7 +196,9 @@ irqc: interrupt-controller@110a0000 {
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err";
"bus-err", "ec7tie1-0", "ec7tie2-0",
"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
"ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
<&cpg CPG_MOD R9A07G043_IA55_PCLK>;
clock-names = "clk", "pclk";

21
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso Normal file
View File

@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree overlay for the RZ/G2UL SMARC EVK with OV5645 camera
* connected to CSI and CRU enabled.
*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
#define OV5645_PARENT_I2C i2c0
#include "rz-smarc-cru-csi-ov5645.dtsi"
&ov5645 {
enable-gpios = <&pinctrl RZG2L_GPIO(4, 4) GPIO_ACTIVE_HIGH>;
reset-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
};

68
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -793,6 +793,22 @@ dsi: dsi@10850000 {
reset-names = "rst", "arst", "prst";
power-domains = <&cpg>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&du_out_dsi>;
};
};
port@1 {
reg = <1>;
};
};
};
vspd: vsp@10870000 {
@ -820,6 +836,36 @@ fcpvd: fcp@10880000 {
resets = <&cpg R9A07G044_LCDC_RESET_N>;
};
du: display@10890000 {
compatible = "renesas,r9a07g044-du";
reg = <0 0x10890000 0 0x10000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
<&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
<&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
clock-names = "aclk", "pclk", "vclk";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_LCDC_RESET_N>;
renesas,vsps = <&vspd 0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_dsi: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
};
};
};
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g044-cpg";
reg = <0 0x11010000 0 0x10000>;
@ -905,7 +951,27 @@ irqc: interrupt-controller@110a0000 {
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"tint0", "tint1", "tint2", "tint3",
"tint4", "tint5", "tint6", "tint7",
"tint8", "tint9", "tint10", "tint11",
"tint12", "tint13", "tint14", "tint15",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err", "ec7tie1-0", "ec7tie2-0",
"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
"ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
clock-names = "clk", "pclk";

69
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@ -798,6 +798,22 @@ dsi: dsi@10850000 {
reset-names = "rst", "arst", "prst";
power-domains = <&cpg>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&du_out_dsi>;
};
};
port@1 {
reg = <1>;
};
};
};
vspd: vsp@10870000 {
@ -826,6 +842,37 @@ fcpvd: fcp@10880000 {
resets = <&cpg R9A07G054_LCDC_RESET_N>;
};
du: display@10890000 {
compatible = "renesas,r9a07g054-du",
"renesas,r9a07g044-du";
reg = <0 0x10890000 0 0x10000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
<&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
<&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
clock-names = "aclk", "pclk", "vclk";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_LCDC_RESET_N>;
renesas,vsps = <&vspd 0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_dsi: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
};
};
};
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g054-cpg";
reg = <0 0x11010000 0 0x10000>;
@ -912,7 +959,27 @@ irqc: interrupt-controller@110a0000 {
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"tint0", "tint1", "tint2", "tint3",
"tint4", "tint5", "tint6", "tint7",
"tint8", "tint9", "tint10", "tint11",
"tint12", "tint13", "tint14", "tint15",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err", "ec7tie1-0", "ec7tie2-0",
"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
"ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
<&cpg CPG_MOD R9A07G054_IA55_PCLK>;
clock-names = "clk", "pclk";

13
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
View File

@ -42,6 +42,11 @@ extal_clk: extal-clk {
clock-frequency = <0>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@ -152,7 +157,10 @@ irqc: interrupt-controller@11050000 {
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
@ -164,7 +172,8 @@ irqc: interrupt-controller@11050000 {
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err";
"bus-err", "ec7tie1-0", "ec7tie2-0",
"ec7tiovf-0";
clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
<&cpg CPG_MOD R9A08G045_IA55_PCLK>;
clock-names = "clk", "pclk";

14
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
View File

@ -40,17 +40,7 @@ &dsi {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&adv7535_in>;
@ -59,6 +49,10 @@ dsi0_out: endpoint {
};
};
&du {
status = "okay";
};
&i2c1 {
adv7535: hdmi@3d {
compatible = "adi,adv7535";

14
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
View File

@ -56,17 +56,7 @@ &dsi {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&adv7535_in>;
@ -75,6 +65,10 @@ dsi0_out: endpoint {
};
};
&du {
status = "okay";
};
&i2c1 {
adv7535: hdmi@3d {
compatible = "adi,adv7535";

4
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
View File

@ -193,12 +193,14 @@ &sdhi2 {
#endif
&pinctrl {
#if SW_CONFIG3 == SW_ON
eth0-phy-irq-hog {
gpio-hog;
gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
input;
line-name = "eth0-phy-irq";
};
#endif
eth0_pins: eth0 {
txc {
@ -234,12 +236,14 @@ mux {
};
};
#if SW_CONFIG3 == SW_ON
eth1-phy-irq-hog {
gpio-hog;
gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
input;
line-name = "eth1-phy-irq";
};
#endif
eth1_pins: eth1 {
txc {

49
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
View File

@ -32,18 +32,40 @@ hdmi1_con: endpoint {
};
};
hdmi_1v8: regulator-hdmi-1v8 {
reg_t1p8v: regulator-t1p8v {
compatible = "regulator-fixed";
regulator-name = "hdmi-1v8";
regulator-name = "T1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
snd_vcc5v: regulator-snd_vcc5v {
pcie_1v5: regulator-pcie-1v5 {
compatible = "regulator-fixed";
regulator-name = "snd-vcc5v";
regulator-name = "pcie-1v5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&gpio_exp_77 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
pcie_3v3: regulator-pcie-3v3 {
compatible = "regulator-fixed";
regulator-name = "pcie-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_exp_77 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
wlan_en: regulator-wlan_en {
@ -136,11 +158,11 @@ hdmi@3d {
pd-gpios = <&gpio_exp_75 5 GPIO_ACTIVE_LOW>;
avdd-supply = <&hdmi_1v8>;
dvdd-supply = <&hdmi_1v8>;
pvdd-supply = <&hdmi_1v8>;
avdd-supply = <&reg_t1p8v>;
dvdd-supply = <&reg_t1p8v>;
pvdd-supply = <&reg_t1p8v>;
dvdd-3v-supply = <&reg_3p3v>;
bgvdd-supply = <&hdmi_1v8>;
bgvdd-supply = <&reg_t1p8v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
@ -190,10 +212,10 @@ pcm3168a: audio-codec@44 {
VDD1-supply = <&reg_3p3v>;
VDD2-supply = <&reg_3p3v>;
VCCAD1-supply = <&snd_vcc5v>;
VCCAD2-supply = <&snd_vcc5v>;
VCCDA1-supply = <&snd_vcc5v>;
VCCDA2-supply = <&snd_vcc5v>;
VCCAD1-supply = <&reg_5v>;
VCCAD2-supply = <&reg_5v>;
VCCDA1-supply = <&reg_5v>;
VCCDA2-supply = <&reg_5v>;
};
gyroscope@6b {
@ -327,6 +349,9 @@ &pciec0 {
&pciec1 {
status = "okay";
vpcie1v5-supply = <&pcie_1v5>;
vpcie3v3-supply = <&pcie_3v3>;
};
&pfc {