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drm/amd/display: Consolidate dmub fb info to a single struct

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[WHY&HOW]
Consolidate dmub fb info into a single structure to simplify translation
between components.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone 2025-12-09 15:26:33 -05:00 committed by Alex Deucher
parent 5ad5b0b784
commit 11dbb6d7b2
9 changed files with 33 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -1336,8 +1336,8 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
/* Initialize hardware. */
memset(&hw_params, 0, sizeof(hw_params));
hw_params.fb_base = adev->gmc.fb_start;
hw_params.fb_offset = adev->vm_manager.vram_base_offset;
hw_params.soc_fb_info.fb_base = adev->gmc.fb_start;
hw_params.soc_fb_info.fb_offset = adev->vm_manager.vram_base_offset;
/* backdoor load firmware and trigger dmub running */
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)

16
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
View File

@ -307,6 +307,16 @@ struct dmub_srv_fb_info {
struct dmub_fb fb[DMUB_WINDOW_TOTAL];
};
/**
* struct dmub_soc_fb_info - relevant addresses from the frame buffer
* @fb_base: base of the framebuffer aperture
* @fb_offset: offset of the framebuffer aperture
*/
struct dmub_soc_fb_info {
uint64_t fb_base;
uint64_t fb_offset;
};
/*
* struct dmub_srv_hw_params - params for dmub hardware initialization
* @fb: framebuffer info for each region
@ -317,8 +327,7 @@ struct dmub_srv_fb_info {
*/
struct dmub_srv_hw_params {
struct dmub_fb *fb[DMUB_WINDOW_TOTAL];
uint64_t fb_base;
uint64_t fb_offset;
struct dmub_soc_fb_info soc_fb_info;
uint32_t psp_version;
bool load_inst_const;
bool skip_panel_power_sequence;
@ -610,8 +619,7 @@ struct dmub_srv {
bool hw_init;
bool dpia_supported;
uint64_t fb_base;
uint64_t fb_offset;
struct dmub_soc_fb_info soc_fb_info;
uint32_t psp_version;
/* Feature capabilities reported by fw */

6
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
View File

@ -63,9 +63,9 @@ static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
{
uint32_t tmp;
if (dmub->fb_base || dmub->fb_offset) {
*fb_base = dmub->fb_base;
*fb_offset = dmub->fb_offset;
if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
*fb_base = dmub->soc_fb_info.fb_base;
*fb_offset = dmub->soc_fb_info.fb_offset;
return;
}

6
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
View File

@ -63,9 +63,9 @@ static void dmub_dcn30_get_fb_base_offset(struct dmub_srv *dmub,
{
uint32_t tmp;
if (dmub->fb_base || dmub->fb_offset) {
*fb_base = dmub->fb_base;
*fb_offset = dmub->fb_offset;
if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
*fb_base = dmub->soc_fb_info.fb_base;
*fb_offset = dmub->soc_fb_info.fb_offset;
return;
}

6
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
View File

@ -59,9 +59,9 @@ static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub,
{
uint32_t tmp;
if (dmub->fb_base || dmub->fb_offset) {
*fb_base = dmub->fb_base;
*fb_offset = dmub->fb_offset;
if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
*fb_base = dmub->soc_fb_info.fb_base;
*fb_offset = dmub->soc_fb_info.fb_offset;
return;
}

6
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
View File

@ -65,9 +65,9 @@ static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
{
uint32_t tmp;
if (dmub->fb_base || dmub->fb_offset) {
*fb_base = dmub->fb_base;
*fb_offset = dmub->fb_offset;
if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
*fb_base = dmub->soc_fb_info.fb_base;
*fb_offset = dmub->soc_fb_info.fb_offset;
return;
}

6
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
View File

@ -63,9 +63,9 @@ static void dmub_dcn35_get_fb_base_offset(struct dmub_srv *dmub,
uint32_t tmp;
/*
if (dmub->fb_base || dmub->fb_offset) {
*fb_base = dmub->fb_base;
*fb_offset = dmub->fb_offset;
if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
*fb_base = dmub->soc_fb_info.fb_base;
*fb_offset = dmub->soc_fb_info.fb_offset;
return;
}
*/

6
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
View File

@ -39,9 +39,9 @@ static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub,
{
uint32_t tmp;
if (dmub->fb_base || dmub->fb_offset) {
*fb_base = dmub->fb_base;
*fb_offset = dmub->fb_offset;
if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
*fb_base = dmub->soc_fb_info.fb_base;
*fb_offset = dmub->soc_fb_info.fb_offset;
return;
}

3
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
View File

@ -709,8 +709,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
}
}
dmub->fb_base = params->fb_base;
dmub->fb_offset = params->fb_offset;
memcpy(&dmub->soc_fb_info, &params->soc_fb_info, sizeof(params->soc_fb_info));
dmub->psp_version = params->psp_version;
if (dmub->hw_funcs.reset)