dt-bindings: clock: airoha: Add PHY binding for Serdes port

Add PHY cell property for Serdes port selection. Currently supported only
for Airoha AN7581 SoC, that support up to 4 Serdes port.

The Serdes port can support both PCIe, USB3 or Ethernet mode.

- PCIe1 Serdes can support PCIe or Ethernet mode.
- PCIe2 Serdes can support PCIe or Ethernet mode.
- USB1 Serdes can support USB3 or HSGMII mode.
- USB2 Serdes can support USB3 or PCIe mode.

Add bindings to permit correct reference of the Serdes ports in DT.
Values are just symbolic and enumerates the Serdes port with a specific
number for precise reference.

The available Serdes port can be selected following the dt-binding header
in [2].

[2] <include/dt-bindings/soc/airoha,scu-ssr.h>

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Christian Marangi 2026-09-15 14:52:23 +02:00 committed by Brian Masney
parent 54d0b69039
commit 11952173d8
2 changed files with 32 additions and 3 deletions

View File

@ -23,6 +23,7 @@ description: |
All these identifiers can be found in:
[1]: <include/dt-bindings/clock/en7523-clk.h>.
[2]: <include/dt-bindings/soc/airoha,scu-ssr.h>.
The clocks are provided inside a system controller node.
@ -50,6 +51,12 @@ properties:
description: ID of the controller reset line
const: 1
'#phy-cells':
description:
The first cell indicates the serdes phy number, see [2] for the
available serdes port.
const: 1
required:
- compatible
- reg
@ -65,12 +72,23 @@ allOf:
reg:
minItems: 2
'#phy-cells': false
- if:
properties:
compatible:
enum:
- airoha,en7581-scu
- econet,en751221-scu
const: econet,en751221-scu
then:
properties:
reg:
maxItems: 1
'#phy-cells': false
- if:
properties:
compatible:
const: airoha,en7581-scu
then:
properties:
reg:

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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef __DT_BINDINGS_AIROHA_SCU_SSR_H
#define __DT_BINDINGS_AIROHA_SCU_SSR_H
#define AIROHA_SCU_SERDES_PCIE1 0
#define AIROHA_SCU_SERDES_PCIE2 1
#define AIROHA_SCU_SERDES_USB1 2
#define AIROHA_SCU_SERDES_USB2 3
#endif /* __DT_BINDINGS_AIROHA_SCU_SSR_H */