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drm/amd/pm: Expose smu_v13_0_6 caps
Expose smu_v13_0_6 caps by moving it to common header Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -101,24 +101,6 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
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#define MCA_BANK_IPID(_ip, _hwid, _type) \
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[AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
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#define SMU_CAP(x) SMU_13_0_6_CAPS_##x
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enum smu_v13_0_6_caps {
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SMU_CAP(DPM),
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SMU_CAP(DPM_POLICY),
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SMU_CAP(OTHER_END_METRICS),
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SMU_CAP(SET_UCLK_MAX),
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SMU_CAP(PCIE_METRICS),
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SMU_CAP(MCA_DEBUG_MODE),
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SMU_CAP(PER_INST_METRICS),
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SMU_CAP(CTF_LIMIT),
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SMU_CAP(RMA_MSG),
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SMU_CAP(ACA_SYND),
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SMU_CAP(SDMA_RESET),
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SMU_CAP(STATIC_METRICS),
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SMU_CAP(ALL),
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};
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struct mca_bank_ipid {
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enum amdgpu_mca_ip ip;
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uint16_t hwid;
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@ -299,8 +281,8 @@ static inline void smu_v13_0_6_cap_clear(struct smu_context *smu,
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dpm_context->caps &= ~BIT_ULL(cap);
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}
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static inline bool smu_v13_0_6_cap_supported(struct smu_context *smu,
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enum smu_v13_0_6_caps cap)
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bool smu_v13_0_6_cap_supported(struct smu_context *smu,
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enum smu_v13_0_6_caps cap)
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{
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struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
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@ -26,6 +26,7 @@
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#define SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL 0x2
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#define SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL 0x4
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#define SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL 0x2
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#define SMU_CAP(x) SMU_13_0_6_CAPS_##x
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typedef enum {
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/*0*/ METRICS_VERSION_V0 = 0,
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@ -51,6 +52,23 @@ struct PPTable_t {
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bool Init;
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};
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enum smu_v13_0_6_caps {
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SMU_CAP(DPM),
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SMU_CAP(DPM_POLICY),
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SMU_CAP(OTHER_END_METRICS),
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SMU_CAP(SET_UCLK_MAX),
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SMU_CAP(PCIE_METRICS),
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SMU_CAP(MCA_DEBUG_MODE),
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SMU_CAP(PER_INST_METRICS),
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SMU_CAP(CTF_LIMIT),
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SMU_CAP(RMA_MSG),
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SMU_CAP(ACA_SYND),
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SMU_CAP(SDMA_RESET),
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SMU_CAP(STATIC_METRICS),
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SMU_CAP(ALL),
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};
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extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu);
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bool smu_v13_0_6_cap_supported(struct smu_context *smu, enum smu_v13_0_6_caps cap);
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#endif
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