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drm/amdgpu/userq: add a helper to check which IPs are enabled

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Add a helper to get a mask of IPs which support user queues.
Use this in the INFO IOCTL to get the IP mask to replace
the current code.

Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2025-04-16 16:43:52 -04:00
parent 4b27406380
commit 11772eb73b
3 changed files with 16 additions and 6 deletions
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7
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View File

@ -1009,12 +1009,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
}
}
if (adev->userq_funcs[AMDGPU_HW_IP_GFX])
dev_info->userq_ip_mask |= (1 << AMDGPU_HW_IP_GFX);
if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE])
dev_info->userq_ip_mask |= (1 << AMDGPU_HW_IP_COMPUTE);
if (adev->userq_funcs[AMDGPU_HW_IP_DMA])
dev_info->userq_ip_mask |= (1 << AMDGPU_HW_IP_DMA);
dev_info->userq_ip_mask = amdgpu_userqueue_get_supported_ip_mask(adev);
ret = copy_to_user(out, dev_info,
min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;

13
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
View File

@ -31,6 +31,19 @@
#include "amdgpu_userqueue.h"
#include "amdgpu_userq_fence.h"
u32 amdgpu_userqueue_get_supported_ip_mask(struct amdgpu_device *adev)
{
int i;
u32 userq_ip_mask = 0;
for (i = 0; i < AMDGPU_HW_IP_NUM; i++) {
if (adev->userq_funcs[i])
userq_ip_mask |= (1 << i);
}
return userq_ip_mask;
}
static void
amdgpu_userqueue_cleanup(struct amdgpu_userq_mgr *uq_mgr,
struct amdgpu_usermode_queue *queue,

2
drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.h
View File

@ -113,6 +113,8 @@ uint64_t amdgpu_userqueue_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr,
struct amdgpu_db_info *db_info,
struct drm_file *filp);
u32 amdgpu_userqueue_get_supported_ip_mask(struct amdgpu_device *adev);
int amdgpu_userq_suspend(struct amdgpu_device *adev);
int amdgpu_userq_resume(struct amdgpu_device *adev);