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net: hip04: use 16-bit byte order for HI13X1 TX fields
The HI13X1 TX descriptor stores send_size and data_offset in 16-bit fields, unlike the 32-bit send_size field in the other descriptor layout. The transmit path nevertheless converts both HI13X1 fields with cpu_to_be32() before assigning them to u16 members. On a little-endian CPU, the conversion moves these small values into the upper half of the 32-bit result and the assignment discards that half. The descriptor consequently loses the packet size and cache-line offset. Use cpu_to_be16() for the two HI13X1 fields. Leave the other layout's 32-bit size conversion unchanged. The issue was found by our static-analysis tool. Cc: stable+noautosel@kernel.org # untested fix for ancient HW Reviewed-by: Simon Horman <horms@kernel.org> Reviewed-by: Jijie Shao <shaojijie@huawei.com> Signed-off-by: Pengpeng Hou <hppiscas@163.com> Link: https://patch.msgid.link/20260920033641.13590-1-hppiscas@163.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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@ -527,13 +527,14 @@ hip04_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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priv->tx_skb[tx_head] = skb;
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priv->tx_phys[tx_head] = phys;
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desc->send_size = (__force u32)cpu_to_be32(skb->len);
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#if defined(CONFIG_HI13X1_GMAC)
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desc->send_size = (__force u16)cpu_to_be16(skb->len);
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desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB | TX_FINISH_CACHE_INV
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| TX_RELEASE_TO_PPE | priv->port << TX_POOL_SHIFT);
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desc->data_offset = (__force u32)cpu_to_be32(phys & SOC_CACHE_LINE_MASK);
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desc->data_offset = (__force u16)cpu_to_be16(phys & SOC_CACHE_LINE_MASK);
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desc->send_addr = (__force u32)cpu_to_be32(phys & ~SOC_CACHE_LINE_MASK);
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#else
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desc->send_size = (__force u32)cpu_to_be32(skb->len);
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desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB | TX_FINISH_CACHE_INV);
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desc->send_addr = (__force u32)cpu_to_be32(phys);
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#endif
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