mirror of
https://github.com/torvalds/linux.git
synced 2026-07-31 11:37:06 +02:00
drm/amd/display: Fix dml2_0 narrowing boundaries
[Why] drm/amd/display dml2_0 code had implicit narrowing conversions reported by a warning in timing, watermark, and translation paths. [How] Apply explicit boundary casts for intentional narrowing, preserve wider intermediate math, and use wider timing intermediates where required for safe range handling. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Gaghik Khachatrian
Alex Deucher
parent
a4702db211
commit
11236ac905
|
|
@ -1119,10 +1119,10 @@ static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st *
|
|||
if (p->myPipe->Dppclk == 0.0 || p->myPipe->Dispclk == 0.0)
|
||||
return true;
|
||||
|
||||
*p->DSTXAfterScaler = (dml_uint_t) dml_round(s->DPPCycles * p->myPipe->PixelClock / p->myPipe->Dppclk + s->DISPCLKCycles * p->myPipe->PixelClock / p->myPipe->Dispclk + p->DSCDelay, 1.0);
|
||||
*p->DSTXAfterScaler = (dml_uint_t) dml_round(s->DPPCycles * p->myPipe->PixelClock / p->myPipe->Dppclk + s->DISPCLKCycles * p->myPipe->PixelClock / p->myPipe->Dispclk + p->DSCDelay, true);
|
||||
*p->DSTXAfterScaler = (dml_uint_t) dml_round(*p->DSTXAfterScaler + (p->myPipe->ODMMode != dml_odm_mode_bypass ? 18 : 0) + (p->myPipe->DPPPerSurface - 1) * p->DPP_RECOUT_WIDTH +
|
||||
((p->myPipe->ODMMode == dml_odm_mode_split_1to2 || p->myPipe->ODMMode == dml_odm_mode_mso_1to2) ? (dml_float_t)p->myPipe->HActive / 2.0 : 0) +
|
||||
((p->myPipe->ODMMode == dml_odm_mode_mso_1to4) ? (dml_float_t)p->myPipe->HActive * 3.0 / 4.0 : 0), 1.0);
|
||||
((p->myPipe->ODMMode == dml_odm_mode_mso_1to4) ? (dml_float_t)p->myPipe->HActive * 3.0 / 4.0 : 0), true);
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: DPPCycles = %u\n", __func__, s->DPPCycles);
|
||||
|
|
@ -4301,7 +4301,7 @@ static void CalculateSwathAndDETConfiguration(struct display_mode_lib_scratch_st
|
|||
|
||||
*p->compbuf_reserved_space_64b = 2 * p->PixelChunkSizeInKByte * 1024 / 64;
|
||||
if (*p->UnboundedRequestEnabled) {
|
||||
*p->compbuf_reserved_space_64b = dml_max(*p->compbuf_reserved_space_64b,
|
||||
*p->compbuf_reserved_space_64b = (dml_uint_t)dml_max(*p->compbuf_reserved_space_64b,
|
||||
(dml_float_t)(p->ROBBufferSizeInKByte * 1024/64)
|
||||
- (dml_float_t)(RoundedUpSwathSizeBytesY[SurfaceDoingUnboundedRequest] * TTUFIFODEPTH / MAXIMUMCOMPRESSION/64));
|
||||
}
|
||||
|
|
@ -6178,9 +6178,9 @@ static void CalculateImmediateFlipBandwithSupport(
|
|||
|
||||
static dml_uint_t MicroSecToVertLines(dml_uint_t num_us, dml_uint_t h_total, dml_float_t pixel_clock)
|
||||
{
|
||||
dml_uint_t lines_time_in_ns = 1000.0 * (h_total * 1000.0) / (pixel_clock * 1000.0);
|
||||
dml_uint_t lines_time_in_ns = (dml_uint_t)(1000.0 * (h_total * 1000.0) / (pixel_clock * 1000.0));
|
||||
|
||||
return dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0);
|
||||
return (dml_uint_t)dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0);
|
||||
}
|
||||
|
||||
/// @brief Calculate the maximum vstartup for mode support and mode programming consideration
|
||||
|
|
@ -6207,9 +6207,9 @@ static dml_uint_t CalculateMaxVStartup(
|
|||
// + 2 is because
|
||||
// 1 -> VStartup_start should be 1 line before VSync
|
||||
// 1 -> always reserve 1 line between start of VBlank to VStartup signal
|
||||
dml_uint_t vblank_nom_vsync_capped = dml_max(vblank_nom_input,
|
||||
dml_uint_t vblank_nom_vsync_capped = (dml_uint_t)dml_max(vblank_nom_input,
|
||||
timing->VTotal[plane_idx] - timing->VActive[plane_idx] - timing->VFrontPorch[plane_idx] + 2);
|
||||
dml_uint_t vblank_nom_max_allowed_capped = dml_min(vblank_nom_vsync_capped, max_allowed_vblank_nom);
|
||||
dml_uint_t vblank_nom_max_allowed_capped = (dml_uint_t)dml_min(vblank_nom_vsync_capped, max_allowed_vblank_nom);
|
||||
dml_uint_t vblank_avail = (vblank_nom_max_allowed_capped == 0) ?
|
||||
vblank_nom_default_in_line : vblank_nom_max_allowed_capped;
|
||||
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ static inline float dcn_bw_pow(float a, float exp)
|
|||
/*ASSERT(exp == (int)exp);*/
|
||||
if ((int)exp == 0)
|
||||
return 1;
|
||||
temp = dcn_bw_pow(a, (int)(exp / 2));
|
||||
temp = dcn_bw_pow(a, (float)(exp / 2));
|
||||
if (((int)exp % 2) == 0) {
|
||||
return temp * temp;
|
||||
} else {
|
||||
|
|
@ -110,7 +110,7 @@ dml_float_t dml_ceil(dml_float_t x, dml_float_t granularity)
|
|||
if (granularity == 0)
|
||||
return 0;
|
||||
//return (dml_float_t) (ceil(x / granularity) * granularity);
|
||||
return (dml_float_t)dcn_bw_ceil2(x, granularity);
|
||||
return (dml_float_t)dcn_bw_ceil2((float)x, (float)granularity);
|
||||
}
|
||||
|
||||
dml_float_t dml_floor(dml_float_t x, dml_float_t granularity)
|
||||
|
|
@ -118,7 +118,7 @@ dml_float_t dml_floor(dml_float_t x, dml_float_t granularity)
|
|||
if (granularity == 0)
|
||||
return 0;
|
||||
//return (dml_float_t) (floor(x / granularity) * granularity);
|
||||
return (dml_float_t)dcn_bw_floor2(x, granularity);
|
||||
return (dml_float_t)dcn_bw_floor2((float)x, (float)granularity);
|
||||
}
|
||||
|
||||
dml_float_t dml_min(dml_float_t x, dml_float_t y)
|
||||
|
|
@ -168,12 +168,12 @@ dml_float_t dml_max5(dml_float_t a, dml_float_t b, dml_float_t c, dml_float_t d,
|
|||
}
|
||||
dml_float_t dml_log(dml_float_t x, dml_float_t base)
|
||||
{
|
||||
return (dml_float_t) (_log(x) / _log(base));
|
||||
return (dml_float_t) (_log((float)x) / _log((float)base));
|
||||
}
|
||||
|
||||
dml_float_t dml_log2(dml_float_t x)
|
||||
{
|
||||
return (dml_float_t) (_log(x) / _log(2));
|
||||
return (dml_float_t) (_log((float)x) / _log(2.0f));
|
||||
}
|
||||
|
||||
dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding)
|
||||
|
|
@ -184,19 +184,19 @@ dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding)
|
|||
// else {
|
||||
// return round(val);
|
||||
double round_pt = 0.5;
|
||||
double ceil = dml_ceil(val, 1);
|
||||
double floor = dml_floor(val, 1);
|
||||
double ceil = dml_ceil(val, 1.0);
|
||||
double floor = dml_floor(val, 1.0);
|
||||
|
||||
if (val - floor >= round_pt)
|
||||
return ceil;
|
||||
return (dml_float_t)ceil;
|
||||
else
|
||||
return floor;
|
||||
return (dml_float_t)floor;
|
||||
// }
|
||||
}
|
||||
|
||||
dml_float_t dml_pow(dml_float_t base, int exp)
|
||||
{
|
||||
return (dml_float_t) dcn_bw_pow(base, exp);
|
||||
return (dml_float_t) dcn_bw_pow((float)base, (float)exp);
|
||||
}
|
||||
|
||||
dml_uint_t dml_round_to_multiple(dml_uint_t num, dml_uint_t multiple, dml_bool_t up)
|
||||
|
|
|
|||
|
|
@ -851,10 +851,10 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state
|
|||
context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.socclk_khz;
|
||||
context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz;
|
||||
context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;
|
||||
context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;
|
||||
context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;
|
||||
context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency;
|
||||
context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period;
|
||||
context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;
|
||||
context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;
|
||||
context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency;
|
||||
context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = (int)in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period;
|
||||
context->bw_ctx.bw.dcn.clk.zstate_support = in_ctx->v21.mode_programming.programming->z8_stutter.supported_in_blank; /*ignore meets_eco since it is not used*/
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -267,7 +267,7 @@ static struct dc_stream_state *dml21_add_phantom_stream(struct dml2_context *dml
|
|||
phantom_stream->dst.height = stream_programming->phantom_stream.descriptor.timing.v_active;
|
||||
|
||||
phantom_stream->src.y = 0;
|
||||
phantom_stream->src.height = (double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height;
|
||||
phantom_stream->src.height = (int)((double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height);
|
||||
|
||||
phantom_stream->use_dynamic_meta = false;
|
||||
|
||||
|
|
|
|||
|
|
@ -244,9 +244,9 @@ static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context
|
|||
continue;
|
||||
|
||||
// Round up
|
||||
refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
|
||||
refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 +
|
||||
pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
|
||||
/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
|
||||
/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total));
|
||||
/* SubVP pipe candidate requirements:
|
||||
* - Refresh rate < 120hz
|
||||
* - Not able to switch in vactive naturally (switching in active means the
|
||||
|
|
@ -264,8 +264,8 @@ static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context
|
|||
pipe = &context->res_ctx.pipe_ctx[i];
|
||||
if (num_pipes <= free_pipes) {
|
||||
struct dc_stream_state *stream = pipe->stream;
|
||||
unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
|
||||
(double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
|
||||
unsigned int frame_us = (unsigned int)((stream->timing.v_total * stream->timing.h_total /
|
||||
(double)(stream->timing.pix_clk_100hz * 100)) * 1000000);
|
||||
if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) {
|
||||
*index = i;
|
||||
max_frame_time = frame_us;
|
||||
|
|
@ -382,8 +382,8 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c
|
|||
phantom->timing.v_addressable;
|
||||
|
||||
// Round up when calculating microschedule time (+ 1 at the end)
|
||||
time_us = (microschedule_lines * phantom->timing.h_total) /
|
||||
(double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
|
||||
time_us = (uint32_t)((microschedule_lines * phantom->timing.h_total) /
|
||||
(double)(phantom->timing.pix_clk_100hz * 100) * 1000000) +
|
||||
ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us +
|
||||
ctx->config.svp_pstate.subvp_fw_processing_delay_us + 1;
|
||||
if (time_us > max_microschedule_us)
|
||||
|
|
@ -402,16 +402,16 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c
|
|||
if (index < 2 || !subvp_pipes[0] || !subvp_pipes[1])
|
||||
return false;
|
||||
|
||||
vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
|
||||
(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
|
||||
vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
|
||||
(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
|
||||
vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
|
||||
vactive1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
|
||||
(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000);
|
||||
vactive2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
|
||||
(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000);
|
||||
vblank1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
|
||||
subvp_pipes[0]->stream->timing.h_total) /
|
||||
(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
|
||||
vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
|
||||
(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100) * 1000000);
|
||||
vblank2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
|
||||
subvp_pipes[1]->stream->timing.h_total) /
|
||||
(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
|
||||
(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100) * 1000000);
|
||||
|
||||
if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
|
||||
(vactive2_us - vblank1_us) / 2 > max_microschedule_us)
|
||||
|
|
@ -445,13 +445,13 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context
|
|||
struct dc_crtc_timing *main_timing = NULL;
|
||||
struct dc_crtc_timing *phantom_timing = NULL;
|
||||
struct dc_stream_state *phantom_stream;
|
||||
int16_t prefetch_us = 0;
|
||||
int16_t mall_region_us = 0;
|
||||
int16_t drr_frame_us = 0; // nominal frame time
|
||||
int16_t subvp_active_us = 0;
|
||||
int16_t stretched_drr_us = 0;
|
||||
int16_t drr_stretched_vblank_us = 0;
|
||||
int16_t max_vblank_mallregion = 0;
|
||||
int32_t prefetch_us = 0;
|
||||
int32_t mall_region_us = 0;
|
||||
int32_t drr_frame_us = 0; // nominal frame time
|
||||
int32_t subvp_active_us = 0;
|
||||
int32_t stretched_drr_us = 0;
|
||||
int32_t drr_stretched_vblank_us = 0;
|
||||
int32_t max_vblank_mallregion = 0;
|
||||
|
||||
// Find SubVP pipe
|
||||
for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
|
||||
|
|
@ -475,19 +475,19 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context
|
|||
phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream);
|
||||
main_timing = &pipe->stream->timing;
|
||||
phantom_timing = &phantom_stream->timing;
|
||||
prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
|
||||
prefetch_us = (int32_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
|
||||
(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
|
||||
ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us;
|
||||
subvp_active_us = main_timing->v_addressable * main_timing->h_total /
|
||||
(double)(main_timing->pix_clk_100hz * 100) * 1000000;
|
||||
drr_frame_us = drr_timing->v_total * drr_timing->h_total /
|
||||
(double)(drr_timing->pix_clk_100hz * 100) * 1000000;
|
||||
ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us);
|
||||
subvp_active_us = (int32_t)(main_timing->v_addressable * main_timing->h_total /
|
||||
(double)(main_timing->pix_clk_100hz * 100) * 1000000);
|
||||
drr_frame_us = (int32_t)(drr_timing->v_total * drr_timing->h_total /
|
||||
(double)(drr_timing->pix_clk_100hz * 100) * 1000000);
|
||||
// P-State allow width and FW delays already included phantom_timing->v_addressable
|
||||
mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
|
||||
(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
|
||||
mall_region_us = (int32_t)(phantom_timing->v_addressable * phantom_timing->h_total /
|
||||
(double)(phantom_timing->pix_clk_100hz * 100) * 1000000);
|
||||
stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
|
||||
drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
|
||||
(double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
|
||||
drr_stretched_vblank_us = (int32_t)((drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
|
||||
(double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us));
|
||||
max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
|
||||
|
||||
/* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
|
||||
|
|
@ -526,12 +526,12 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *
|
|||
bool schedulable = false;
|
||||
uint32_t i = 0;
|
||||
uint8_t vblank_index = 0;
|
||||
uint16_t prefetch_us = 0;
|
||||
uint16_t mall_region_us = 0;
|
||||
uint16_t vblank_frame_us = 0;
|
||||
uint16_t subvp_active_us = 0;
|
||||
uint16_t vblank_blank_us = 0;
|
||||
uint16_t max_vblank_mallregion = 0;
|
||||
uint32_t prefetch_us = 0;
|
||||
uint32_t mall_region_us = 0;
|
||||
uint32_t vblank_frame_us = 0;
|
||||
uint32_t subvp_active_us = 0;
|
||||
uint32_t vblank_blank_us = 0;
|
||||
uint32_t max_vblank_mallregion = 0;
|
||||
struct dc_crtc_timing *main_timing = NULL;
|
||||
struct dc_crtc_timing *phantom_timing = NULL;
|
||||
struct dc_crtc_timing *vblank_timing = NULL;
|
||||
|
|
@ -581,18 +581,18 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *
|
|||
vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
|
||||
// Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
|
||||
// Also include the prefetch end to mallstart delay time
|
||||
prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
|
||||
prefetch_us = (uint32_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
|
||||
(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
|
||||
ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us;
|
||||
ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us);
|
||||
// P-State allow width and FW delays already included phantom_timing->v_addressable
|
||||
mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
|
||||
(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
|
||||
vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
|
||||
(double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
|
||||
vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
|
||||
(double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
|
||||
subvp_active_us = main_timing->v_addressable * main_timing->h_total /
|
||||
(double)(main_timing->pix_clk_100hz * 100) * 1000000;
|
||||
mall_region_us = (uint32_t)(phantom_timing->v_addressable * phantom_timing->h_total /
|
||||
(double)(phantom_timing->pix_clk_100hz * 100) * 1000000);
|
||||
vblank_frame_us = (uint32_t)(vblank_timing->v_total * vblank_timing->h_total /
|
||||
(double)(vblank_timing->pix_clk_100hz * 100) * 1000000);
|
||||
vblank_blank_us = (uint32_t)((vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
|
||||
(double)(vblank_timing->pix_clk_100hz * 100) * 1000000);
|
||||
subvp_active_us = (uint32_t)(main_timing->v_addressable * main_timing->h_total /
|
||||
(double)(main_timing->pix_clk_100hz * 100) * 1000000);
|
||||
max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
|
||||
|
||||
// Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
|
||||
|
|
@ -694,10 +694,10 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state
|
|||
}
|
||||
|
||||
// Calculate lines required for pstate allow width and FW processing delays
|
||||
pstate_width_fw_delay_lines = ((double)(ctx->config.svp_pstate.subvp_fw_processing_delay_us +
|
||||
pstate_width_fw_delay_lines = (uint32_t)(((double)(ctx->config.svp_pstate.subvp_fw_processing_delay_us +
|
||||
ctx->config.svp_pstate.subvp_pstate_allow_width_us) / 1000000) *
|
||||
(ref_pipe->stream->timing.pix_clk_100hz * 100) /
|
||||
(double)ref_pipe->stream->timing.h_total;
|
||||
(double)ref_pipe->stream->timing.h_total);
|
||||
|
||||
// DML calculation for MALL region doesn't take into account FW delay
|
||||
// and required pstate allow width for multi-display cases
|
||||
|
|
@ -712,7 +712,7 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state
|
|||
fp_and_sync_width_time = (phantom_stream->timing.v_front_porch + phantom_stream->timing.v_sync_width) * line_time;
|
||||
|
||||
if ((svp_vstartup * line_time) + fp_and_sync_width_time > cvt_rb_vblank_max) {
|
||||
svp_vstartup = (cvt_rb_vblank_max - fp_and_sync_width_time) / line_time;
|
||||
svp_vstartup = (unsigned int)((cvt_rb_vblank_max - fp_and_sync_width_time) / line_time);
|
||||
}
|
||||
|
||||
// For backporch of phantom pipe, use vstartup of the main pipe
|
||||
|
|
|
|||
|
|
@ -123,9 +123,9 @@ int dml2_policy_build_synthetic_soc_states(struct dml2_policy_build_synthetic_so
|
|||
struct dml2_policy_build_synthetic_soc_states_params *p)
|
||||
{
|
||||
int i, j;
|
||||
unsigned int min_fclk_mhz = p->in_states->state_array[0].fabricclk_mhz;
|
||||
unsigned int min_dcfclk_mhz = p->in_states->state_array[0].dcfclk_mhz;
|
||||
unsigned int min_socclk_mhz = p->in_states->state_array[0].socclk_mhz;
|
||||
unsigned int min_fclk_mhz = (unsigned int)p->in_states->state_array[0].fabricclk_mhz;
|
||||
unsigned int min_dcfclk_mhz = (unsigned int)p->in_states->state_array[0].dcfclk_mhz;
|
||||
unsigned int min_socclk_mhz = (unsigned int)p->in_states->state_array[0].socclk_mhz;
|
||||
|
||||
int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
|
||||
max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0,
|
||||
|
|
|
|||
|
|
@ -508,11 +508,11 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
|
|||
/* DCFCLK stas values are project specific */
|
||||
if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) ||
|
||||
(dml2->v20.dml_core_ctx.project == dml_project_dcn321)) {
|
||||
p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz;
|
||||
p->dcfclk_stas_mhz[0] = (int)p->in_states->state_array[0].dcfclk_mhz;
|
||||
p->dcfclk_stas_mhz[1] = 615;
|
||||
p->dcfclk_stas_mhz[2] = 906;
|
||||
p->dcfclk_stas_mhz[3] = 1324;
|
||||
p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz;
|
||||
p->dcfclk_stas_mhz[4] = (int)p->in_states->state_array[1].dcfclk_mhz;
|
||||
} else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
|
||||
dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&
|
||||
dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
|
||||
|
|
|
|||
|
|
@ -333,7 +333,7 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont
|
|||
}
|
||||
|
||||
context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb;
|
||||
context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000;
|
||||
context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = (int)(dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000);
|
||||
if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz)
|
||||
context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz;
|
||||
|
||||
|
|
@ -362,10 +362,10 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont
|
|||
context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
|
||||
context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
|
||||
|
||||
context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz
|
||||
* 1000;
|
||||
context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz
|
||||
* 1000;
|
||||
context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = (int)(in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz
|
||||
* 1000);
|
||||
context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = (int)(in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz
|
||||
* 1000);
|
||||
|
||||
if (dc->config.forced_clocks || dc->debug.max_disp_clk) {
|
||||
context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
|
||||
|
|
@ -375,18 +375,18 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont
|
|||
|
||||
void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx)
|
||||
{
|
||||
watermark->urgent_ns = dml_get_wm_urgent(dml_core_ctx) * 1000;
|
||||
watermark->cstate_pstate.cstate_enter_plus_exit_ns = dml_get_wm_stutter_enter_exit(dml_core_ctx) * 1000;
|
||||
watermark->cstate_pstate.cstate_exit_ns = dml_get_wm_stutter_exit(dml_core_ctx) * 1000;
|
||||
watermark->cstate_pstate.pstate_change_ns = dml_get_wm_dram_clock_change(dml_core_ctx) * 1000;
|
||||
watermark->pte_meta_urgent_ns = dml_get_wm_memory_trip(dml_core_ctx) * 1000;
|
||||
watermark->frac_urg_bw_nom = dml_get_fraction_of_urgent_bandwidth(dml_core_ctx) * 1000;
|
||||
watermark->frac_urg_bw_flip = dml_get_fraction_of_urgent_bandwidth_imm_flip(dml_core_ctx) * 1000;
|
||||
watermark->urgent_latency_ns = dml_get_urgent_latency(dml_core_ctx) * 1000;
|
||||
watermark->cstate_pstate.fclk_pstate_change_ns = dml_get_wm_fclk_change(dml_core_ctx) * 1000;
|
||||
watermark->usr_retraining_ns = dml_get_wm_usr_retraining(dml_core_ctx) * 1000;
|
||||
watermark->cstate_pstate.cstate_enter_plus_exit_z8_ns = dml_get_wm_z8_stutter_enter_exit(dml_core_ctx) * 1000;
|
||||
watermark->cstate_pstate.cstate_exit_z8_ns = dml_get_wm_z8_stutter(dml_core_ctx) * 1000;
|
||||
watermark->urgent_ns = (uint32_t)(dml_get_wm_urgent(dml_core_ctx) * 1000);
|
||||
watermark->cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(dml_get_wm_stutter_enter_exit(dml_core_ctx) * 1000);
|
||||
watermark->cstate_pstate.cstate_exit_ns = (uint32_t)(dml_get_wm_stutter_exit(dml_core_ctx) * 1000);
|
||||
watermark->cstate_pstate.pstate_change_ns = (uint32_t)(dml_get_wm_dram_clock_change(dml_core_ctx) * 1000);
|
||||
watermark->pte_meta_urgent_ns = (uint32_t)(dml_get_wm_memory_trip(dml_core_ctx) * 1000);
|
||||
watermark->frac_urg_bw_nom = (uint32_t)(dml_get_fraction_of_urgent_bandwidth(dml_core_ctx) * 1000);
|
||||
watermark->frac_urg_bw_flip = (uint32_t)(dml_get_fraction_of_urgent_bandwidth_imm_flip(dml_core_ctx) * 1000);
|
||||
watermark->urgent_latency_ns = (uint32_t)(dml_get_urgent_latency(dml_core_ctx) * 1000);
|
||||
watermark->cstate_pstate.fclk_pstate_change_ns = (uint32_t)(dml_get_wm_fclk_change(dml_core_ctx) * 1000);
|
||||
watermark->usr_retraining_ns = (uint32_t)(dml_get_wm_usr_retraining(dml_core_ctx) * 1000);
|
||||
watermark->cstate_pstate.cstate_enter_plus_exit_z8_ns = (uint32_t)(dml_get_wm_z8_stutter_enter_exit(dml_core_ctx) * 1000);
|
||||
watermark->cstate_pstate.cstate_exit_z8_ns = (uint32_t)(dml_get_wm_z8_stutter(dml_core_ctx) * 1000);
|
||||
}
|
||||
|
||||
unsigned int dml2_calc_max_scaled_time(
|
||||
|
|
@ -434,9 +434,9 @@ void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib
|
|||
for (j = 0 ; j < 4; j++) {
|
||||
/*current dml only has one set of watermark, need to follow up*/
|
||||
bw_writeback->mcif_wb_arb[i].cli_watermark[j] =
|
||||
dml_get_wm_writeback_urgent(dml_core_ctx) * 1000;
|
||||
(unsigned int)(dml_get_wm_writeback_urgent(dml_core_ctx) * 1000);
|
||||
bw_writeback->mcif_wb_arb[i].pstate_watermark[j] =
|
||||
dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000;
|
||||
(unsigned int)(dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000);
|
||||
}
|
||||
if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) {
|
||||
/* time_per_pixel should be in u6.6 format */
|
||||
|
|
@ -450,7 +450,7 @@ void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib
|
|||
wbif_mode, wb_arb_params->cli_watermark[0]);
|
||||
/*not required any more*/
|
||||
bw_writeback->mcif_wb_arb[i].dram_speed_change_duration =
|
||||
dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000;
|
||||
(unsigned int)(dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000);
|
||||
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user