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a22:uart:add uart busy judgement before set the baud rate
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hhb
root
parent
a452030b6a
commit
10e078ae1a
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@ -56,9 +56,6 @@
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#define UART_USR 0x1F /* UART Status Register */
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#define UART_USR_BUSY (1)
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#define UART_IER_PTIME 0x80 /* Programmable THRE Interrupt Mode Enable */
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#define UART_LSR_RFE 0x80 /* receive fifo error */
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#define RX_TIMEOUT (3000*10) //uint ms
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#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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@ -106,9 +103,9 @@ static struct uart_driver serial_rk_reg;
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#define uart_console(port) (0)
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#endif
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#define DEBUG 0
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#ifdef DEBUG
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extern void printascii(const char *);
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static void dbg(const char *fmt, ...)
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{
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va_list va;
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@ -121,7 +118,6 @@ static void dbg(const char *fmt, ...)
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printascii(buff);
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}
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#if DEBUG
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#define DEBUG_INTR(fmt...) if (!uart_console(&up->port)) dbg(fmt)
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#else
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#define DEBUG_INTR(fmt...) do { } while (0)
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@ -236,28 +232,26 @@ static inline void serial_dl_write(struct uart_rk_port *up, unsigned int value)
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serial_out(up, UART_DLM, value >> 8 & 0xff);
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}
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static int serial_lcr_write(struct uart_rk_port *up, unsigned char value)
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static void serial_lcr_write(struct uart_rk_port *up, unsigned char value)
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{
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unsigned int tmout = 10000;
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unsigned char lcr;
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lcr = serial_in(up, UART_LCR);
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if (lcr == value)
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return -1;
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while(serial_in(up, UART_USR) & UART_USR_BUSY){
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unsigned int tmout = 15000;
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for (;;) {
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unsigned char lcr;
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serial_out(up, UART_LCR, value);
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lcr = serial_in(up, UART_LCR);
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if (lcr == value)
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break;
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/* Read the USR to clear any busy interrupts */
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serial_in(up, UART_USR);
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serial_in(up, UART_RX);
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if (--tmout == 0){
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dbg("set serial.%d lcr timeout\n", up->port.line);
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return -1;
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dev_info(up->port.dev, "set lcr timeout\n");
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break;
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}
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udelay(1);
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}
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if (tmout != 0){
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serial_out(up, UART_LCR, value);
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}
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return 0;
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}
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static inline void serial_rk_enable_ier_thri(struct uart_rk_port *up)
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@ -277,26 +271,6 @@ static inline void serial_rk_disable_ier_thri(struct uart_rk_port *up)
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}
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}
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static int rk29_uart_dump_register(struct uart_rk_port *up){
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unsigned int reg_value = 0;
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reg_value = serial_in(up, UART_IER);
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dbg("UART_IER = 0x%0x\n", reg_value);
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reg_value = serial_in(up, UART_IIR);
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dbg("UART_IIR = 0x%0x\n", reg_value);
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// reg_value = serial_in(up, 0X25);
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// dbg("DMA_MODE = 0x%0x\n", reg_value);
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reg_value = serial_in(up, UART_LSR);
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dbg("UART_LSR = 0x%0x\n", reg_value);
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reg_value = serial_in(up, 0x21);
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dbg("UART_RFL = 0x%0x\n", reg_value);
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return 0;
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}
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/*
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* FIFO support.
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*/
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@ -755,9 +729,8 @@ receive_chars(struct uart_rk_port *up, unsigned int *status)
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char flag;
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do {
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if (likely(lsr & UART_LSR_DR)){
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if (likely(lsr & UART_LSR_DR))
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ch = serial_in(up, UART_RX);
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}
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else
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/*
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* Intel 82571 has a Serial Over Lan device that will
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@ -897,14 +870,14 @@ static void serial_rk_handle_port(struct uart_rk_port *up)
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unsigned long flags;
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spin_lock_irqsave(&up->port.lock, flags);
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/* reading UART_LSR can automatically clears PE FE OE bits, except receive fifo error bit*/
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status = serial_in(up, UART_LSR);
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DEBUG_INTR("status = %x...", status);
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/* DMA mode enable */
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if(up->prk29_uart_dma_t->use_dma == 1) {
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if(up->iir & UART_IIR_RLSI){
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if (status & (UART_LSR_DR | UART_LSR_BI)) {
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up->port_activity = jiffies;
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up->ier &= ~UART_IER_RLSI;
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@ -912,28 +885,21 @@ static void serial_rk_handle_port(struct uart_rk_port *up)
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serial_out(up, UART_IER, up->ier);
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//receive_chars(up, &status);
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//mod_timer(&up->prk29_uart_dma_t->rx_timer, jiffies +
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//msecs_to_jiffies(up->prk29_uart_dma_t->rx_timeout));
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//msecs_to_jiffies(up->prk29_uart_dma_t->rx_timeout));
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if(serial_rk_start_rx_dma(&up->port) == -1){
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receive_chars(up, &status);
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}
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}
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}
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/*
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if (status & UART_LSR_THRE) {
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transmit_chars(up);
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}
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*/
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}else { //dma mode disable
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/*
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* when uart receive a serial of data which doesn't have stop bit and so on, that causes frame error,and
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* set UART_LSR_RFE to one,what is worse,we couldn't read the data in the receive fifo. So if
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* wo don't clear this bit and reset the receive fifo, the received data available interrupt would
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* occur continuously. added by hhb@rock-chips.com 2011-08-05
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*/
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if(status & UART_LSR_RFE){
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dbg("serial.%d LSR = 0x%02x...\n", up->port.line, status);
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serial_out(up, UART_FCR, serial_in(up, UART_FCR) | UART_FCR_CLEAR_RCVR);
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//dsb(); //dsb is an instruction that make sure write the UART_FCR in time
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serial_in(up, UART_RX);
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rk29_uart_dump_register(up);
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}
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if (status & (UART_LSR_DR | UART_LSR_BI)) {
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receive_chars(up, &status);
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}
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@ -958,24 +924,23 @@ static irqreturn_t serial_rk_interrupt(int irq, void *dev_id)
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iir = serial_in(up, UART_IIR);
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DEBUG_INTR("%s(%d) iir = 0x%02x ", __func__, irq, iir);
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up->iir = iir;
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if (!(iir & UART_IIR_NO_INT)) {
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serial_rk_handle_port(up);
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handled = 1;
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} else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
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/* The DesignWare APB UART has an Busy Detect (0x07)
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* interrupt meaning an LCR write attempt occured while the
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* UART was busy. The interrupt must be cleared by reading
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* the UART status register (USR) and the LCR re-written. */
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if(!(serial_in(up, UART_USR) & UART_USR_BUSY)){
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serial_out(up, UART_LCR, up->lcr);
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//serial_out(up, UART_LCR, up->lcr);
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}
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handled = 1;
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dbg("the serial.%d is busy\n", up->port.line);
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dev_info(up->port.dev, "the serial is busy\n");
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}
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DEBUG_INTR("end(%d).\n", handled);
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@ -1154,6 +1119,8 @@ static int serial_rk_startup(struct uart_port *port)
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up->mcr = 0;
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clk_enable(up->clk); // enable the config uart clock
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/*
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* Clear the FIFO buffers and disable them.
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* (they will be reenabled in set_termios())
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@ -1190,11 +1157,11 @@ static int serial_rk_startup(struct uart_port *port)
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* saved flags to avoid getting false values from polling
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* routines or the previous session.
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*/
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(void) serial_in(up, UART_LSR);
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(void) serial_in(up, UART_RX);
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(void) serial_in(up, UART_IIR);
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(void) serial_in(up, UART_MSR);
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(void) serial_in(up, UART_USR);
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serial_in(up, UART_LSR);
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serial_in(up, UART_RX);
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serial_in(up, UART_IIR);
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serial_in(up, UART_MSR);
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serial_in(up, UART_USR);
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up->lsr_saved_flags = 0;
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#if 0
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up->msr_saved_flags = 0;
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@ -1270,7 +1237,7 @@ serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,
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{
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struct uart_rk_port *up =
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container_of(port, struct uart_rk_port, port);
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unsigned char cval, fcr = 0;
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unsigned char cval=0, fcr = 0;
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unsigned long flags, bits;
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unsigned int baud, quot;
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@ -1292,7 +1259,6 @@ serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,
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bits += 7;
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break;
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default:
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case CS8:
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cval = UART_LCR_WLEN8;
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bits += 8;
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break;
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@ -1327,9 +1293,19 @@ serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,
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quot = uart_get_divisor(port, baud);
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// dev_info(up->port.dev, "*****baud:%d*******\n", baud);
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dev_info(up->port.dev, "*****baud:%d*******\n", baud);
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// dev_info(up->port.dev, "*****quot:%d*******\n", quot);
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int timeout = 10000000;
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while(serial_in(up, UART_USR)&UART_USR_BUSY){
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if(timeout-- == 0){
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printk("rk29_serial_set_termios uart timeout,uart%d,ret=0x%x\n",up->port.line,serial_in(up, UART_USR));
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break;
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}
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cpu_relax();
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}
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printk("%s:timeout=%d\n",__FUNCTION__,timeout);
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if (baud < 2400){
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fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
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}
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@ -1356,6 +1332,7 @@ serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,
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up->mcr |= UART_MCR_AFE;
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}
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/*
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* Ok, we're now changing the port state. Do it with
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* interrupts disabled.
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@ -1411,15 +1388,13 @@ serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,
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serial_lcr_write(up, cval); /* reset DLAB */
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up->lcr = cval; /* Save LCR */
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serial_out(up, UART_FCR, fcr); /* set fcr */
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serial_rk_set_mctrl(&up->port, up->port.mctrl);
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/* enable the uart interrupt last */
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serial_out(up, UART_FCR, fcr); /* set fcr */
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up->ier |= UART_IER_RDI;
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up->ier |= UART_IER_RLSI;
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serial_out(up, UART_IER, up->ier);
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spin_unlock_irqrestore(&up->port.lock, flags);
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/* Don't rewrite B0 */
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if (tty_termios_baud_rate(termios))
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@ -1696,7 +1671,7 @@ static int __devinit serial_rk_probe(struct platform_device *pdev)
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goto do_put_clk;
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}
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up->port.mapbase = mem->start;
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up->port.irqflags = IRQF_DISABLED;
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up->port.irqflags = 0;
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up->port.uartclk = clk_get_rate(up->clk);
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/* set dma config */
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