From 10cf797f3f8a50d5ac7a823117e5097b87c7e51d Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Tue, 23 Jun 2026 23:22:02 -0700 Subject: [PATCH] arm64: dts: socfpga: agilex5: Enable the SMMU The SMMU is disabled in socfpga_agilex5.dtsi. The SoC uses a different memory-mapped base address for its peripherals, which requires the SMMU to be active so that the Secure Device Manager (SDM) can correctly access those regions through address translation. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index c936f8db1bd0..153bb22002b5 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -385,7 +385,6 @@ smmu: iommu@16000000 { interrupt-names = "eventq", "gerror", "priq"; dma-coherent; #iommu-cells = <1>; - status = "disabled"; }; spi0: spi@10da4000 {