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Graphics support for the old rk3066-marsboard (hdmi + Mali400 gpu),

Browse Source 
rk3036 improvements (mmc asliases, hdmi refclk), dropping of
 redundant clock-latency props.
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Merge tag 'v6.16-rockchip-dts32-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

Graphics support for the old rk3066-marsboard (hdmi + Mali400 gpu),
rk3036 improvements (mmc asliases, hdmi refclk), dropping of
redundant clock-latency props.

* tag 'v6.16-rockchip-dts32-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: enable Mali gpu on rk3066 marsboard
  ARM: dts: rockchip: enable hdmi on rk3066 marsboard
  Revert "ARM: dts: rockchip: drop grf reference from rk3036 hdmi"
  ARM: dts: rockchip: Add ref clk for hdmi
  ARM: dts: rockchip: Drop redundant CPU "clock-latency"
  ARM: dts: rockchip: Add aliases for rk3036-kylin MMC devices

Link: https://lore.kernel.org/r/22686731.EfDdHjke4D@diego
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-05-09 23:04:33 +02:00
commit 109c5aedf6
8 changed files with 54 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/boot/dts/rockchip/rk3036-kylin.dts
View File

@ -8,6 +8,12 @@ / {
model = "Rockchip RK3036 KylinBoard";
compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdio;
};
chosen {
stdout-path = "serial2:115200n8";
};

5
arch/arm/boot/dts/rockchip/rk3036.dtsi
View File

@ -398,8 +398,9 @@ hdmi: hdmi@20034000 {
compatible = "rockchip,rk3036-inno-hdmi";
reg = <0x20034000 0x4000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI>;
clock-names = "pclk";
clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>;
clock-names = "pclk", "ref";
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
#sound-dai-cells = <0>;

37
arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts
View File

@ -19,6 +19,17 @@ memory@60000000 {
reg = <0x60000000 0x40000000>;
};
hdmi_con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
vdd_log: regulator-vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm3 0 1000>;
@ -58,6 +69,28 @@ &cpu1 {
cpu-supply = <&vdd_arm>;
};
&gpu {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_in_vop1 {
status = "disabled";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
@ -216,6 +249,10 @@ &usb_otg {
status = "okay";
};
&vop0 {
status = "okay";
};
&wdt {
status = "okay";
};

8
arch/arm/boot/dts/rockchip/rk3128.dtsi
View File

@ -48,7 +48,6 @@ cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
resets = <&cru SRST_CORE0>;
operating-points-v2 = <&cpu_opp_table>;
@ -87,31 +86,38 @@ cpu_opp_table: opp-table-0 {
opp-216000000 {
opp-hz = /bits/ 64 <216000000>;
opp-microvolt = <950000 950000 1325000>;
clock-latency-ns = <40000>;
};
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000 950000 1325000>;
clock-latency-ns = <40000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000 950000 1325000>;
clock-latency-ns = <40000>;
};
opp-696000000 {
opp-hz = /bits/ 64 <696000000>;
opp-microvolt = <975000 975000 1325000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1075000 1075000 1325000>;
opp-suspend;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1200000 1200000 1325000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1325000 1325000 1325000>;
clock-latency-ns = <40000>;
};
};

1
arch/arm/boot/dts/rockchip/rk3188.dtsi
View File

@ -23,7 +23,6 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x0>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
resets = <&cru SRST_CORE0>;

1
arch/arm/boot/dts/rockchip/rk322x.dtsi
View File

@ -36,7 +36,6 @@ cpu0: cpu@f00 {
resets = <&cru SRST_CORE0>;
operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
enable-method = "psci";
};

5
arch/arm/boot/dts/rockchip/rk3288.dtsi
View File

@ -70,7 +70,6 @@ cpu0: cpu@500 {
resets = <&cru SRST_CORE0>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
dynamic-power-coefficient = <370>;
};
@ -81,7 +80,6 @@ cpu1: cpu@501 {
resets = <&cru SRST_CORE1>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
dynamic-power-coefficient = <370>;
};
@ -92,7 +90,6 @@ cpu2: cpu@502 {
resets = <&cru SRST_CORE2>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
dynamic-power-coefficient = <370>;
};
@ -103,7 +100,6 @@ cpu3: cpu@503 {
resets = <&cru SRST_CORE3>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
dynamic-power-coefficient = <370>;
};
@ -116,6 +112,7 @@ cpu_opp_table: opp-table-0 {
opp-126000000 {
opp-hz = /bits/ 64 <126000000>;
opp-microvolt = <900000>;
clock-latency-ns = <40000>;
};
opp-216000000 {
opp-hz = /bits/ 64 <216000000>;

1
arch/arm/boot/dts/rockchip/rv1108.dtsi
View File

@ -32,7 +32,6 @@ cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <75>;