mirror of
https://github.com/torvalds/linux.git
synced 2026-05-26 16:12:59 +02:00
Merge branch 'pci/dt-bindings'
- Update socionext,uniphier-pcie binding pcie_intc name to 'legacy-interrupt-controller' to match .dts files (Rob Herring) - Merge SC8180x binding into SM8150 (Krzysztof Kozlowski) - Move SDX55, SDM845, QCS404, IPQ5018, IPQ6018, IPQ8074 Gen3, IPQ8074, IPQ4019, IPQ9574, APQ8064, MSM8996, APQ8084 to dedicated schema (Krzysztof Kozlowski) - Add MT7981 compatible to mediatek-pcie-gen3 binding (Sjoerd Simons) - Document Loongson msi-parent property (Yao Zi) - Add Glymur compatible to qcom,pcie-x1e80100 binding (Prudhvi Yarlagadda) * pci/dt-bindings: dt-bindings: PCI: qcom: Document the Glymur PCIe Controller dt-bindings: PCI: loongson: Document msi-parent property dt-bindings: PCI: mediatek-gen3: Add MT7981 PCIe compatible dt-bindings: PCI: qcom,pcie-apq8084: Move APQ8084 to dedicated schema dt-bindings: PCI: qcom,pcie-msm8996: Move MSM8996 to dedicated schema dt-bindings: PCI: qcom,pcie-apq8064: Move APQ8064 to dedicated schema dt-bindings: PCI: qcom,pcie-ipq9574: Move IPQ9574 to dedicated schema dt-bindings: PCI: qcom,pcie-ipq4019: Move IPQ4019 to dedicated schema dt-bindings: PCI: qcom,pcie-ipq8074: Move IPQ8074 to dedicated schema dt-bindings: PCI: qcom,pcie-ipq6018: Move IPQ6018 and IPQ8074 Gen3 to dedicated schema dt-bindings: PCI: qcom,pcie-ipq5018: Move IPQ5018 to dedicated schema dt-bindings: PCI: qcom,pcie-qcs404: Move QCS404 to dedicated schema dt-bindings: PCI: qcom,pcie-sdm845: Move SDM845 to dedicated schema dt-bindings: PCI: qcom,pcie-sdx55: Move SDX55 to dedicated schema dt-bindings: PCI: qcom,pcie-sm8150: Merge SC8180x into SM8150 dt-bindings: PCI: socionext,uniphier-pcie: Fix interrupt controller node name
This commit is contained in:
Bjorn Helgaas
commit
10973851fc
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|
@ -32,6 +32,8 @@ properties:
|
|||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
msi-parent: true
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||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
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||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@ properties:
|
|||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7981-pcie
|
||||
- mediatek,mt7986-pcie
|
||||
- mediatek,mt8188-pcie
|
||||
- mediatek,mt8195-pcie
|
||||
|
|
|
|||
170
Documentation/devicetree/bindings/pci/qcom,pcie-apq8064.yaml
Normal file
170
Documentation/devicetree/bindings/pci/qcom,pcie-apq8064.yaml
Normal file
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@ -0,0 +1,170 @@
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|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8064.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
|
||||
title: Qualcomm APQ8064/IPQ8064 PCI Express Root Complex
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||||
|
||||
maintainers:
|
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- Bjorn Andersson <andersson@kernel.org>
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||||
- Manivannan Sadhasivam <mani@kernel.org>
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||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
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||||
- qcom,pcie-ipq8064
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||||
- qcom,pcie-ipq8064-v2
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||||
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: parf
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||||
- const: config
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||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
items:
|
||||
- const: core # Clocks the pcie hw block
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||||
- const: iface # Configuration AHB clock
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||||
- const: phy
|
||||
- const: aux
|
||||
- const: ref
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
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||||
|
||||
resets:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reset-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: axi
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||||
- const: ahb
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||||
- const: por
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||||
- const: pci
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||||
- const: phy
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||||
- const: ext
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||||
|
||||
vdda-supply:
|
||||
description: A phandle to the core analog power supply
|
||||
|
||||
vdda_phy-supply:
|
||||
description: A phandle to the core analog power supply for PHY
|
||||
|
||||
vdda_refclk-supply:
|
||||
description: A phandle to the core analog power supply for IC which generates reference clock
|
||||
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
- vdda-supply
|
||||
- vdda_phy-supply
|
||||
- vdda_refclk-supply
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
maxItems: 3
|
||||
resets:
|
||||
maxItems: 5
|
||||
reset-names:
|
||||
maxItems: 5
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
clock-names:
|
||||
minItems: 5
|
||||
resets:
|
||||
minItems: 6
|
||||
reset-names:
|
||||
minItems: 6
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
|
||||
|
||||
pcie@1b500000 {
|
||||
compatible = "qcom,pcie-apq8064";
|
||||
reg = <0x1b500000 0x1000>,
|
||||
<0x1b502000 0x80>,
|
||||
<0x1b600000 0x100>,
|
||||
<0x0ff00000 0x100000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
|
||||
<0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
|
||||
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc PCIE_A_CLK>,
|
||||
<&gcc PCIE_H_CLK>,
|
||||
<&gcc PCIE_PHY_REF_CLK>;
|
||||
clock-names = "core", "iface", "phy";
|
||||
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
resets = <&gcc PCIE_ACLK_RESET>,
|
||||
<&gcc PCIE_HCLK_RESET>,
|
||||
<&gcc PCIE_POR_RESET>,
|
||||
<&gcc PCIE_PCI_RESET>,
|
||||
<&gcc PCIE_PHY_RESET>;
|
||||
reset-names = "axi", "ahb", "por", "pci", "phy";
|
||||
|
||||
perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
|
||||
vdda-supply = <&pm8921_s3>;
|
||||
vdda_phy-supply = <&pm8921_lvs6>;
|
||||
vdda_refclk-supply = <&v3p3_fixed>;
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
109
Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml
Normal file
109
Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8084.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm APQ8084 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-apq8084
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
items:
|
||||
- const: parf
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: config
|
||||
- const: mhi
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # Configuration AHB clock
|
||||
- const: master_bus # Master AXI clock
|
||||
- const: slave_bus # Slave AXI clock
|
||||
- const: aux
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
vdda-supply:
|
||||
description: A phandle to the core analog power supply
|
||||
|
||||
required:
|
||||
- power-domains
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
pcie@fc520000 {
|
||||
compatible = "qcom,pcie-apq8084";
|
||||
reg = <0xfc520000 0x2000>,
|
||||
<0xff000000 0x1000>,
|
||||
<0xff001000 0x1000>,
|
||||
<0xff002000 0x2000>;
|
||||
reg-names = "parf", "dbi", "elbi", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
|
||||
<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc 324>,
|
||||
<&gcc 325>,
|
||||
<&gcc 327>,
|
||||
<&gcc 323>;
|
||||
clock-names = "iface", "master_bus", "slave_bus", "aux";
|
||||
resets = <&gcc 81>;
|
||||
reset-names = "core";
|
||||
power-domains = <&gcc 1>;
|
||||
vdda-supply = <&pma8084_l3>;
|
||||
phys = <&pciephy0>;
|
||||
phy-names = "pciephy";
|
||||
perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
146
Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml
Normal file
146
Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq4019.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm IPQ4019 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-ipq4019
|
||||
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: parf
|
||||
- const: config
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux
|
||||
- const: master_bus # Master AXI clock
|
||||
- const: slave_bus # Slave AXI clock
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
resets:
|
||||
maxItems: 12
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: axi_m # AXI master reset
|
||||
- const: axi_s # AXI slave reset
|
||||
- const: pipe
|
||||
- const: axi_m_vmid
|
||||
- const: axi_s_xpu
|
||||
- const: parf
|
||||
- const: phy
|
||||
- const: axi_m_sticky # AXI master sticky reset
|
||||
- const: pipe_sticky
|
||||
- const: pwr
|
||||
- const: ahb
|
||||
- const: phy_ahb
|
||||
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pcie@40000000 {
|
||||
compatible = "qcom,pcie-ipq4019";
|
||||
reg = <0x40000000 0xf1d>,
|
||||
<0x40000f20 0xa8>,
|
||||
<0x80000 0x2000>,
|
||||
<0x40100000 0x1000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
|
||||
<0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
|
||||
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE_AXI_S_CLK>;
|
||||
clock-names = "aux",
|
||||
"master_bus",
|
||||
"slave_bus";
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
resets = <&gcc PCIE_AXI_M_ARES>,
|
||||
<&gcc PCIE_AXI_S_ARES>,
|
||||
<&gcc PCIE_PIPE_ARES>,
|
||||
<&gcc PCIE_AXI_M_VMIDMT_ARES>,
|
||||
<&gcc PCIE_AXI_S_XPU_ARES>,
|
||||
<&gcc PCIE_PARF_XPU_ARES>,
|
||||
<&gcc PCIE_PHY_ARES>,
|
||||
<&gcc PCIE_AXI_M_STICKY_ARES>,
|
||||
<&gcc PCIE_PIPE_STICKY_ARES>,
|
||||
<&gcc PCIE_PWR_ARES>,
|
||||
<&gcc PCIE_AHB_ARES>,
|
||||
<&gcc PCIE_PHY_AHB_ARES>;
|
||||
reset-names = "axi_m",
|
||||
"axi_s",
|
||||
"pipe",
|
||||
"axi_m_vmid",
|
||||
"axi_s_xpu",
|
||||
"parf",
|
||||
"phy",
|
||||
"axi_m_sticky",
|
||||
"pipe_sticky",
|
||||
"pwr",
|
||||
"ahb",
|
||||
"phy_ahb";
|
||||
|
||||
perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
189
Documentation/devicetree/bindings/pci/qcom,pcie-ipq5018.yaml
Normal file
189
Documentation/devicetree/bindings/pci/qcom,pcie-ipq5018.yaml
Normal file
|
|
@ -0,0 +1,189 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq5018.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm IPQ5018 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-ipq5018
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: atu
|
||||
- const: parf
|
||||
- const: config
|
||||
- const: mhi
|
||||
|
||||
clocks:
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: ahb
|
||||
- const: aux
|
||||
- const: axi_bridge
|
||||
|
||||
interrupts:
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 8
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe
|
||||
- const: sleep
|
||||
- const: sticky # Core sticky reset
|
||||
- const: axi_m # AXI master reset
|
||||
- const: axi_s # AXI slave reset
|
||||
- const: ahb
|
||||
- const: axi_m_sticky # AXI master sticky reset
|
||||
- const: axi_s_sticky # AXI slave sticky reset
|
||||
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
|
||||
|
||||
pcie@a0000000 {
|
||||
compatible = "qcom,pcie-ipq5018";
|
||||
reg = <0xa0000000 0xf1d>,
|
||||
<0xa0000f20 0xa8>,
|
||||
<0xa0001000 0x1000>,
|
||||
<0x00080000 0x3000>,
|
||||
<0xa0100000 0x1000>,
|
||||
<0x00083000 0x1000>;
|
||||
reg-names = "dbi",
|
||||
"elbi",
|
||||
"atu",
|
||||
"parf",
|
||||
"config",
|
||||
"mhi";
|
||||
ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
|
||||
<0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
|
||||
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
/* The controller supports Gen3, but the connected PHY is Gen2-capable */
|
||||
max-link-speed = <2>;
|
||||
|
||||
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
|
||||
<&gcc GCC_PCIE0_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE0_AXI_S_CLK>,
|
||||
<&gcc GCC_PCIE0_AHB_CLK>,
|
||||
<&gcc GCC_PCIE0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
|
||||
clock-names = "iface",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"aux",
|
||||
"axi_bridge";
|
||||
|
||||
msi-map = <0x0 &v2m0 0x0 0xff8>;
|
||||
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7",
|
||||
"global";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
|
||||
<&gcc GCC_PCIE0_SLEEP_ARES>,
|
||||
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
|
||||
<&gcc GCC_PCIE0_AHB_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
|
||||
reset-names = "pipe",
|
||||
"sleep",
|
||||
"sticky",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"axi_m_sticky",
|
||||
"axi_s_sticky";
|
||||
|
||||
perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
179
Documentation/devicetree/bindings/pci/qcom,pcie-ipq6018.yaml
Normal file
179
Documentation/devicetree/bindings/pci/qcom,pcie-ipq6018.yaml
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq6018.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm IPQ6018 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-ipq6018
|
||||
- qcom,pcie-ipq8074-gen3
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: atu
|
||||
- const: parf
|
||||
- const: config
|
||||
- const: mhi
|
||||
|
||||
clocks:
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: axi_bridge
|
||||
- const: rchng
|
||||
|
||||
interrupts:
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 8
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe
|
||||
- const: sleep
|
||||
- const: sticky # Core sticky reset
|
||||
- const: axi_m # AXI master reset
|
||||
- const: axi_s # AXI slave reset
|
||||
- const: ahb
|
||||
- const: axi_m_sticky # AXI master sticky reset
|
||||
- const: axi_s_sticky # AXI slave sticky reset
|
||||
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@20000000 {
|
||||
compatible = "qcom,pcie-ipq6018";
|
||||
reg = <0x0 0x20000000 0x0 0xf1d>,
|
||||
<0x0 0x20000f20 0x0 0xa8>,
|
||||
<0x0 0x20001000 0x0 0x1000>,
|
||||
<0x0 0x80000 0x0 0x4000>,
|
||||
<0x0 0x20100000 0x0 0x1000>;
|
||||
reg-names = "dbi", "elbi", "atu", "parf", "config";
|
||||
ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
|
||||
<0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
|
||||
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
max-link-speed = <3>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
|
||||
<&gcc GCC_PCIE0_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE0_AXI_S_CLK>,
|
||||
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
|
||||
<&gcc PCIE0_RCHNG_CLK>;
|
||||
clock-names = "iface",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"axi_bridge",
|
||||
"rchng";
|
||||
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7",
|
||||
"global";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
phys = <&pcie_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
|
||||
<&gcc GCC_PCIE0_SLEEP_ARES>,
|
||||
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
|
||||
<&gcc GCC_PCIE0_AHB_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
|
||||
reset-names = "pipe",
|
||||
"sleep",
|
||||
"sticky",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"axi_m_sticky",
|
||||
"axi_s_sticky";
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
};
|
||||
165
Documentation/devicetree/bindings/pci/qcom,pcie-ipq8074.yaml
Normal file
165
Documentation/devicetree/bindings/pci/qcom,pcie-ipq8074.yaml
Normal file
|
|
@ -0,0 +1,165 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq8074.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm IPQ8074 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-ipq8074
|
||||
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: parf
|
||||
- const: config
|
||||
|
||||
clocks:
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: ahb
|
||||
- const: aux
|
||||
|
||||
interrupts:
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 7
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe
|
||||
- const: sleep
|
||||
- const: sticky # Core sticky reset
|
||||
- const: axi_m # AXI master reset
|
||||
- const: axi_s # AXI slave reset
|
||||
- const: ahb
|
||||
- const: axi_m_sticky # AXI master sticky reset
|
||||
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pcie@10000000 {
|
||||
compatible = "qcom,pcie-ipq8074";
|
||||
reg = <0x10000000 0xf1d>,
|
||||
<0x10000f20 0xa8>,
|
||||
<0x00088000 0x2000>,
|
||||
<0x10100000 0x1000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
|
||||
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
|
||||
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <1>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
max-link-speed = <2>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
|
||||
<&gcc GCC_PCIE1_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE1_AXI_S_CLK>,
|
||||
<&gcc GCC_PCIE1_AHB_CLK>,
|
||||
<&gcc GCC_PCIE1_AUX_CLK>;
|
||||
clock-names = "iface",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"aux";
|
||||
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7",
|
||||
"global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
phys = <&pcie_qmp1>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
|
||||
<&gcc GCC_PCIE1_SLEEP_ARES>,
|
||||
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
|
||||
<&gcc GCC_PCIE1_AHB_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
|
||||
reset-names = "pipe",
|
||||
"sleep",
|
||||
"sticky",
|
||||
"axi_m",
|
||||
"axi_s",
|
||||
"ahb",
|
||||
"axi_m_sticky";
|
||||
|
||||
perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
183
Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml
Normal file
183
Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml
Normal file
|
|
@ -0,0 +1,183 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq9574.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm IPQ9574 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,pcie-ipq9574
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,pcie-ipq5332
|
||||
- qcom,pcie-ipq5424
|
||||
- const: qcom,pcie-ipq9574
|
||||
|
||||
reg:
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: atu
|
||||
- const: parf
|
||||
- const: config
|
||||
- const: mhi
|
||||
|
||||
clocks:
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: axi_bridge
|
||||
- const: rchng
|
||||
- const: ahb
|
||||
- const: aux
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 8
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe
|
||||
- const: sticky # Core sticky reset
|
||||
- const: axi_s_sticky # AXI Slave Sticky reset
|
||||
- const: axi_s # AXI slave reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
- const: axi_m # AXI master reset
|
||||
- const: aux
|
||||
- const: ahb
|
||||
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interconnect/qcom,ipq9574.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
|
||||
|
||||
pcie@10000000 {
|
||||
compatible = "qcom,pcie-ipq9574";
|
||||
reg = <0x10000000 0xf1d>,
|
||||
<0x10000f20 0xa8>,
|
||||
<0x10001000 0x1000>,
|
||||
<0x000f8000 0x4000>,
|
||||
<0x10100000 0x1000>,
|
||||
<0x000fe000 0x1000>;
|
||||
reg-names = "dbi",
|
||||
"elbi",
|
||||
"atu",
|
||||
"parf",
|
||||
"config",
|
||||
"mhi";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
|
||||
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <1>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
|
||||
<&gcc GCC_PCIE1_AXI_S_CLK>,
|
||||
<&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
|
||||
<&gcc GCC_PCIE1_RCHNG_CLK>,
|
||||
<&gcc GCC_PCIE1_AHB_CLK>,
|
||||
<&gcc GCC_PCIE1_AUX_CLK>;
|
||||
clock-names = "axi_m",
|
||||
"axi_s",
|
||||
"axi_bridge",
|
||||
"rchng",
|
||||
"ahb",
|
||||
"aux";
|
||||
|
||||
interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
|
||||
<&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
|
||||
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_S_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE1_AXI_M_ARES>,
|
||||
<&gcc GCC_PCIE1_AUX_ARES>,
|
||||
<&gcc GCC_PCIE1_AHB_ARES>;
|
||||
reset-names = "pipe",
|
||||
"sticky",
|
||||
"axi_s_sticky",
|
||||
"axi_s",
|
||||
"axi_m_sticky",
|
||||
"axi_m",
|
||||
"aux",
|
||||
"ahb";
|
||||
|
||||
phys = <&pcie1_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
156
Documentation/devicetree/bindings/pci/qcom,pcie-msm8996.yaml
Normal file
156
Documentation/devicetree/bindings/pci/qcom,pcie-msm8996.yaml
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-msm8996.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm MSM8996 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,pcie-msm8996
|
||||
- items:
|
||||
- const: qcom,pcie-msm8998
|
||||
- const: qcom,pcie-msm8996
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
items:
|
||||
- const: parf
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: config
|
||||
- const: mhi
|
||||
|
||||
clocks:
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # Pipe Clock driving internal logic
|
||||
- const: aux
|
||||
- const: cfg
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
vdda-supply:
|
||||
description: A phandle to the core analog power supply
|
||||
|
||||
vddpe-3v3-supply:
|
||||
description: A phandle to the PCIe endpoint power supply
|
||||
|
||||
required:
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pcie@600000 {
|
||||
compatible = "qcom,pcie-msm8996";
|
||||
reg = <0x00600000 0x2000>,
|
||||
<0x0c000000 0xf1d>,
|
||||
<0x0c000f20 0xa8>,
|
||||
<0x0c100000 0x100000>;
|
||||
reg-names = "parf", "dbi", "elbi", "config";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
|
||||
|
||||
device_type = "pci";
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave";
|
||||
|
||||
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pcie0_state_on>;
|
||||
pinctrl-1 = <&pcie0_state_off>;
|
||||
|
||||
phys = <&pciephy_0>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
power-domains = <&gcc PCIE0_GDSC>;
|
||||
|
||||
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
|
||||
vddpe-3v3-supply = <&wlan_en>;
|
||||
vdda-supply = <&vreg_l28a_0p925>;
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
131
Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml
Normal file
131
Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-qcs404.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm QCS404 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-qcs404
|
||||
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: parf
|
||||
- const: config
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # AHB clock
|
||||
- const: aux
|
||||
- const: master_bus # AXI Master clock
|
||||
- const: slave_bus # AXI Slave clock
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
resets:
|
||||
maxItems: 6
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
- const: pipe_sticky
|
||||
- const: pwr
|
||||
- const: ahb
|
||||
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pcie@10000000 {
|
||||
compatible = "qcom,pcie-qcs404";
|
||||
reg = <0x10000000 0xf1d>,
|
||||
<0x10000f20 0xa8>,
|
||||
<0x07780000 0x2000>,
|
||||
<0x10001000 0x2000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
|
||||
<0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
|
||||
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
|
||||
clock-names = "iface", "aux", "master_bus", "slave_bus";
|
||||
|
||||
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
phys = <&pcie_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
|
||||
<&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
|
||||
<&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
|
||||
<&gcc GCC_PCIE_0_BCR>,
|
||||
<&gcc GCC_PCIE_0_AHB_ARES>;
|
||||
reset-names = "axi_m",
|
||||
"axi_s",
|
||||
"axi_m_sticky",
|
||||
"pipe_sticky",
|
||||
"pwr",
|
||||
"ahb";
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,168 +0,0 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SC8180x PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
description:
|
||||
Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
|
||||
DesignWare PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-sc8180x
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
|
||||
#include <dt-bindings/interconnect/qcom,sc8180x.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c00000 {
|
||||
compatible = "qcom,pcie-sc8180x";
|
||||
reg = <0 0x01c00000 0 0x3000>,
|
||||
<0 0x60000000 0 0xf1d>,
|
||||
<0 0x60000f20 0 0xa8>,
|
||||
<0 0x60001000 0 0x1000>,
|
||||
<0 0x60100000 0 0x100000>;
|
||||
reg-names = "parf",
|
||||
"dbi",
|
||||
"elbi",
|
||||
"atu",
|
||||
"config";
|
||||
ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
num-lanes = <2>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7",
|
||||
"global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
|
||||
<0x100 &apps_smmu 0x1d81 0x1>;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "pci";
|
||||
};
|
||||
};
|
||||
190
Documentation/devicetree/bindings/pci/qcom,pcie-sdm845.yaml
Normal file
190
Documentation/devicetree/bindings/pci/qcom,pcie-sdm845.yaml
Normal file
|
|
@ -0,0 +1,190 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sdm845.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SDM845 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-sdm845
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
items:
|
||||
- const: parf
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: config
|
||||
- const: mhi
|
||||
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 8
|
||||
|
||||
clock-names:
|
||||
minItems: 7
|
||||
items:
|
||||
- const: pipe
|
||||
- const: aux
|
||||
- const: cfg
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a
|
||||
- enum: [ ref, tbu ]
|
||||
- const: tbu
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
|
||||
required:
|
||||
- power-domains
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1c00000 {
|
||||
compatible = "qcom,pcie-sdm845";
|
||||
reg = <0x0 0x01c00000 0x0 0x2000>,
|
||||
<0x0 0x60000000 0x0 0xf1d>,
|
||||
<0x0 0x60000f20 0x0 0xa8>,
|
||||
<0x0 0x60100000 0x0 0x100000>,
|
||||
<0x0 0x01c07000 0x0 0x1000>;
|
||||
reg-names = "parf", "dbi", "elbi", "config", "mhi";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
|
||||
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"tbu";
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7",
|
||||
"global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
|
||||
<0x100 &apps_smmu 0x1c11 0x1>,
|
||||
<0x200 &apps_smmu 0x1c12 0x1>,
|
||||
<0x300 &apps_smmu 0x1c13 0x1>,
|
||||
<0x400 &apps_smmu 0x1c14 0x1>,
|
||||
<0x500 &apps_smmu 0x1c15 0x1>,
|
||||
<0x600 &apps_smmu 0x1c16 0x1>,
|
||||
<0x700 &apps_smmu 0x1c17 0x1>,
|
||||
<0x800 &apps_smmu 0x1c18 0x1>,
|
||||
<0x900 &apps_smmu 0x1c19 0x1>,
|
||||
<0xa00 &apps_smmu 0x1c1a 0x1>,
|
||||
<0xb00 &apps_smmu 0x1c1b 0x1>,
|
||||
<0xc00 &apps_smmu 0x1c1c 0x1>,
|
||||
<0xd00 &apps_smmu 0x1c1d 0x1>,
|
||||
<0xe00 &apps_smmu 0x1c1e 0x1>,
|
||||
<0xf00 &apps_smmu 0x1c1f 0x1>;
|
||||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
phys = <&pcie0_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
vddpe-3v3-supply = <&pcie0_3p3v_dual>;
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
};
|
||||
172
Documentation/devicetree/bindings/pci/qcom,pcie-sdx55.yaml
Normal file
172
Documentation/devicetree/bindings/pci/qcom,pcie-sdx55.yaml
Normal file
|
|
@ -0,0 +1,172 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sdx55.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SDX55 PCI Express Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pcie-sdx55
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf
|
||||
- const: dbi
|
||||
- const: elbi
|
||||
- const: atu
|
||||
- const: config
|
||||
- const: mhi
|
||||
|
||||
clocks:
|
||||
maxItems: 7
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe
|
||||
- const: aux
|
||||
- const: cfg
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a
|
||||
- const: sleep
|
||||
|
||||
interrupts:
|
||||
maxItems: 8
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: msi8
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
|
||||
required:
|
||||
- power-domains
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,pcie-common.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdx55.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pcie@1c00000 {
|
||||
compatible = "qcom,pcie-sdx55";
|
||||
reg = <0x01c00000 0x3000>,
|
||||
<0x40000000 0xf1d>,
|
||||
<0x40000f20 0xc8>,
|
||||
<0x40001000 0x1000>,
|
||||
<0x40100000 0x100000>;
|
||||
reg-names = "parf",
|
||||
"dbi",
|
||||
"elbi",
|
||||
"atu",
|
||||
"config";
|
||||
ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
|
||||
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi",
|
||||
"msi2",
|
||||
"msi3",
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7",
|
||||
"msi8";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
<0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
||||
<0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
||||
<0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
||||
|
||||
clocks = <&gcc GCC_PCIE_PIPE_CLK>,
|
||||
<&gcc GCC_PCIE_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_SLEEP_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"sleep";
|
||||
|
||||
assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
|
||||
<0x100 &apps_smmu 0x0201 0x1>,
|
||||
<0x200 &apps_smmu 0x0202 0x1>,
|
||||
<0x300 &apps_smmu 0x0203 0x1>,
|
||||
<0x400 &apps_smmu 0x0204 0x1>;
|
||||
|
||||
power-domains = <&gcc PCIE_GDSC>;
|
||||
|
||||
phys = <&pcie_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
resets = <&gcc GCC_PCIE_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
|
@ -17,6 +17,7 @@ description:
|
|||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,pcie-sc8180x
|
||||
- const: qcom,pcie-sm8150
|
||||
- items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -16,7 +16,12 @@ description:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-x1e80100
|
||||
oneOf:
|
||||
- const: qcom,pcie-x1e80100
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,glymur-pcie
|
||||
- const: qcom,pcie-x1e80100
|
||||
|
||||
reg:
|
||||
minItems: 6
|
||||
|
|
|
|||
|
|
@ -1,782 +0,0 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm PCI express root complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
- Manivannan Sadhasivam <mani@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
|
||||
PCIe IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-apq8084
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq5018
|
||||
- qcom,pcie-ipq6018
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064-v2
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-ipq8074-gen3
|
||||
- qcom,pcie-ipq9574
|
||||
- qcom,pcie-msm8996
|
||||
- qcom,pcie-qcs404
|
||||
- qcom,pcie-sdm845
|
||||
- qcom,pcie-sdx55
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,pcie-ipq5332
|
||||
- qcom,pcie-ipq5424
|
||||
- const: qcom,pcie-ipq9574
|
||||
- items:
|
||||
- const: qcom,pcie-msm8998
|
||||
- const: qcom,pcie-msm8996
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
maxItems: 6
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
|
||||
iommu-map:
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
# Common definitions for clocks, clock-names and reset.
|
||||
# Platform constraints are described later.
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 13
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 13
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interconnects:
|
||||
maxItems: 2
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: pcie-mem
|
||||
- const: cpu-pcie
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 12
|
||||
|
||||
reset-names:
|
||||
minItems: 1
|
||||
maxItems: 12
|
||||
|
||||
vdda-supply:
|
||||
description: A phandle to the core analog power supply
|
||||
|
||||
vdda_phy-supply:
|
||||
description: A phandle to the core analog power supply for PHY
|
||||
|
||||
vdda_refclk-supply:
|
||||
description: A phandle to the core analog power supply for IC which generates reference clock
|
||||
|
||||
vddpe-3v3-supply:
|
||||
description: A phandle to the PCIe endpoint power supply
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: pciephy
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
perst-gpios:
|
||||
description: GPIO controlled connection to PERST# signal
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
maxItems: 1
|
||||
|
||||
wake-gpios:
|
||||
description: GPIO controlled connection to WAKE# signal
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- "#interrupt-cells"
|
||||
- required:
|
||||
- msi-map
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-host-bridge.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064v2
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-qcs404
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: config # PCIe configuration space
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq5018
|
||||
- qcom,pcie-ipq6018
|
||||
- qcom,pcie-ipq8074-gen3
|
||||
- qcom,pcie-ipq9574
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8084
|
||||
- qcom,pcie-msm8996
|
||||
- qcom,pcie-sdm845
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
reg-names:
|
||||
minItems: 4
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sdx55
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064v2
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
minItems: 3
|
||||
items:
|
||||
- const: core # Clocks the pcie hw block
|
||||
- const: iface # Configuration AHB clock
|
||||
- const: phy # Clocks the pcie PHY block
|
||||
- const: aux # Clocks the pcie AUX block, not on apq8064
|
||||
- const: ref # Clocks the pcie ref block, not on apq8064
|
||||
resets:
|
||||
minItems: 5
|
||||
maxItems: 6
|
||||
reset-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: axi # AXI reset
|
||||
- const: ahb # AHB reset
|
||||
- const: por # POR reset
|
||||
- const: pci # PCI reset
|
||||
- const: phy # PHY reset
|
||||
- const: ext # EXT reset, not on apq8064
|
||||
required:
|
||||
- vdda-supply
|
||||
- vdda_phy-supply
|
||||
- vdda_refclk-supply
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8084
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # Configuration AHB clock
|
||||
- const: master_bus # Master AXI clock
|
||||
- const: slave_bus # Slave AXI clock
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: core # Core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq4019
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
- const: master_bus # Master AXI clock
|
||||
- const: slave_bus # Slave AXI clock
|
||||
resets:
|
||||
minItems: 12
|
||||
maxItems: 12
|
||||
reset-names:
|
||||
items:
|
||||
- const: axi_m # AXI master reset
|
||||
- const: axi_s # AXI slave reset
|
||||
- const: pipe # PIPE reset
|
||||
- const: axi_m_vmid # VMID reset
|
||||
- const: axi_s_xpu # XPU reset
|
||||
- const: parf # PARF reset
|
||||
- const: phy # PHY reset
|
||||
- const: axi_m_sticky # AXI sticky reset
|
||||
- const: pipe_sticky # PIPE sticky reset
|
||||
- const: pwr # PWR reset
|
||||
- const: ahb # AHB reset
|
||||
- const: phy_ahb # PHY AHB reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq5018
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: ahb # AHB clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: axi_bridge # AXI bridge clock
|
||||
resets:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe # PIPE reset
|
||||
- const: sleep # Sleep reset
|
||||
- const: sticky # Core sticky reset
|
||||
- const: axi_m # AXI master reset
|
||||
- const: axi_s # AXI slave reset
|
||||
- const: ahb # AHB reset
|
||||
- const: axi_m_sticky # AXI master sticky reset
|
||||
- const: axi_s_sticky # AXI slave sticky reset
|
||||
interrupts:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-msm8996
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # Pipe Clock driving internal logic
|
||||
- const: aux # Auxiliary (AUX) clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
resets: false
|
||||
reset-names: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq8074
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: ahb # AHB clock
|
||||
- const: aux # Auxiliary clock
|
||||
resets:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe # PIPE reset
|
||||
- const: sleep # Sleep reset
|
||||
- const: sticky # Core Sticky reset
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: ahb # AHB Reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq6018
|
||||
- qcom,pcie-ipq8074-gen3
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: axi_bridge # AXI bridge clock
|
||||
- const: rchng
|
||||
resets:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe # PIPE reset
|
||||
- const: sleep # Sleep reset
|
||||
- const: sticky # Core Sticky reset
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: ahb # AHB Reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
- const: axi_s_sticky # AXI Slave Sticky reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq9574
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: axi_bridge
|
||||
- const: rchng
|
||||
- const: ahb
|
||||
- const: aux
|
||||
|
||||
resets:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe # PIPE reset
|
||||
- const: sticky # Core Sticky reset
|
||||
- const: axi_s_sticky # AXI Slave Sticky reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: aux # AUX Reset
|
||||
- const: ahb # AHB Reset
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-qcs404
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # AHB clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: master_bus # AXI Master clock
|
||||
- const: slave_bus # AXI Slave clock
|
||||
resets:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
reset-names:
|
||||
items:
|
||||
- const: axi_m # AXI Master reset
|
||||
- const: axi_s # AXI Slave reset
|
||||
- const: axi_m_sticky # AXI Master Sticky reset
|
||||
- const: pipe_sticky # PIPE sticky reset
|
||||
- const: pwr # PWR reset
|
||||
- const: ahb # AHB reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sdm845
|
||||
then:
|
||||
oneOf:
|
||||
# Unfortunately the "optional" ref clock is used in the middle of the list
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- properties:
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-sdx55
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 7
|
||||
maxItems: 7
|
||||
clock-names:
|
||||
items:
|
||||
- const: pipe # PIPE clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: cfg # Configuration clock
|
||||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: sleep # PCIe Sleep clock
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci # PCIe core reset
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq5018
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064v2
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-ipq8074-gen3
|
||||
- qcom,pcie-ipq9574
|
||||
- qcom,pcie-qcs404
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-msm8996
|
||||
then:
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq6018
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-ipq8074-gen3
|
||||
- qcom,pcie-msm8996
|
||||
- qcom,pcie-msm8998
|
||||
- qcom,pcie-sdm845
|
||||
then:
|
||||
oneOf:
|
||||
- properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
- properties:
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 9
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-apq8084
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064-v2
|
||||
- qcom,pcie-qcs404
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pcie@1b500000 {
|
||||
compatible = "qcom,pcie-ipq8064";
|
||||
reg = <0x1b500000 0x1000>,
|
||||
<0x1b502000 0x80>,
|
||||
<0x1b600000 0x100>,
|
||||
<0x0ff00000 0x100000>;
|
||||
reg-names = "dbi", "elbi", "parf", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
|
||||
<0x82000000 0 0 0x08000000 0 0x07e00000>;
|
||||
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc 41>,
|
||||
<&gcc 43>,
|
||||
<&gcc 44>,
|
||||
<&gcc 42>,
|
||||
<&gcc 248>;
|
||||
clock-names = "core", "iface", "phy", "aux", "ref";
|
||||
resets = <&gcc 27>,
|
||||
<&gcc 26>,
|
||||
<&gcc 25>,
|
||||
<&gcc 24>,
|
||||
<&gcc 23>,
|
||||
<&gcc 22>;
|
||||
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
||||
pinctrl-0 = <&pcie_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
vdda-supply = <&pm8921_s3>;
|
||||
vdda_phy-supply = <&pm8921_lvs6>;
|
||||
vdda_refclk-supply = <&ext_3p3v>;
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
pcie@fc520000 {
|
||||
compatible = "qcom,pcie-apq8084";
|
||||
reg = <0xfc520000 0x2000>,
|
||||
<0xff000000 0x1000>,
|
||||
<0xff001000 0x1000>,
|
||||
<0xff002000 0x2000>;
|
||||
reg-names = "parf", "dbi", "elbi", "config";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
num-lanes = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
|
||||
<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc 324>,
|
||||
<&gcc 325>,
|
||||
<&gcc 327>,
|
||||
<&gcc 323>;
|
||||
clock-names = "iface", "master_bus", "slave_bus", "aux";
|
||||
resets = <&gcc 81>;
|
||||
reset-names = "core";
|
||||
power-domains = <&gcc 1>;
|
||||
vdda-supply = <&pma8084_l3>;
|
||||
phys = <&pciephy0>;
|
||||
phy-names = "pciephy";
|
||||
perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-0 = <&pcie0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
...
|
||||
|
|
@ -51,7 +51,7 @@ properties:
|
|||
phy-names:
|
||||
const: pcie-phy
|
||||
|
||||
interrupt-controller:
|
||||
legacy-interrupt-controller:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
|
|
@ -111,7 +111,7 @@ examples:
|
|||
<0 0 0 3 &pcie_intc 2>,
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
|
||||
pcie_intc: interrupt-controller {
|
||||
pcie_intc: legacy-interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user