From 35ac96f796649346c9b0440413dc6c5138249b3e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 7 Mar 2025 00:57:05 +0000 Subject: [PATCH 01/27] arm64: dts: allwinner: Add Allwinner A523 .dtsi file The Allwinner A523, and its siblings A527 and T527, which share the same die, are a new family of SoCs introduced in 2023. They features eight Arm Cortex-A55 cores, and, among the other usual peripherals, a PCIe and USB 3.0 controller. Add the basic SoC devicetree .dtsi for the chip, describing the fundamental peripherals: the cores, GIC, timer, RTC, CCU and pinctrl. Also some other peripherals are fully compatible with previous IP, so add the USB and MMC nodes as well. The other peripherals will be added in the future, once we understand their compatibility and DT requirements. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20250307005712.16828-9-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 598 ++++++++++++++++++ 1 file changed, 598 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi new file mode 100644 index 000000000000..ee485899ba0a --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -0,0 +1,598 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2023-2024 Arm Ltd. + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x000>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x100>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x200>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x300>; + enable-method = "psci"; + }; + + cpu4: cpu@400 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x400>; + enable-method = "psci"; + }; + + cpu5: cpu@500 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x500>; + enable-method = "psci"; + }; + + cpu6: cpu@600 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x600>; + enable-method = "psci"; + }; + + cpu7: cpu@700 { + compatible = "arm,cortex-a55"; + device_type = "cpu"; + reg = <0x700>; + enable-method = "psci"; + }; + }; + + osc24M: osc24M-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + arm,no-tick-in-suspend; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x40000000>; + + pio: pinctrl@2000000 { + compatible = "allwinner,sun55i-a523-pinctrl"; + reg = <0x2000000 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + mmc0_pins: mmc0-pins { + pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; + allwinner,pinmux = <2>; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins = "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5"; + allwinner,pinmux = <2>; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins = "PC0", "PC1" ,"PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", "PC13", "PC14", + "PC15", "PC16"; + allwinner,pinmux = <3>; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + uart0_pb_pins: uart0-pb-pins { + pins = "PB9", "PB10"; + allwinner,pinmux = <2>; + function = "uart0"; + }; + }; + + ccu: clock-controller@2001000 { + compatible = "allwinner,sun55i-a523-ccu"; + reg = <0x02001000 0x1000>; + clocks = <&osc24M>, <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>; + clock-names = "hosc", "losc", + "iosc", "losc-fanout"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mmc0: mmc@4020000 { + compatible = "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg = <0x04020000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + status = "disabled"; + + max-frequency = <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg = <0x04021000 0x1000>; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "disabled"; + + max-frequency = <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@4022000 { + compatible = "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg = <0x04022000 0x1000>; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + status = "disabled"; + + max-frequency = <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells = <1>; + #size-cells = <0>; + }; + + wdt: watchdog@2050000 { + compatible = "allwinner,sun55i-a523-wdt"; + reg = <0x2050000 0x20>; + interrupts = ; + clocks = <&osc24M>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + status = "okay"; + }; + + uart0: serial@2500000 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + status = "disabled"; + }; + + uart1: serial@2500400 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + status = "disabled"; + }; + + uart2: serial@2500800 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + status = "disabled"; + }; + + uart3: serial@2500c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x02500c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + status = "disabled"; + }; + + uart4: serial@2501000 { + compatible = "snps,dw-apb-uart"; + reg = <0x02501000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + status = "disabled"; + }; + + uart5: serial@2501400 { + compatible = "snps,dw-apb-uart"; + reg = <0x02501400 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + status = "disabled"; + }; + + uart6: serial@2501800 { + compatible = "snps,dw-apb-uart"; + reg = <0x02501800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART6>; + resets = <&ccu RST_BUS_UART6>; + status = "disabled"; + }; + + uart7: serial@2501c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x02501c00 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART7>; + resets = <&ccu RST_BUS_UART7>; + status = "disabled"; + }; + + i2c0: i2c@2502000 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@2502400 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@2502800 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@2502c00 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@2503000 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2503000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C4>; + resets = <&ccu RST_BUS_I2C4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c5: i2c@2503400 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2503400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C5>; + resets = <&ccu RST_BUS_I2C5>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@3400000 { + compatible = "arm,gic-v3"; + #address-cells = <1>; + #interrupt-cells = <3>; + #size-cells = <1>; + ranges; + interrupt-controller; + reg = <0x3400000 0x10000>, + <0x3460000 0x100000>; + interrupts = ; + dma-noncoherent; + + its: msi-controller@3440000 { + compatible = "arm,gic-v3-its"; + reg = <0x3440000 0x20000>; + msi-controller; + #msi-cells = <1>; + dma-noncoherent; + }; + }; + + usb_otg: usb@4100000 { + compatible = "allwinner,sun55i-a523-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x4100000 0x400>; + interrupts = ; + interrupt-names = "mc"; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + extcon = <&usbphy 0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: phy@4100400 { + compatible = "allwinner,sun55i-a523-usb-phy", + "allwinner,sun20i-d1-usb-phy"; + reg = <0x4100400 0x100>, + <0x4101800 0x100>, + <0x4200800 0x100>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1"; + clocks = <&osc24M>, + <&osc24M>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@4101000 { + compatible = "allwinner,sun55i-a523-ehci", + "generic-ehci"; + reg = <0x4101000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@4101400 { + compatible = "allwinner,sun55i-a523-ohci", + "generic-ohci"; + reg = <0x4101400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@4200000 { + compatible = "allwinner,sun55i-a523-ehci", + "generic-ehci"; + reg = <0x4200000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@4200400 { + compatible = "allwinner,sun55i-a523-ohci", + "generic-ohci"; + reg = <0x4200400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + r_ccu: clock-controller@7010000 { + compatible = "allwinner,sun55i-a523-r-ccu"; + reg = <0x7010000 0x250>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0_200M>, + <&ccu CLK_PLL_AUDIO0_4X>; + clock-names = "hosc", + "losc", + "iosc", + "pll-periph", + "pll-audio"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + nmi_intc: interrupt-controller@7010320 { + compatible = "allwinner,sun55i-a523-nmi"; + reg = <0x07010320 0xc>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun55i-a523-r-pinctrl"; + reg = <0x7022000 0x800>; + interrupts = , + ; + clocks = <&r_ccu CLK_R_APB0>, + <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_i2c_pins: r-i2c-pins { + pins = "PL0" ,"PL1"; + allwinner,pinmux = <2>; + function = "r_i2c0"; + }; + }; + + r_i2c0: i2c@7081400 { + compatible = "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x07081400 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_BUS_R_I2C0>; + resets = <&r_ccu RST_BUS_R_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&r_i2c_pins>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + rtc: rtc@7090000 { + compatible = "allwinner,sun55i-a523-rtc", + "allwinner,sun50i-r329-rtc"; + reg = <0x7090000 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_BUS_R_RTC>, + <&osc24M>, + <&r_ccu CLK_R_AHB>; + clock-names = "bus", "hosc", "ahb"; + #clock-cells = <1>; + }; + }; +}; From acf5b947cff1b991ceb7fa53c66555242ff4c87b Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 7 Mar 2025 00:57:06 +0000 Subject: [PATCH 02/27] dt-bindings: vendor-prefixes: Add YuzukiHD name YuzukiHD provides Open Source Hardware designs, and also offers ready-made builds of them: https://github.com/YuzukiHD Signed-off-by: Andre Przywara Acked-by: Conor Dooley Link: https://patch.msgid.link/20250307005712.16828-10-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 86f6a19b28ae..411fd65e0bde 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1749,6 +1749,8 @@ patternProperties: description: Y Soft Corporation a.s. "^yuridenki,.*": description: Yuridenki-Shokai Co. Ltd. + "^yuzukihd,.*": + description: YuzukiHD Open Source Hardware "^zarlink,.*": description: Zarlink Semiconductor "^zealz,.*": From f9d55227839199e928a41574e41089288a43a2d6 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 7 Mar 2025 00:57:07 +0000 Subject: [PATCH 03/27] dt-bindings: arm: sunxi: Add new board names for A523 generation The new Allwinner A523 SoC family comes in different packages, though they all share the same die, and so the devicetree bindings. Add three board names that use a version from this SoC family: - The Avaota A1: an Open Source hardware router board. - The Radxa Cubie A5E: a typical development board - The X96QPro+: a TV box Add their compatible name to the list. Signed-off-by: Andre Przywara Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250307005712.16828-11-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index f536cdd2c1a6..61627c900b31 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -845,6 +845,11 @@ properties: - const: allwinner,r7-tv-dongle - const: allwinner,sun5i-a10s + - description: Radxa Cubie A5E + items: + - const: radxa,cubie-a5e + - const: allwinner,sun55i-a527 + - description: Remix Mini PC items: - const: jide,remix-mini-pc @@ -966,6 +971,11 @@ properties: - const: hechuang,x96-mate - const: allwinner,sun50i-h616 + - description: X96Q Pro+ + items: + - const: amediatech,x96q-pro-plus + - const: allwinner,sun55i-h728 + - description: Xunlong OrangePi items: - const: xunlong,orangepi @@ -1081,4 +1091,9 @@ properties: - const: xunlong,orangepi-zero3 - const: allwinner,sun50i-h618 + - description: YuzukiHD Avaota A1 + items: + - const: yuzukihd,avaota-a1 + - const: allwinner,sun55i-t527 + additionalProperties: true From dbe54efa32afe5b82763c015cbe9e64c4d4e117a Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 7 Mar 2025 00:57:08 +0000 Subject: [PATCH 04/27] arm64: dts: allwinner: a523: add Avaota-A1 router support The Avaota A1 router board is an Open Source hardware board, designed by YuzukiHD. Pine64 produces some boards and sells them. It uses the Allwinner A527 or T527 SoC, and comes with the following features: - Eight ARM Cortex-A55 cores, Mali-G57 MC1 GPU - 1GiB/2GiB/4GiB LPDDR4 DRAM - AXP717 + AXP323 PMIC - Raspberry-Pi-2 compatible GPIO header - 1 USB 2.0 type A host port, 1 USB 3.0 type A host post - 1 USB 2.0 type C port (OTG + serial debug) - MicroSD slot - eMMC between 16 and 128 GiB - on-board 16MiB bootable SPI NOR flash - two 1Gbps Ethernet ports (via RTL8211F PHYs) - HDMI port - DP port - camera and LCD connectors - 3.5mm headphone jack - (yet) unsupported WiFi/BT chip - 1.3" LC display, connected via SPI - 12 V barrel plug for power supply Add the devicetree file describing the currently supported features. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250307005712.16828-12-andre.przywara@arm.com [wens@csie.org: Squash in SD card detect pull resistor fix] Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun55i-t527-avaota-a1.dts | 308 ++++++++++++++++++ 2 files changed, 309 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 00bed412ee31..0d678a7499e3 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -52,3 +52,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-sp.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-avaota-a1.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts new file mode 100644 index 000000000000..dea2acc1849b --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2024 Arm Ltd. + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include + +/ { + model = "Avaota A1"; + compatible = "yuzukihd,avaota-a1", "allwinner,sun55i-t527"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext_osc32k"; + }; + + reg_vcc12v: vcc12v { + /* DC input jack */ + compatible = "regulator-fixed"; + regulator-name = "vcc-12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from the 12V->5V regulator */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc12v>; + regulator-always-on; + }; + + reg_usb_vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + gpio = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ + enable-active-high; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_cldo3>; + cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + bus-width = <8>; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <®_cldo3>; + vqmmc-supply = <®_cldo1>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply = <®_cldo1>; + vcc-pd-supply = <®_dcdc4>; + vcc-pe-supply = <®_dcdc4>; + vcc-pf-supply = <®_cldo3>; /* actually switchable */ + vcc-pg-supply = <®_bldo1>; + vcc-ph-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply = <®_dcdc4>; + vcc-pj-supply = <®_dcdc4>; + vcc-pk-supply = <®_bldo3>; +}; + +&r_i2c0 { + status = "okay"; + + axp717: pmic@35 { + compatible = "x-powers,axp717"; + reg = <0x35>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin4-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.4 GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1160000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-dram"; + }; + + reg_dcdc4: dcdc4 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vdd-io"; + }; + + reg_aldo1: aldo1 { + /* not connected */ + }; + + reg_aldo2: aldo2 { + /* not connected */ + }; + + reg_aldo3: aldo3 { + /* supplies the I2C pins for this PMIC */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl-pm"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg-wifi-lvds"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dram-1v8"; + }; + + reg_bldo3: bldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-cvp-pk-vid1v8"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io-mmc-spi-ana"; + }; + + reg_cldo4: cldo4 { + /* not connected */ + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible = "x-powers,axp323"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + aldo1 { + /* not connected */ + }; + + dldo1 { + /* not connected */ + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + /* Some RISC-V management core related voltage */ + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-dnr"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply = <®_aldo3>; + */ + vcc-pm-supply = <®_aldo3>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + /* + * The CC pins of the USB-C port have two pull-down resistors + * connected to GND, which fixes this port to a peripheral role. + * There is a regulator, controlled by a GPIO, to provide VBUS power + * to the port, and a VBUSDET GPIO, to detect externally provided + * power, but without the CC pins there is no real way to do a + * runtime role detection. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_usb_vbus>; + usb0_vbus_det-gpios = <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */ + status = "okay"; +}; From 4ee87d875071390b4e24ce46dbdd792216d61651 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 7 Mar 2025 00:57:09 +0000 Subject: [PATCH 05/27] arm64: dts: allwinner: a523: add X96Q-Pro+ support The X96QPro+ is a TV box using the Allwinner H728 SoC. That SoC seems to be a package variant of the A523 family, at least it uses the same SoC ID and is compatible as far as we can assess. It comes with the following specs: - Allwinner H728 SoC: 8 Arm Cortex-A55 cores, Mali-G57 MC1 GPU - 2 or 4GiB DDR3L DRAM - 32, 64, or 128 GiB eMMC flash - AXP717 + AXP323 PMICs - Gigabit Ethernet (using MAXIO PHY) - HDMI port - 2 * USB 2.0 ports - 1 * USB 3.0 port - microSD card slot - TOSLINK digital audio output - 3.5mm A/V port - infrared sensor - 7-segment display - 5V barrel plug power supply - power button The PCB provides holes for soldering a UART header or cable, this is connected to the debug UART0. There is another set of UART pins available. The board also features a FEL button (accessible through the 3.5mm socket) and a reset button (only accessible when case is open). This .dts just describes the basic peripherals as far as we support them at the moment. The PMIC rail assignments are reverse engineered as far as possible, by dumping them from a running Android system, and correlating them to other boards using the same SoC. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250307005712.16828-13-andre.przywara@arm.com [wens@csie.org: Squash in SD card detect pull resistor fix] Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun55i-h728-x96qpro+.dts | 287 ++++++++++++++++++ 2 files changed, 288 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 0d678a7499e3..983be49ea6ef 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -52,4 +52,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-sp.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun55i-h728-x96qpro+.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-avaota-a1.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts new file mode 100644 index 000000000000..59db103546f6 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2024 Arm Ltd. + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include + +/ { + model = "X96Q Pro+"; + compatible = "amediatech,x96q-pro-plus", "allwinner,sun55i-h728"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext_osc32k"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from the barrel plug */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_vcc3v3: vcc3v3 { + /* 3.3V dummy supply for the SD card */ + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v>; + regulator-always-on; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ + bus-width = <4>; + disable-wp; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_cldo3>; + vqmmc-supply = <®_cldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply = <®_cldo1>; + vcc-pd-supply = <®_dcdc4>; + vcc-pe-supply = <®_dcdc4>; + vcc-pf-supply = <®_cldo3>; /* actually switchable */ + vcc-pg-supply = <®_bldo1>; + vcc-ph-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply = <®_dcdc4>; + vcc-pj-supply = <®_dcdc4>; + vcc-pk-supply = <®_bldo3>; +}; + +&r_i2c0 { + status = "okay"; + + axp717: pmic@34 { + compatible = "x-powers,axp717"; + reg = <0x34>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin4-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.0(?) GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1360000>; + regulator-max-microvolt = <1360000>; + regulator-name = "vdd-dram"; + }; + + reg_dcdc4: dcdc4 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd-dcdc4"; + }; + + reg_aldo1: aldo1 { + /* not connected */ + }; + + reg_aldo2: aldo2 { + /* not connected */ + }; + + reg_aldo3: aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-aldo3"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg-wifi-lvds"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dram-1v8"; + }; + + reg_bldo3: bldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-bldo3"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-codec-sd"; + }; + + reg_cldo2: cldo2 { + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-codec-eth-sd"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-eth-phy"; + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible = "x-powers,axp323"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + aldo1 { + /* not connected */ + }; + + dldo1 { + /* not connected */ + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd-dcdc3"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply = <®_aldo3>; + */ + vcc-pm-supply = <®_aldo3>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + /* USB0 is a USB-A receptacle, always powered, so force host mode. */ + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; From c2520cd032ae8ca3fdaf77b3f3aa687c8cb7843f Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 7 Mar 2025 00:57:10 +0000 Subject: [PATCH 06/27] arm64: dts: allwinner: a523: add Radxa A5E support The Radxa A5E is a development board using the Allwinner A527 SoC, which is using the same die as the A523 SoC, just exposing the pins of more peripherals (like HDMI or the 2nd MAC). The board features: - Allwinner A527/T527 SoC: 8 ARM Cortex-A55 cores, Mali-G57 MC1 GPU - 1GiB/2GiB/4GiB LPDDR4 DRAM - AXP717 + AXP323 PMICs - Raspberry-Pi-2 compatible 40pin GPIO header - 1 USB 2.0 type C port (OTG), also power supply - 1 USB 3.0 type A host port (multiplexed with M.2 slot) - 1 M.2 M-key 2230 slot, with 1 PCIe2.1 lane connected (multiplexed with USB 3.0 port) - MicroSD slot - optional eMMC, 8, 16 or 32GB available - optional on-board 16MiB bootable SPI NOR flash - two 1Gbps Ethernet ports (via MAXIO MAE0621A PHYs) - PoE header for optional supply circuit on one Ethernet port - WiFi 802.11 a/b/g/n/ac/ax (LB-Link BL-M8800DS2 module using AIC8800) - HDMI port - camera and LCD connectors - power supply via USB-C connector (but no PD) or GPIO header pins This .dts describes the devices as far as we support them at the moment. The PMIC rails have been assigned as per the schematics. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250307005712.16828-14-andre.przywara@arm.com [wens@csie.org: Squash in SD card detect pull resistor fix] Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com [wens@csie.org: Rename dts file to sun55i-a527-cubie-a5e.dts] Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 299 ++++++++++++++++++ 2 files changed, 300 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 983be49ea6ef..9652a61cf1f2 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -52,5 +52,6 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-sp.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun55i-a527-cubie-a5e.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun55i-h728-x96qpro+.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-avaota-a1.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts new file mode 100644 index 000000000000..ad9bd6da4249 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2025 Arm Ltd. + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include + +/ { + model = "Radxa A5E"; + compatible = "radxa,cubie-a5e", "allwinner,sun55i-a527"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext_osc32k"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from the USB-C connector */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_vbus: vbus { + compatible = "regulator-fixed"; + regulator-name = "usb-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_cldo3>; + cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply = <®_cldo1>; + vcc-pd-supply = <®_cldo3>; + vcc-pe-supply = <®_aldo2>; + vcc-pf-supply = <®_cldo3>; /* actually switchable */ + vcc-pg-supply = <®_bldo1>; + vcc-ph-supply = <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply = <®_cldo3>; + vcc-pj-supply = <®_cldo4>; + vcc-pk-supply = <®_cldo1>; +}; + +&r_i2c0 { + status = "okay"; + + axp717: pmic@34 { + compatible = "x-powers,axp717"; + reg = <0x34>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin4-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.4 GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + + reg_aldo1: aldo1 { + /* not connected */ + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pe"; + }; + + reg_aldo3: aldo3 { + /* supplies the I2C pins for this PMIC */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl-usb"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg-iowifi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pm-lpddr4"; + }; + + reg_bldo3: bldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-mipi-cam"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc-and-their-dog"; + }; + + reg_cldo2: cldo2 { + /* not connected */ + }; + + reg_cldo3: cldo3 { + /* IO, USB-2, 3V3, card, NAND, sensor, PI */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io-mmc-spi-ana"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pj-phy"; + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible = "x-powers,axp323"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-mipi-dsi"; + }; + + dldo1 { + /* not connected */ + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1160000>; + regulator-name = "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + /* RISC-V management core supply */ + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-dnr"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply = <®_aldo3>; + */ + vcc-pm-supply = <®_aldo3>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + /* + * The USB-C port is the primary power supply, so in this configuration + * relies on the other end of the USB cable to supply the VBUS power. + * So use this port in peripheral mode. + * It is possible to supply the board with the 5V pins on the GPIO + * header, and since the DCIN_5V line is hardwired to the USB-C VBUS + * pins, the port turns into a host port, unconditionally supplying + * power. The dr_mode property should be changed to "host" here, if + * users choose this setup. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +/* + * The schematic describes USB0_ID (PL10), measuring VBUS_5V, which looks to + * be always on. Also there is USB-VBUSDET (PL2), which is measuring the same + * VBUS_5V. There is also DCIN_DET, which measures DCIN_5V, so the power + * input rail. + * None of them seem to make any sense in relation to detecting USB devices + * or whether there is power provided via any USB pins: they would always + * report high, otherwise the system wouldn't be running. + * The AXP717C provides proper USB-C CC pin functionality, but the PMIC is + * not connected to those pins of the USB-C connector. + */ +&usbphy { + usb0_vbus-supply = <®_vcc5v>; + usb1_vbus-supply = <®_usb_vbus>; + status = "okay"; +}; From 8b9b2f0547627476517a602ebdfee040c0b6698e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 7 Mar 2025 00:57:11 +0000 Subject: [PATCH 07/27] dt-bindings: arm: sunxi: Add YuzukiHD Chameleon board name The Chameleon is an Open Source hardware board designed by YuzkuiHD, using the Allwinner H618 SoC: https://github.com/YuzukiHD/YuzukiChameleon Add its compatible name to the list of valid board name. Signed-off-by: Andre Przywara Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250307005712.16828-15-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 61627c900b31..cb354c2c61b2 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -1096,4 +1096,9 @@ properties: - const: yuzukihd,avaota-a1 - const: allwinner,sun55i-t527 + - description: YuzukiHD Chameleon + items: + - const: yuzukihd,chameleon + - const: allwinner,sun50i-h618 + additionalProperties: true From f4a6b0f7200f8629f4138f1094ce654ab75df41e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 7 Mar 2025 00:57:12 +0000 Subject: [PATCH 08/27] arm64: dts: allwinner: h616: add YuzukiHD Chameleon support The Chameleon board is an OpenHardware devboard made by YuzukiTsuru. The form factor resembles the Raspberry Pi Model A boards, though it differs significantly in its features: - Allwinner H618 SoC (4 * Arm Cortex-A53 cores, 1MB L2 cache, 1.4 GHz) - between 512MiB and 2GiB DDR3 DRAM - up to 128 GiB eMMC flash - AXP313a PMIC - 100 Mbit/s Ethernet pins on a header - XR829 WIFI+Bluetooth chip - 4 * USB 2.0 USB-C ports - microSD card slot - 3.5mm A/V port Add the devicetree describing the board's peripherals and their connections. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250307005712.16828-16-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../sun50i-h618-yuzukihd-chameleon.dts | 222 ++++++++++++++++++ 2 files changed, 223 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 9652a61cf1f2..790aad3a91e8 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-transpeed-8k618-t.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-yuzukihd-chameleon.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts new file mode 100644 index 000000000000..eae56908b9b4 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" + +#include +#include + +/ { + model = "Yuzuki Chameleon"; + compatible = "yuzukihd,chameleon", "allwinner,sun50i-h618"; + + aliases { + ethernet1 = &sdio_wifi; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + wifi_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11 */ + }; +}; + +&codec { + allwinner,audio-routing = "Line Out", "LINEOUT"; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + disable-wp; + vmmc-supply = <®_dldo1>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_dldo1>; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 12 IRQ_TYPE_LEVEL_LOW>; /* PG12 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + bus-width = <8>; + cap-mmc-hw-reset; + mmc-ddr-3_3v; + non-removable; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_dldo1>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pf-supply = <®_dldo1>; /* via VCC_IO */ + vcc-pg-supply = <®_dldo1>; + vcc-ph-supply = <®_dldo1>; /* via VCC_IO */ + vcc-pi-supply = <®_dldo1>; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <2 2 IRQ_TYPE_LEVEL_LOW>; /* PC2 */ + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL, so needs to be always on. */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +/* Connected to the Bluetooth UART pins of the XR829 Wifi/BT chip. */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */ + usb0_vbus-supply = <®_vcc5v>; + usb1_vbus-supply = <®_vcc5v>; + usb2_vbus-supply = <®_vcc5v>; + usb3_vbus-supply = <®_vcc5v>; + status = "okay"; +}; From 71776a6eb34d96ed5996434021b9c5df7b8d27ac Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 9 Apr 2025 15:36:12 -0500 Subject: [PATCH 09/27] arm/arm64: dts: allwinner: Use preferred node names for cooling maps The preferred node name for cooling map nodes is a 'map' prefix. Use 'map0' like most other platforms. Signed-off-by: Rob Herring (Arm) Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250409203613.1506047-1-robh@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 4 ++-- arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 2 +- arch/arm/boot/dts/allwinner/sun8i-r40.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi index addf0cb0f465..6f88d8764e6a 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi @@ -1225,7 +1225,7 @@ cpu0_very_hot: cpu-very-hot { }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu0_hot>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -1255,7 +1255,7 @@ cpu1_very_hot: cpu-very-hot { }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu1_hot>; cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi index eac2349a2380..cfd039840b43 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi @@ -262,7 +262,7 @@ cpu_very_hot_trip: cpu-very-hot { }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu_hot_trip>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi index a5b1f1e3900d..fa162f7fa9f0 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi @@ -146,7 +146,7 @@ cpu_very_hot_trip: cpu-very-hot { }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu_hot_trip>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index d3caf27b6a55..51b61f0d2f44 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -207,7 +207,7 @@ cpu_very_hot_trip: cpu-very-hot { }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu_hot_trip>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, From 4e743ca6eef8611c2271c5cd3d0cb1e733e30e14 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:22 -0500 Subject: [PATCH 10/27] arm64: dts: allwinner: h5/h6: Drop spurious 'clock-latency-ns' properties 'clock-latency-ns' is not a valid property for CPU nodes. It belongs in OPP table (which has it). Drop them from the CPU nodes. Signed-off-by: Rob Herring (Arm) Reviewed-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250410-dt-cpu-schema-v2-1-63d7dc9ddd0a@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ---- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 51b61f0d2f44..01a29c1988a6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -16,7 +16,6 @@ cpu0: cpu@0 { reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -26,7 +25,6 @@ cpu1: cpu@1 { reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -36,7 +34,6 @@ cpu2: cpu@2 { reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -46,7 +43,6 @@ cpu3: cpu@3 { reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 2301c59b41b1..73e8604315c5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -27,7 +27,6 @@ cpu0: cpu@0 { reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -44,7 +43,6 @@ cpu1: cpu@1 { reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -61,7 +59,6 @@ cpu2: cpu@2 { reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -78,7 +75,6 @@ cpu3: cpu@3 { reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; i-cache-size = <0x8000>; i-cache-line-size = <64>; From b2163b513e97b44c06f8f400c394615f8879355d Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Sat, 15 Feb 2025 11:02:26 +1300 Subject: [PATCH 11/27] arm64: dts: allwinner: h700: Add hp-det-gpios for Anbernic RG35XX Add support for headphone insertion detection via GPIO for the RG35XX series, and add the corresponding routing to the codec node. Signed-off-by: Chris Morgan Signed-off-by: Ryan Walklin Tested-by: Philippe Simons -- Changelog v1..v2: - Remove vendor prefix from GPIO description. - Whitespace fix Changelog v2..v3: - Add Tested-by tag Link: https://patch.msgid.link/20250214220247.10810-5-ryan@testtoast.com Signed-off-by: Chen-Yu Tsai --- .../boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts index 7e17ca07892d..db058201a414 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -184,8 +184,11 @@ reg_vcc5v: regulator-vcc5v { /* USB-C power input */ }; &codec { - allwinner,audio-routing = "Line Out", "LINEOUT"; + /* Both speakers and headphone jack connected to 74HC4052D analog mux*/ + allwinner,audio-routing = "Speaker", "LINEOUT", + "Headphone", "LINEOUT"; allwinner,pa-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; // PI5 + hp-det-gpios = <&pio 8 3 GPIO_ACTIVE_HIGH>; // PI3 status = "okay"; }; From 87c6b4504c4083ef96f21c34ea6e21f338e7a1b7 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 16 Apr 2025 23:48:38 +0100 Subject: [PATCH 12/27] arm64: dts: allwinner: h616: Add Mali GPU node The Allwinner H616 SoC contains a Mali-G31 MP2 GPU, which is of the Mali Bifrost family. There is a power domain specifically for that GPU, which needs to be enabled to make use of the it. Add the DT nodes for those two devices, and link them together through the "power-domains" property. Any board wishing to use the GPU would need to enable the GPU node and specify the "mali-supply" regulator. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20250416224839.9840-4-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index cdce3dcb8ec0..ceedae9e399b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -150,6 +150,21 @@ soc { #size-cells = <1>; ranges = <0x0 0x0 0x0 0x40000000>; + gpu: gpu@1800000 { + compatible = "allwinner,sun50i-h616-mali", + "arm,mali-bifrost"; + reg = <0x1800000 0x40000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>; + clock-names = "core", "bus"; + power-domains = <&prcm_ppu 2>; + resets = <&ccu RST_BUS_GPU>; + status = "disabled"; + }; + crypto: crypto@1904000 { compatible = "allwinner,sun50i-h616-crypto"; reg = <0x01904000 0x800>; @@ -874,6 +889,12 @@ r_ccu: clock@7010000 { #reset-cells = <1>; }; + prcm_ppu: power-controller@7010250 { + compatible = "allwinner,sun50i-h616-prcm-ppu"; + reg = <0x07010250 0x10>; + #power-domain-cells = <1>; + }; + nmi_intc: interrupt-controller@7010320 { compatible = "allwinner,sun50i-h616-nmi", "allwinner,sun9i-a80-nmi"; From 224e986158e9cbca4a3344cc12e298bd3c9f45c8 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 16 Apr 2025 23:48:39 +0100 Subject: [PATCH 13/27] arm64: dts: allwinner: h616: enable Mali GPU for all boards All Allwinner H616/H618 SoCs contain a Mali G31 MP2 GPU. Enable the DT nodes for that GPU, and specify the regulator providing power to the VDD_GPU pins of the package. The rest of the DT node is set by the SoC, so is not board specific. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250416224839.9840-5-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts | 5 +++++ .../boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 5 +++++ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 4 ++++ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 4 ++++ arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts | 5 +++++ .../boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi | 5 +++++ .../arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts | 5 +++++ arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 4 ++++ .../boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts | 5 +++++ .../boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts | 5 +++++ 10 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts index 17e6aef67aaf..7906b79c0389 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts @@ -79,6 +79,11 @@ &ehci0 { status = "okay"; }; +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &ir { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi index d12b01c5f41b..bebfeb2a337a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi @@ -67,6 +67,11 @@ &cpu0 { cpu-supply = <®_dcdc2>; }; +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &mmc0 { vmmc-supply = <®_dldo1>; /* Card detection pin is not connected */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi index 908fa3b847a6..a8644fb52b04 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi @@ -77,6 +77,10 @@ &emac0 { status = "okay"; }; +&gpu { + status = "okay"; +}; + &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts index a360d8567f95..f2e3300e078a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -24,6 +24,10 @@ &emac0 { phy-supply = <®_dcdce>; }; +&gpu { + mali-supply = <®_dcdcc>; +}; + &mmc0 { vmmc-supply = <®_dcdce>; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts index 968960ebf1d1..085f3e4e8eaa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts @@ -50,6 +50,11 @@ &ehci2 { status = "okay"; }; +&gpu { + mali-supply = <®_dcdcc>; + status = "okay"; +}; + &ir { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi index e92d150aaf1c..3f416d129b72 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-longan-module-3h.dtsi @@ -10,6 +10,11 @@ &cpu0 { cpu-supply = <®_dcdc2>; }; +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts index a0fe7a9afb77..b340bbcb710d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts @@ -69,6 +69,11 @@ &ehci1 { /* USB 2 & 3 are on the FPC connector (or the exansion board) */ +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &mmc0 { cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ bus-width = <4>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts index e1cd7572a14c..c51d4d9120de 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts @@ -27,6 +27,10 @@ &ext_rgmii_phy { motorcomm,clk-out-frequency-hz = <125000000>; }; +&gpu { + mali-supply = <®_dcdc1>; +}; + &mmc0 { /* * The schematic shows the card detect pin wired up to PF6, via an diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts index f828ca1ce51e..efe0faa252f5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts @@ -69,6 +69,11 @@ &ehci1 { status = "okay"; }; +&gpu { + mali-supply = <®_dcdc1>; + status = "okay"; +}; + &ir { status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts index db058201a414..1a750c5f6fac 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -200,6 +200,11 @@ &ehci0 { status = "okay"; }; +&gpu { + mali-supply = <®_dcdc2>; + status = "okay"; +}; + &mmc0 { vmmc-supply = <®_cldo3>; disable-wp; From 5209e0e62e54b1f33c9e456350cbd54d4536aa5d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Apr 2025 10:47:36 +0200 Subject: [PATCH 14/27] arm64: dts: allwinner: Align wifi node name with bindings Since commit 3c3606793f7e ("dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schema"), bindings expect 'wifi' as node name: sun50i-h6-orangepi-3.dtb: sdio-wifi@1: $nodename:0: 'sdio-wifi@1' does not match '^wifi(@.*)?$' Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250424084737.105215-1-krzysztof.kozlowski@linaro.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index ab87c3447cd7..7b2de2ac8b2d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -144,7 +144,7 @@ &mmc1 { non-removable; status = "okay"; - brcm: sdio-wifi@1 { + brcm: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&r_pio>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts index a3f65a45bd26..0911c537cc6b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts @@ -28,7 +28,7 @@ &mmc1 { non-removable; status = "okay"; - brcm: sdio-wifi@1 { + brcm: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&r_pio>; From efcb1a41592ab6b1e2e957c137674bdd4ff64eb5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Apr 2025 10:47:37 +0200 Subject: [PATCH 15/27] ARM: dts: allwinner: Align wifi node name with bindings Since commit 3c3606793f7e ("dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schema"), bindings expect 'wifi' as node name: sun8i-h3-nanopi-neo-air.dtb: bcrmf@1: $nodename:0: 'bcrmf@1' does not match '^wifi(@.*)?$' Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250424084737.105215-2-krzysztof.kozlowski@linaro.org Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts index 6d85370e04f1..9a2742363cd0 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts @@ -94,7 +94,7 @@ &mmc1 { non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; From a1c3985cc7231185aa38734cc7996f94ff7febca Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 16 Apr 2025 18:00:06 +0800 Subject: [PATCH 16/27] arm64: dts: allwinner: correct the model name for Radxa Cubie A5E According to https://radxa.com/products/cubie/a5e, the name of this board should be "Radxa Cubie A5E". This is also consistent with the dt-bindings. Fixes: 80e0fb4e491b ("arm64: dts: allwinner: a523: add Radxa A5E support") Signed-off-by: Chukun Pan Reviewed-by: Andre Przywara Link: https://patch.msgid.link/20250416100006.82920-1-amadeus@jmu.edu.cn Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index ad9bd6da4249..2d2f3af91d05 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -8,7 +8,7 @@ #include / { - model = "Radxa A5E"; + model = "Radxa Cubie A5E"; compatible = "radxa,cubie-a5e", "allwinner,sun55i-a527"; aliases { From dd39864aabea2f7896a65def86057e13fcc4801f Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 20 Apr 2025 10:48:04 +0100 Subject: [PATCH 17/27] arm64: dts: allwinner: a64: Add WiFi/BT header on PINE A64 This adds all the pin mappings on the WiFi/BT header on the original Pine64. They're disabled by default as the modules don't ship by default. This includes, where they haven't been already, UART1 for BT and mmc1 for WiFi. Signed-off-by: Peter Robinson Link: https://patch.msgid.link/20250420094823.954073-2-pbrobinson@gmail.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index 09e71fd60785..3256acec1ff9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -124,6 +124,17 @@ &mmc0 { status = "okay"; }; +/* On Wifi/BT connector */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo4>; + vqmmc-supply = <®_eldo1>; + bus-width = <4>; + non-removable; + status = "disabled"; +}; + &ohci0 { status = "okay"; }; @@ -286,6 +297,7 @@ &uart0 { &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; status = "disabled"; }; From b6aa4fb7ca0a858c4427a870bcdcd9eef8278c2a Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 20 Apr 2025 10:48:05 +0100 Subject: [PATCH 18/27] arm64: dts: allwinner: a64: Add WiFi/BT header on SOPINE Baseboard This adds all the pin mappings on the WiFi/BT header on the SOPINE Baseboard/A64-LTS. They're disabled by default as the modules don't ship by default. This includes, where they haven't been already, UART1 for BT and mmc1 for WiFi. Signed-off-by: Peter Robinson Link: https://patch.msgid.link/20250420094823.954073-3-pbrobinson@gmail.com Signed-off-by: Chen-Yu Tsai --- .../allwinner/sun50i-a64-sopine-baseboard.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index be2347c8f267..231e652cab67 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -103,6 +103,17 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; +/* On Wifi/BT connector */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo4>; + vqmmc-supply = <®_eldo1>; + bus-width = <4>; + non-removable; + status = "disabled"; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; @@ -175,6 +186,14 @@ &uart0 { status = "okay"; }; +/* On Wifi/BT connector, with RTS/CTS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "disabled"; +}; + /* On Pi-2 connector */ &uart2 { pinctrl-names = "default"; From 02f27ea7fa02c015cc831fa0f14bf3d58a516a6f Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 30 Apr 2025 13:32:03 +0800 Subject: [PATCH 19/27] dt-bindings: sram: sunxi-sram: Add A523 compatible The Allwinner A523 family of SoCs have their "system control" registers compatible to the A64 SoC, so add the new SoC specific compatible string. Reviewed-by: Andre Przywara Signed-off-by: Yixun Lan Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250430-01-sun55i-emac0-v3-1-6fc000bbccbd@gentoo.org Signed-off-by: Chen-Yu Tsai --- .../bindings/sram/allwinner,sun4i-a10-system-control.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index a7236f7db4ec..e7f7cf72719e 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -50,6 +50,7 @@ properties: - enum: - allwinner,sun50i-a100-system-control - allwinner,sun50i-h6-system-control + - allwinner,sun55i-a523-system-control - const: allwinner,sun50i-a64-system-control reg: From 56766ca6c4f6099de41bb51aba653217dae5df57 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 30 Apr 2025 13:32:05 +0800 Subject: [PATCH 20/27] arm64: dts: allwinner: a523: Add EMAC0 ethernet MAC Add EMAC0 ethernet MAC support which found on A523 variant SoCs, including the A527/T527 chips. MAC0 is compatible to the A64 chip which requires an external PHY. This patch only add RGMII pins for now. Reviewed-by: Andre Przywara Tested-by: Corentin LABBE Signed-off-by: Yixun Lan Link: https://patch.msgid.link/20250430-01-sun55i-emac0-v3-3-6fc000bbccbd@gentoo.org Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index ee485899ba0a..8b7cbc2e78f5 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -126,6 +126,16 @@ pio: pinctrl@2000000 { interrupt-controller; #interrupt-cells = <3>; + rgmii0_pins: rgmii0-pins { + pins = "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH9", "PH10", + "PH14", "PH15", "PH16", "PH17", "PH18"; + allwinner,pinmux = <5>; + function = "emac0"; + drive-strength = <40>; + bias-disable; + }; + mmc0_pins: mmc0-pins { pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; allwinner,pinmux = <2>; @@ -409,6 +419,15 @@ i2c5: i2c@2503400 { #size-cells = <0>; }; + syscon: syscon@3000000 { + compatible = "allwinner,sun55i-a523-system-control", + "allwinner,sun50i-a64-system-control"; + reg = <0x03000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + gic: interrupt-controller@3400000 { compatible = "arm,gic-v3"; #address-cells = <1>; @@ -521,6 +540,28 @@ ohci1: usb@4200400 { status = "disabled"; }; + emac0: ethernet@4500000 { + compatible = "allwinner,sun55i-a523-emac0", + "allwinner,sun50i-a64-emac"; + reg = <0x04500000 0x10000>; + clocks = <&ccu CLK_BUS_EMAC0>; + clock-names = "stmmaceth"; + resets = <&ccu RST_BUS_EMAC0>; + reset-names = "stmmaceth"; + interrupts = ; + interrupt-names = "macirq"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii0_pins>; + syscon = <&syscon>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + r_ccu: clock-controller@7010000 { compatible = "allwinner,sun55i-a523-r-ccu"; reg = <0x7010000 0x250>; From acca163f3f5171b05438114e089e01bedcfeb6c6 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 30 Apr 2025 13:32:06 +0800 Subject: [PATCH 21/27] arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board On Radxa A5E board, the EMAC0 connect to external Maxio MAE0621A PHY, which features a 25MHz crystal, and using PH8 pin as PHY reset. Tested on A5E board with schematic V1.20. Tested-by: Corentin LABBE Signed-off-by: Yixun Lan Link: https://patch.msgid.link/20250430-01-sun55i-emac0-v3-4-6fc000bbccbd@gentoo.org Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 2d2f3af91d05..0f58d92a6adc 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -12,6 +12,7 @@ / { compatible = "radxa,cubie-a5e", "allwinner,sun55i-a527"; aliases { + ethernet0 = &emac0; serial0 = &uart0; }; @@ -54,6 +55,24 @@ &ehci1 { status = "okay"; }; +&emac0 { + phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_cldo3>; + + allwinner,tx-delay-ps = <300>; + allwinner,rx-delay-ps = <400>; + + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { vmmc-supply = <®_cldo3>; cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ From c6800f15998b05a2f412169456682e0dffba7232 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 30 Apr 2025 13:32:07 +0800 Subject: [PATCH 22/27] arm64: dts: allwinner: t527: add EMAC0 to Avaota-A1 board On Avaota A1 board, the EMAC0 connect to an external RTL8211F-CG PHY, which features a 25MHz crystal, and using PH8 pin as PHY reset. Signed-off-by: Yixun Lan Link: https://patch.msgid.link/20250430-01-sun55i-emac0-v3-5-6fc000bbccbd@gentoo.org Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-t527-avaota-a1.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index dea2acc1849b..08127f0cdd35 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -12,6 +12,7 @@ / { compatible = "yuzukihd,avaota-a1", "allwinner,sun55i-t527"; aliases { + ethernet0 = &emac0; serial0 = &uart0; }; @@ -64,6 +65,24 @@ &ehci1 { status = "okay"; }; +&emac0 { + phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii_phy>; + phy-supply = <®_dcdc4>; + + allwinner,tx-delay-ps = <100>; + allwinner,rx-delay-ps = <300>; + + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + &mmc0 { vmmc-supply = <®_cldo3>; cd-gpios = <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ From d8f10550448b03d3c5c6d9392119205c65ebfc89 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 5 May 2025 21:24:16 +0100 Subject: [PATCH 23/27] arm64: dts: allwinner: a100: set maximum MMC frequency The manual for the Allwinner A133 SoC mentions that the maximum supported MMC frequency is 150 MHz, for all of the MMC devices. Describe that in the DT entry, to help drivers setting the right interface frequency. Fixes: fcfbb8d9ec58 ("arm64: allwinner: a100: Add MMC related nodes") Signed-off-by: Andre Przywara Link: https://patch.msgid.link/20250505202416.23753-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index f9f6fea03b74..bd366389b238 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -252,6 +252,7 @@ mmc0: mmc@4020000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; + max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -267,6 +268,7 @@ mmc1: mmc@4021000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; + max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -282,6 +284,7 @@ mmc2: mmc@4022000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; + max-frequency = <150000000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; From d010f85f1acf7b109646de9f1812128289bd2414 Mon Sep 17 00:00:00 2001 From: Michael Klein Date: Thu, 8 May 2025 19:36:56 +0200 Subject: [PATCH 24/27] ARM: dts: bananapi: add support for PHY LEDs The RTL8211E ethernet PHY driver has recently gained support for controlling PHY LEDs via /sys/class/leds. The Bananapi M1 has three LEDs connected to the RTL8211E PHY. Add the corresponding nodes to the device tree. Signed-off-by: Michael Klein Link: https://patch.msgid.link/20250508173657.8695-1-michael@fossekall.de Signed-off-by: Chen-Yu Tsai --- .../boot/dts/allwinner/sun7i-a20-bananapi.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts index 46ecf9db2324..d8b362c9661a 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts @@ -48,6 +48,7 @@ #include #include +#include / { model = "LeMaker Banana Pi"; @@ -169,6 +170,32 @@ &ir0 { &gmac_mdio { phy1: ethernet-phy@1 { reg = <1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; }; }; From 9baa27a2e9fc746143ab686b6dbe2d515284a4c5 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 5 May 2025 17:47:27 +0100 Subject: [PATCH 25/27] dt-bindings: vendor-prefixes: Add Liontron name Liontron is a company based in Shenzen, China, making industrial development boards and embedded computers, mostly using Rockchip and Allwinner SoCs. Add their name to the list of vendors. Signed-off-by: Andre Przywara Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250505164729.18175-2-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 411fd65e0bde..580dfd62dc9a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -864,6 +864,8 @@ patternProperties: description: Linux-specific binding "^linx,.*": description: Linx Technologies + "^liontron,.*": + description: Shenzhen Liontron Technology Co., Ltd "^liteon,.*": description: LITE-ON Technology Corp. "^litex,.*": From d26382bb852cd9020a276765d3f2695f2aa7f607 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 5 May 2025 17:47:28 +0100 Subject: [PATCH 26/27] dt-bindings: arm: sunxi: Add Liontron H-A133L board name The Liontron H-A133L is an industrial development board using the Allwinner A133 SoC. Add its compatible name to the list of valid board names. Signed-off-by: Andre Przywara Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250505164729.18175-3-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index cb354c2c61b2..7807ea613258 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -492,6 +492,11 @@ properties: - const: lamobo,lamobo-r1 - const: allwinner,sun7i-a20 + - description: Liontron H-A133L + items: + - const: liontron,h-a133l + - const: allwinner,sun50i-a100 + - description: HAOYU Electronics Marsboard A10 items: - const: haoyu,a10-marsboard From a3cd12acb7b74d9b243cd893209972fc657d0bd3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 5 May 2025 17:47:29 +0100 Subject: [PATCH 27/27] arm64: dts: allwinner: a100: add Liontron H-A133L board support The H-A133L board is an industrial development board made by Liontron. It contains a number of dedicated JST connectors, to connect external peripherals. It features: - Allwinner A133 SoC (4 * Arm Cortex-A53 cores at up to 1.6 GHz) - 1 GiB, 2 GiB or 4 GiB of LPDDR4 DRAM - between 16 and 128 GiB eMMC flash - AXP707 PMIC (compatible to AXP803) - 100 Mbit/s RJ45 Ethernet socket, using an JLSemi JL1101 PHY - XR829 WIFI+Bluetooth chip - 2 * USB 2.0 USB-A ports, plus three sets of USB pins on connectors (connected via a USB hub connected to USB1 on the SoC) - microSD card slot - 3.5mm A/V port - 12V power supply - connectors for an LVDS or MIPI-DSI panel Add the devicetree describing the board's peripherals and their connections. Despite being a devboard, the manufacturer does not publish a schematic (I asked), so the PMIC rail assignments were bases on BSP dumps, educated guesses and some experimentation. Dropping the always-on property from any of the rails carrying it will make the board hang as soon as the kernel turns off unused regulators. Signed-off-by: Andre Przywara Link: https://patch.msgid.link/20250505164729.18175-4-andre.przywara@arm.com [wens@csie.org: fix property in &usbphy; fix comment typo in &usb_otg] Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../sun50i-a133-liontron-h-a133l.dts | 211 ++++++++++++++++++ 2 files changed, 212 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 790aad3a91e8..773cc02a13d0 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h64-remix-mini-pc.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a133-liontron-h-a133l.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts new file mode 100644 index 000000000000..fe77178d3e33 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-a100.dtsi" +#include "sun50i-a100-cpu-opp.dtsi" + +#include +#include + +/{ + model = "Liontron H-A133L"; + compatible = "liontron,h-a133l", "allwinner,sun50i-a100"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; /* PH16 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from a 12V->5V regulator */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_eldo1>; + cap-mmc-hw-reset; + non-removable; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_dcdc1>; + vcc-pc-supply = <®_eldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-ph-supply = <®_dcdc1>; +}; + +&r_i2c0 { + status = "okay"; + + axp803: pmic@34 { + compatible = "x-powers,axp803"; + reg = <0x34>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp803.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-codec-avcc"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dram-1"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb-pl"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io-usb-pd-emmc"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-cpux"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-usb-cpus"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc-dram"; +}; + +/* DCDC6 unused */ +/* DLDO3 unused */ +/* DLDO4 unused */ + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc-emmc"; +}; + +/* ELDO2 unused */ +/* ELDO3 unused */ + +®_fldo1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-cpus-usb"; +}; + +/* reg_drivevbus unused */ +/* dc1sw unused */ + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; /* USB A type receptacle, always powered */ + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +};