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clk: eyeq: Drop PLL, dividers, and fixed factors structs

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Now that there are no users of the eqc_pll, eqc_div, and eqc_fixed_factor
structures since they have been converted to eqc_clock, remove these
structs and the code related to their parsing in probe and early
initialization.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
This commit is contained in:
Benoît Monin 2025-12-10 18:14:20 +01:00
parent 5e80c4b4f4
commit 0fe7490b03
1 changed files with 3 additions and 189 deletions
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192
drivers/clk/clk-eyeq.c
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@ -78,33 +78,6 @@
#define PARENT_BY_FWNAME (-1)
#define PARENT_BY_NAME (-2)
struct eqc_pll {
unsigned int index;
const char *name;
unsigned int reg64;
};
/*
* Divider clock. Divider is 2*(v+1), with v the register value.
* Min divider is 2, max is 2*(2^width).
*/
struct eqc_div {
unsigned int index;
const char *name;
unsigned int parent;
unsigned int reg;
u8 shift;
u8 width;
};
struct eqc_fixed_factor {
unsigned int index;
const char *name;
unsigned int mult;
unsigned int div;
unsigned int parent;
};
struct eqc_clock {
int index;
int parent_idx;
@ -133,15 +106,6 @@ struct eqc_clock {
};
struct eqc_match_data {
unsigned int pll_count;
const struct eqc_pll *plls;
unsigned int div_count;
const struct eqc_div *divs;
unsigned int fixed_factor_count;
const struct eqc_fixed_factor *fixed_factors;
unsigned int clk_count;
const struct eqc_clock *clks;
@ -153,12 +117,6 @@ struct eqc_match_data {
};
struct eqc_early_match_data {
unsigned int early_pll_count;
const struct eqc_pll *early_plls;
unsigned int early_fixed_factor_count;
const struct eqc_fixed_factor *early_fixed_factors;
unsigned int early_clk_count;
const struct eqc_clock *early_clks;
@ -271,97 +229,6 @@ static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult,
return 0;
}
static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data *data,
void __iomem *base, struct clk_hw_onecell_data *cells)
{
unsigned long mult, div, acc;
const struct eqc_pll *pll;
struct clk_hw *hw;
unsigned int i;
int ret;
for (i = 0; i < data->pll_count; i++) {
pll = &data->plls[i];
ret = eqc_pll_parse_fracg(base + pll->reg64, &mult, &div, &acc);
if (ret) {
dev_warn(dev, "failed parsing state of %s\n", pll->name);
cells->hws[pll->index] = ERR_PTR(ret);
continue;
}
hw = clk_hw_register_fixed_factor_with_accuracy_fwname(dev,
dev->of_node, pll->name, "ref", 0, mult, div, acc);
cells->hws[pll->index] = hw;
if (IS_ERR(hw))
dev_warn(dev, "failed registering %s: %pe\n", pll->name, hw);
}
}
static void eqc_probe_init_divs(struct device *dev, const struct eqc_match_data *data,
void __iomem *base, struct clk_hw_onecell_data *cells)
{
struct clk_parent_data parent_data = { };
const struct eqc_div *div;
struct clk_hw *parent;
void __iomem *reg;
struct clk_hw *hw;
unsigned int i;
for (i = 0; i < data->div_count; i++) {
div = &data->divs[i];
reg = base + div->reg;
parent = cells->hws[div->parent];
if (IS_ERR(parent)) {
/* Parent is in early clk provider. */
parent_data.index = div->parent;
parent_data.hw = NULL;
} else {
/* Avoid clock lookup when we already have the hw reference. */
parent_data.index = 0;
parent_data.hw = parent;
}
hw = clk_hw_register_divider_table_parent_data(dev, div->name,
&parent_data, 0, reg, div->shift, div->width,
CLK_DIVIDER_EVEN_INTEGERS, NULL, NULL);
cells->hws[div->index] = hw;
if (IS_ERR(hw))
dev_warn(dev, "failed registering %s: %pe\n",
div->name, hw);
}
}
static void eqc_probe_init_fixed_factors(struct device *dev,
const struct eqc_match_data *data,
struct clk_hw_onecell_data *cells)
{
const struct eqc_fixed_factor *ff;
struct clk_hw *hw, *parent_hw;
unsigned int i;
for (i = 0; i < data->fixed_factor_count; i++) {
ff = &data->fixed_factors[i];
parent_hw = cells->hws[ff->parent];
if (IS_ERR(parent_hw)) {
/* Parent is in early clk provider. */
hw = clk_hw_register_fixed_factor_index(dev, ff->name,
ff->parent, 0, ff->mult, ff->div);
} else {
/* Avoid clock lookup when we already have the hw reference. */
hw = clk_hw_register_fixed_factor_parent_hw(dev, ff->name,
parent_hw, 0, ff->mult, ff->div);
}
cells->hws[ff->index] = hw;
if (IS_ERR(hw))
dev_warn(dev, "failed registering %s: %pe\n",
ff->name, hw);
}
}
static void eqc_auxdev_create_optional(struct device *dev, void __iomem *base,
const char *name)
{
@ -500,12 +367,10 @@ static int eqc_probe(struct platform_device *pdev)
eqc_auxdev_create_optional(dev, base, data->pinctrl_auxdev_name);
eqc_auxdev_create_optional(dev, base, data->eth_phy_auxdev_name);
if (data->pll_count + data->div_count + data->fixed_factor_count + data->clk_count == 0)
if (data->clk_count == 0)
return 0; /* Zero clocks, we are done. */
clk_count = data->pll_count + data->div_count +
data->fixed_factor_count + data->clk_count +
data->early_clk_count;
clk_count = data->clk_count + data->early_clk_count;
cells = kzalloc_flex(*cells, hws, clk_count);
if (!cells)
return -ENOMEM;
@ -516,12 +381,6 @@ static int eqc_probe(struct platform_device *pdev)
for (i = 0; i < clk_count; i++)
cells->hws[i] = ERR_PTR(-EINVAL);
eqc_probe_init_plls(dev, data, base, cells);
eqc_probe_init_divs(dev, data, base, cells);
eqc_probe_init_fixed_factors(dev, data, cells);
for (i = 0; i < data->clk_count; i++) {
const struct eqc_clock *clk = &data->clks[i];
@ -872,8 +731,7 @@ static void __init eqc_early_init(struct device_node *np,
void __iomem *base;
int ret;
clk_count = early_data->early_pll_count + early_data->early_fixed_factor_count +
early_data->early_clk_count + early_data->late_clk_count;
clk_count = early_data->early_clk_count + early_data->late_clk_count;
cells = kzalloc_flex(*cells, hws, clk_count);
if (!cells) {
ret = -ENOMEM;
@ -899,42 +757,6 @@ static void __init eqc_early_init(struct device_node *np,
goto err;
}
for (i = 0; i < early_data->early_pll_count; i++) {
const struct eqc_pll *pll = &early_data->early_plls[i];
unsigned long mult, div, acc;
struct clk_hw *hw;
ret = eqc_pll_parse_fracg(base + pll->reg64, &mult, &div, &acc);
if (ret) {
pr_err("failed parsing state of %s\n", pll->name);
goto err;
}
hw = clk_hw_register_fixed_factor_with_accuracy_fwname(NULL,
np, pll->name, "ref", 0, mult, div, acc);
cells->hws[pll->index] = hw;
if (IS_ERR(hw)) {
pr_err("failed registering %s: %pe\n", pll->name, hw);
ret = PTR_ERR(hw);
goto err;
}
}
for (i = 0; i < early_data->early_fixed_factor_count; i++) {
const struct eqc_fixed_factor *ff = &early_data->early_fixed_factors[i];
struct clk_hw *parent_hw = cells->hws[ff->parent];
struct clk_hw *hw;
hw = clk_hw_register_fixed_factor_parent_hw(NULL, ff->name,
parent_hw, 0, ff->mult, ff->div);
cells->hws[ff->index] = hw;
if (IS_ERR(hw)) {
pr_err("failed registering %s: %pe\n", ff->name, hw);
ret = PTR_ERR(hw);
goto err;
}
}
for (i = 0; i < early_data->early_clk_count; i++) {
const struct eqc_clock *clk = &early_data->early_clks[i];
@ -969,14 +791,6 @@ static void __init eqc_early_init(struct device_node *np,
if (cells) {
of_clk_del_provider(np);
for (i = 0; i < early_data->early_pll_count; i++) {
const struct eqc_pll *pll = &early_data->early_plls[i];
struct clk_hw *hw = cells->hws[pll->index];
if (!IS_ERR_OR_NULL(hw))
clk_hw_unregister_fixed_factor(hw);
}
for (i = 0; i < early_data->early_clk_count; i++) {
const struct eqc_clock *clk = &early_data->early_clks[i];
struct clk_hw *hw = cells->hws[clk->index];