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ASoC: tegra: Fixes for issues exposed in Linux v7.2

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Jon Hunter <jonathanh@nvidia.com> says:

Commit 4b05ccb17f ("regcache: Sort the local copy of an unsorted
reg_defaults array") exposed an issue in the Tegra I2S and MIXER drivers
and after this commit was added, this underlying issue now causes audio
tests that exercise the I2S and MIXER drivers to fail. This series fixes
the issue in the I2S and MIXER drivers and also fixes warning observed
with the ADMAIF and MBDRC drivers that have unsorted reg_defaults.

Link: https://patch.msgid.link/20260821153734.158426-1-jonathanh@nvidia.com
This commit is contained in:
Mark Brown 2026-08-21 18:08:40 +01:00
commit 0fd298233f
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
5 changed files with 185 additions and 98 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

210
sound/soc/tegra/tegra210_admaif.c
View File

@ -26,94 +26,162 @@
#define CH_RX_REG(reg, id) CH_REG(admaif->soc_data->rx_base, reg, id)
#define REG_DEFAULTS(id, rx_ctrl, tx_ctrl, tx_base, rx_base, cif_ctrl) \
#define RX_REG_DEFAULTS(id, rx_ctrl, rx_base, cif_ctrl) \
{ CH_REG(rx_base, TEGRA_ADMAIF_RX_INT_MASK, id), 0x00000001 }, \
{ CH_REG(rx_base, TEGRA_ADMAIF_CH_ACIF_RX_CTRL, id), cif_ctrl }, \
{ CH_REG(rx_base, TEGRA_ADMAIF_RX_FIFO_CTRL, id), rx_ctrl }, \
{ CH_REG(rx_base, TEGRA_ADMAIF_RX_FIFO_CTRL, id), rx_ctrl }
#define TX_REG_DEFAULTS(id, tx_ctrl, tx_base, cif_ctrl) \
{ CH_REG(tx_base, TEGRA_ADMAIF_TX_INT_MASK, id), 0x00000001 }, \
{ CH_REG(tx_base, TEGRA_ADMAIF_CH_ACIF_TX_CTRL, id), cif_ctrl }, \
{ CH_REG(tx_base, TEGRA_ADMAIF_TX_FIFO_CTRL, id), tx_ctrl }
#define ADMAIF_REG_DEFAULTS(id, chip) \
REG_DEFAULTS((id) - 1, \
#define ADMAIF_RX_REG_DEFAULTS(id, chip) \
RX_REG_DEFAULTS((id) - 1, \
chip ## _ADMAIF_RX ## id ## _FIFO_CTRL_REG_DEFAULT, \
chip ## _ADMAIF_TX ## id ## _FIFO_CTRL_REG_DEFAULT, \
chip ## _ADMAIF_TX_BASE, \
chip ## _ADMAIF_RX_BASE, \
chip ## _ADMAIF_CIF_REG_DEFAULT)
#define ADMAIF_TX_REG_DEFAULTS(id, chip) \
TX_REG_DEFAULTS((id) - 1, \
chip ## _ADMAIF_TX ## id ## _FIFO_CTRL_REG_DEFAULT, \
chip ## _ADMAIF_TX_BASE, \
chip ## _ADMAIF_CIF_REG_DEFAULT)
static const struct reg_default tegra186_admaif_reg_defaults[] = {
{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA186_ADMAIF_GLOBAL_BASE), 0x00000003},
ADMAIF_REG_DEFAULTS(1, TEGRA186),
ADMAIF_REG_DEFAULTS(2, TEGRA186),
ADMAIF_REG_DEFAULTS(3, TEGRA186),
ADMAIF_REG_DEFAULTS(4, TEGRA186),
ADMAIF_REG_DEFAULTS(5, TEGRA186),
ADMAIF_REG_DEFAULTS(6, TEGRA186),
ADMAIF_REG_DEFAULTS(7, TEGRA186),
ADMAIF_REG_DEFAULTS(8, TEGRA186),
ADMAIF_REG_DEFAULTS(9, TEGRA186),
ADMAIF_REG_DEFAULTS(10, TEGRA186),
ADMAIF_REG_DEFAULTS(11, TEGRA186),
ADMAIF_REG_DEFAULTS(12, TEGRA186),
ADMAIF_REG_DEFAULTS(13, TEGRA186),
ADMAIF_REG_DEFAULTS(14, TEGRA186),
ADMAIF_REG_DEFAULTS(15, TEGRA186),
ADMAIF_REG_DEFAULTS(16, TEGRA186),
ADMAIF_REG_DEFAULTS(17, TEGRA186),
ADMAIF_REG_DEFAULTS(18, TEGRA186),
ADMAIF_REG_DEFAULTS(19, TEGRA186),
ADMAIF_REG_DEFAULTS(20, TEGRA186)
ADMAIF_RX_REG_DEFAULTS(1, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(2, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(3, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(4, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(5, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(6, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(7, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(8, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(9, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(10, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(11, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(12, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(13, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(14, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(15, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(16, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(17, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(18, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(19, TEGRA186),
ADMAIF_RX_REG_DEFAULTS(20, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(1, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(2, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(3, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(4, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(5, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(6, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(7, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(8, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(9, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(10, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(11, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(12, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(13, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(14, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(15, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(16, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(17, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(18, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(19, TEGRA186),
ADMAIF_TX_REG_DEFAULTS(20, TEGRA186),
{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA186_ADMAIF_GLOBAL_BASE), 0x00000003}
};
static const struct reg_default tegra210_admaif_reg_defaults[] = {
{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA210_ADMAIF_GLOBAL_BASE), 0x00000003},
ADMAIF_REG_DEFAULTS(1, TEGRA210),
ADMAIF_REG_DEFAULTS(2, TEGRA210),
ADMAIF_REG_DEFAULTS(3, TEGRA210),
ADMAIF_REG_DEFAULTS(4, TEGRA210),
ADMAIF_REG_DEFAULTS(5, TEGRA210),
ADMAIF_REG_DEFAULTS(6, TEGRA210),
ADMAIF_REG_DEFAULTS(7, TEGRA210),
ADMAIF_REG_DEFAULTS(8, TEGRA210),
ADMAIF_REG_DEFAULTS(9, TEGRA210),
ADMAIF_REG_DEFAULTS(10, TEGRA210)
ADMAIF_RX_REG_DEFAULTS(1, TEGRA210),
ADMAIF_RX_REG_DEFAULTS(2, TEGRA210),
ADMAIF_RX_REG_DEFAULTS(3, TEGRA210),
ADMAIF_RX_REG_DEFAULTS(4, TEGRA210),
ADMAIF_RX_REG_DEFAULTS(5, TEGRA210),
ADMAIF_RX_REG_DEFAULTS(6, TEGRA210),
ADMAIF_RX_REG_DEFAULTS(7, TEGRA210),
ADMAIF_RX_REG_DEFAULTS(8, TEGRA210),
ADMAIF_RX_REG_DEFAULTS(9, TEGRA210),
ADMAIF_RX_REG_DEFAULTS(10, TEGRA210),
ADMAIF_TX_REG_DEFAULTS(1, TEGRA210),
ADMAIF_TX_REG_DEFAULTS(2, TEGRA210),
ADMAIF_TX_REG_DEFAULTS(3, TEGRA210),
ADMAIF_TX_REG_DEFAULTS(4, TEGRA210),
ADMAIF_TX_REG_DEFAULTS(5, TEGRA210),
ADMAIF_TX_REG_DEFAULTS(6, TEGRA210),
ADMAIF_TX_REG_DEFAULTS(7, TEGRA210),
ADMAIF_TX_REG_DEFAULTS(8, TEGRA210),
ADMAIF_TX_REG_DEFAULTS(9, TEGRA210),
ADMAIF_TX_REG_DEFAULTS(10, TEGRA210),
{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA210_ADMAIF_GLOBAL_BASE), 0x00000003}
};
static const struct reg_default tegra264_admaif_reg_defaults[] = {
{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA264_ADMAIF_GLOBAL_BASE), 0x00000003},
ADMAIF_REG_DEFAULTS(1, TEGRA264),
ADMAIF_REG_DEFAULTS(2, TEGRA264),
ADMAIF_REG_DEFAULTS(3, TEGRA264),
ADMAIF_REG_DEFAULTS(4, TEGRA264),
ADMAIF_REG_DEFAULTS(5, TEGRA264),
ADMAIF_REG_DEFAULTS(6, TEGRA264),
ADMAIF_REG_DEFAULTS(7, TEGRA264),
ADMAIF_REG_DEFAULTS(8, TEGRA264),
ADMAIF_REG_DEFAULTS(9, TEGRA264),
ADMAIF_REG_DEFAULTS(10, TEGRA264),
ADMAIF_REG_DEFAULTS(11, TEGRA264),
ADMAIF_REG_DEFAULTS(12, TEGRA264),
ADMAIF_REG_DEFAULTS(13, TEGRA264),
ADMAIF_REG_DEFAULTS(14, TEGRA264),
ADMAIF_REG_DEFAULTS(15, TEGRA264),
ADMAIF_REG_DEFAULTS(16, TEGRA264),
ADMAIF_REG_DEFAULTS(17, TEGRA264),
ADMAIF_REG_DEFAULTS(18, TEGRA264),
ADMAIF_REG_DEFAULTS(19, TEGRA264),
ADMAIF_REG_DEFAULTS(20, TEGRA264),
ADMAIF_REG_DEFAULTS(21, TEGRA264),
ADMAIF_REG_DEFAULTS(22, TEGRA264),
ADMAIF_REG_DEFAULTS(23, TEGRA264),
ADMAIF_REG_DEFAULTS(24, TEGRA264),
ADMAIF_REG_DEFAULTS(25, TEGRA264),
ADMAIF_REG_DEFAULTS(26, TEGRA264),
ADMAIF_REG_DEFAULTS(27, TEGRA264),
ADMAIF_REG_DEFAULTS(28, TEGRA264),
ADMAIF_REG_DEFAULTS(29, TEGRA264),
ADMAIF_REG_DEFAULTS(30, TEGRA264),
ADMAIF_REG_DEFAULTS(31, TEGRA264),
ADMAIF_REG_DEFAULTS(32, TEGRA264)
ADMAIF_RX_REG_DEFAULTS(1, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(2, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(3, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(4, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(5, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(6, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(7, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(8, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(9, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(10, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(11, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(12, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(13, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(14, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(15, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(16, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(17, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(18, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(19, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(20, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(21, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(22, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(23, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(24, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(25, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(26, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(27, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(28, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(29, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(30, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(31, TEGRA264),
ADMAIF_RX_REG_DEFAULTS(32, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(1, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(2, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(3, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(4, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(5, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(6, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(7, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(8, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(9, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(10, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(11, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(12, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(13, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(14, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(15, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(16, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(17, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(18, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(19, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(20, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(21, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(22, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(23, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(24, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(25, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(26, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(27, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(28, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(29, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(30, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(31, TEGRA264),
ADMAIF_TX_REG_DEFAULTS(32, TEGRA264),
{(TEGRA_ADMAIF_GLOBAL_CG_0 + TEGRA264_ADMAIF_GLOBAL_BASE), 0x00000003}
};
static bool tegra_admaif_wr_reg(struct device *dev, unsigned int reg)

20
sound/soc/tegra/tegra210_i2s.c
View File

@ -23,7 +23,7 @@ static const struct reg_default tegra210_i2s_reg_defaults[] = {
{ TEGRA210_I2S_RX_CIF_CTRL, 0x00007700 },
{ TEGRA210_I2S_TX_INT_MASK, 0x00000003 },
{ TEGRA210_I2S_TX_CIF_CTRL, 0x00007700 },
{ TEGRA210_I2S_ENABLE, 0x1 },
{ TEGRA210_I2S_ENABLE, 0x0 },
{ TEGRA210_I2S_CG, 0x1 },
{ TEGRA210_I2S_TIMING, 0x0000001f },
/*
@ -42,7 +42,7 @@ static const struct reg_default tegra264_i2s_reg_defaults[] = {
{ TEGRA264_I2S_TX_INT_MASK, 0x00000003 },
{ TEGRA264_I2S_TX_CIF_CTRL, 0x00003f00 },
{ TEGRA264_I2S_TX_FIFO_RD_ACCESS_MODE, 0x1 },
{ TEGRA264_I2S_ENABLE, 0x1 },
{ TEGRA264_I2S_ENABLE, 0x0 },
{ TEGRA264_I2S_CG, 0x1 },
{ TEGRA264_I2S_TIMING, 0x0000001f },
};
@ -201,9 +201,21 @@ static int tegra210_i2s_runtime_resume(struct device *dev)
}
regcache_cache_only(i2s->regmap, false);
regcache_sync(i2s->regmap);
err = regcache_sync(i2s->regmap);
if (err)
goto err;
err = regmap_write(i2s->regmap, i2s->soc_data->enable_reg, I2S_EN);
if (err)
goto err;
return 0;
err:
regcache_cache_only(i2s->regmap, true);
clk_disable_unprepare(i2s->clk_i2s);
return err;
}
static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s,
@ -1133,6 +1145,7 @@ static const struct tegra_i2s_soc_data soc_data_tegra210 = {
.regmap_conf = &tegra210_regmap_conf,
.i2s_cmpnt = &tegra210_i2s_cmpnt,
.max_ch = TEGRA210_I2S_MAX_CHANNEL,
.enable_reg = TEGRA210_I2S_ENABLE,
.tx_offset = TEGRA210_I2S_TX_OFFSET,
.i2s_ctrl_offset = TEGRA210_I2S_CTRL_OFFSET,
.fsync_width_mask = I2S_CTRL_FSYNC_WIDTH_MASK,
@ -1144,6 +1157,7 @@ static const struct tegra_i2s_soc_data soc_data_tegra264 = {
.regmap_conf = &tegra264_regmap_conf,
.i2s_cmpnt = &tegra264_i2s_cmpnt,
.max_ch = TEGRA264_I2S_MAX_CHANNEL,
.enable_reg = TEGRA264_I2S_ENABLE,
.tx_offset = TEGRA264_I2S_TX_OFFSET,
.i2s_ctrl_offset = TEGRA264_I2S_CTRL_OFFSET,
.fsync_width_mask = TEGRA264_I2S_CTRL_FSYNC_WIDTH_MASK,

1
sound/soc/tegra/tegra210_i2s.h
View File

@ -150,6 +150,7 @@ struct tegra_i2s_soc_data {
const struct regmap_config *regmap_conf;
const struct snd_soc_component_driver *i2s_cmpnt;
unsigned int max_ch;
unsigned int enable_reg;
unsigned int tx_offset;
unsigned int i2s_ctrl_offset;
unsigned int fsync_width_mask;

42
sound/soc/tegra/tegra210_mbdrc.c
View File

@ -20,33 +20,33 @@
#define MBDRC_FILTER_REG(reg, id) \
((reg) + ((id) * TEGRA210_MBDRC_FILTER_PARAM_STRIDE))
#define MBDRC_FILTER_REG_DEFAULTS(id) \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IIR_CFG, id), 0x00000005}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_ATTACK, id), 0x3e48590c}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_RELEASE, id), 0x08414e9f}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_FAST_ATTACK, id), 0x7fffffff}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_IN_THRESHOLD, id), 0x06145082}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_OUT_THRESHOLD, id), 0x060d379b}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_1ST, id), 0x0000a000}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_2ND, id), 0x00002000}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_3RD, id), 0x00000b33}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_4TH, id), 0x00000800}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_RATIO_5TH, id), 0x0000019a}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_MAKEUP_GAIN, id), 0x00000002}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_INIT_GAIN, id), 0x00066666}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_GAIN_ATTACK, id), 0x00d9ba0e}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_GAIN_RELEASE, id), 0x3e48590c}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_FAST_RELEASE, id), 0x7ffff26a}, \
{ MBDRC_FILTER_REG(TEGRA210_MBDRC_CFG_RAM_CTRL, id), 0x4000}
#define MBDRC_FILTER_PARAM_REG_DEFAULTS(reg, val) \
{ MBDRC_FILTER_REG(reg, 0), val}, \
{ MBDRC_FILTER_REG(reg, 1), val}, \
{ MBDRC_FILTER_REG(reg, 2), val}
static const struct reg_default tegra210_mbdrc_reg_defaults[] = {
{ TEGRA210_MBDRC_CFG, 0x0030de51},
{ TEGRA210_MBDRC_CHANNEL_MASK, 0x00000003},
{ TEGRA210_MBDRC_FAST_FACTOR, 0x30000800},
MBDRC_FILTER_REG_DEFAULTS(0),
MBDRC_FILTER_REG_DEFAULTS(1),
MBDRC_FILTER_REG_DEFAULTS(2),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_IIR_CFG, 0x00000005),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_IN_ATTACK, 0x3e48590c),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_IN_RELEASE, 0x08414e9f),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_FAST_ATTACK, 0x7fffffff),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_IN_THRESHOLD, 0x06145082),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_OUT_THRESHOLD, 0x060d379b),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_RATIO_1ST, 0x0000a000),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_RATIO_2ND, 0x00002000),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_RATIO_3RD, 0x00000b33),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_RATIO_4TH, 0x00000800),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_RATIO_5TH, 0x0000019a),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_MAKEUP_GAIN, 0x00000002),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_INIT_GAIN, 0x00066666),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_GAIN_ATTACK, 0x00d9ba0e),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_GAIN_RELEASE, 0x3e48590c),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_FAST_RELEASE, 0x7ffff26a),
MBDRC_FILTER_PARAM_REG_DEFAULTS(TEGRA210_MBDRC_CFG_RAM_CTRL, 0x4000),
};
/* Default MBDRC parameters */

10
sound/soc/tegra/tegra210_mixer.c
View File

@ -57,7 +57,7 @@ static const struct reg_default tegra210_mixer_reg_defaults[] = {
MIXER_TX_REG_DEFAULTS(3),
MIXER_TX_REG_DEFAULTS(4),
{ TEGRA210_MIXER_ENABLE, 0x1 },
{ TEGRA210_MIXER_ENABLE, 0x0 },
{ TEGRA210_MIXER_CG, 0x00000001},
{ TEGRA210_MIXER_GAIN_CFG_RAM_CTRL, 0x00004000},
{ TEGRA210_MIXER_PEAKM_RAM_CTRL, 0x00004000},
@ -86,11 +86,15 @@ static int tegra210_mixer_runtime_suspend(struct device *dev)
static int tegra210_mixer_runtime_resume(struct device *dev)
{
struct tegra210_mixer *mixer = dev_get_drvdata(dev);
int err;
regcache_cache_only(mixer->regmap, false);
regcache_sync(mixer->regmap);
err = regcache_sync(mixer->regmap);
if (err)
return err;
return 0;
return regmap_write(mixer->regmap, TEGRA210_MIXER_ENABLE,
TEGRA210_MIXER_EN);
}
static int tegra210_mixer_write_ram(struct tegra210_mixer *mixer,