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spi: bcm63xx-hsspi: add support for 1-2-2 read ops
Add support for 1-2-2 read ops by separately calculating the switch from single-bit to multi-bit, and then switching within the prepend data. This allows us to support single-bit write followed by multi-bit write followed by multi-bit read, and we do not need to reject 1-2-2 read operations anymore. Tested on BCM963268BU_P300 with custom fixup to allow 1-2-2 on the non-SDFP capable s25fl129p1 attached (which it actually supports): root@OpenWrt:~# cat /sys/kernel/debug/spi-nor/spi1.0/params name s25fl129p1 id 01 20 18 4d 01 01 size 16.0 MiB write size 1 page size 256 address nbytes 3 flags HAS_16BIT_SR | NO_READ_CR opcodes read 0xbb dummy cycles 4 erase 0xd8 program 0x02 8D extension none protocols read 1S-2S-2S write 1S-1S-1S register 1S-1S-1S Reading from flash is still working as expected: [ 1.070000] parser_imagetag: rootfs: CFE image tag found at 0x0 with version 6, board type 963168VX [ 1.080000] parser_imagetag: Partition 0 is rootfs offset 100 and length 665000 [ 1.090000] parser_imagetag: Partition 1 is kernel offset 665100 and length 136fa1 [ 1.100000] parser_imagetag: Spare partition is offset 7b0000 and length 30000 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Acked-by: William Zhang <william.zhang@broadcom.com> Tested-by: David Regan <dregan@broadcom.com> Link: https://patch.msgid.link/20251217211026.173946-1-jonas.gorski@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -142,6 +142,7 @@ struct bcm63xx_hsspi {
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u32 wait_mode;
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u32 xfer_mode;
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u32 prepend_cnt;
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u32 md_start;
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u8 *prepend_buf;
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};
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@ -268,18 +269,20 @@ static bool bcm63xx_prepare_prepend_transfer(struct spi_controller *host,
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{
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struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
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bool tx_only = false;
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bool tx_only = false, multidata = false;
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struct spi_transfer *t;
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/*
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* Multiple transfers within a message may be combined into one transfer
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* to the controller using its prepend feature. A SPI message is prependable
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* only if the following are all true:
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* 1. One or more half duplex write transfer in single bit mode
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* 2. Optional full duplex read/write at the end
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* 3. No delay and cs_change between transfers
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* 1. One or more half duplex write transfers at the start
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* 2. Optional switch from single to dual bit within the write transfers
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* 3. Optional full duplex read/write at the end if all single bit
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* 4. No delay and cs_change between transfers
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*/
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bs->prepend_cnt = 0;
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bs->md_start = 0;
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list_for_each_entry(t, &msg->transfers, transfer_list) {
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if ((spi_delay_to_ns(&t->delay, t) > 0) || t->cs_change) {
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bcm63xx_prepend_printk_on_checkfail(bs,
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@ -297,31 +300,44 @@ static bool bcm63xx_prepare_prepend_transfer(struct spi_controller *host,
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return false;
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}
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if (t->tx_nbits > SPI_NBITS_SINGLE &&
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!list_is_last(&t->transfer_list, &msg->transfers)) {
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if (t->tx_nbits == SPI_NBITS_SINGLE &&
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!list_is_last(&t->transfer_list, &msg->transfers) &&
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multidata) {
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bcm63xx_prepend_printk_on_checkfail(bs,
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"multi-bit prepend buf not supported!\n");
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"single-bit after multi-bit not supported!\n");
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return false;
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}
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if (t->tx_nbits == SPI_NBITS_SINGLE) {
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memcpy(bs->prepend_buf + bs->prepend_cnt, t->tx_buf, t->len);
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bs->prepend_cnt += t->len;
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}
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if (t->tx_nbits > SPI_NBITS_SINGLE)
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multidata = true;
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memcpy(bs->prepend_buf + bs->prepend_cnt, t->tx_buf, t->len);
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bs->prepend_cnt += t->len;
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if (t->tx_nbits == SPI_NBITS_SINGLE)
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bs->md_start += t->len;
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} else {
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if (!list_is_last(&t->transfer_list, &msg->transfers)) {
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bcm63xx_prepend_printk_on_checkfail(bs,
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"rx/tx_rx transfer not supported when it is not last one!\n");
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return false;
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}
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if (t->rx_buf && t->rx_nbits == SPI_NBITS_SINGLE &&
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multidata) {
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bcm63xx_prepend_printk_on_checkfail(bs,
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"single-bit after multi-bit not supported!\n");
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return false;
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}
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}
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if (list_is_last(&t->transfer_list, &msg->transfers)) {
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memcpy(t_prepend, t, sizeof(struct spi_transfer));
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if (tx_only && t->tx_nbits == SPI_NBITS_SINGLE) {
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if (tx_only) {
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/*
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* if the last one is also a single bit tx only transfer, merge
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* if the last one is also a tx only transfer, merge
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* all of them into one single tx transfer
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*/
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t_prepend->len = bs->prepend_cnt;
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@ -329,7 +345,7 @@ static bool bcm63xx_prepare_prepend_transfer(struct spi_controller *host,
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bs->prepend_cnt = 0;
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} else {
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/*
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* if the last one is not a tx only transfer or dual tx xfer, all
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* if the last one is not a tx only transfer, all
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* the previous transfers are sent through prepend bytes and
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* make sure it does not exceed the max prepend len
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*/
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@ -339,6 +355,15 @@ static bool bcm63xx_prepare_prepend_transfer(struct spi_controller *host,
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return false;
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}
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}
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/*
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* If switching from single-bit to multi-bit, make sure
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* the start offset does not exceed the maximum
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*/
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if (multidata && bs->md_start > HSSPI_MAX_PREPEND_LEN) {
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bcm63xx_prepend_printk_on_checkfail(bs,
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"exceed max multi-bit offset, abort prepending transfers!\n");
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return false;
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}
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}
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}
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@ -381,11 +406,11 @@ static int bcm63xx_hsspi_do_prepend_txrx(struct spi_device *spi,
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if (t->rx_nbits == SPI_NBITS_DUAL) {
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reg |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT;
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reg |= bs->prepend_cnt << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT;
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reg |= bs->md_start << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT;
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}
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if (t->tx_nbits == SPI_NBITS_DUAL) {
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reg |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT;
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reg |= bs->prepend_cnt << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT;
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reg |= bs->md_start << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT;
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}
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}
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@ -692,13 +717,6 @@ static bool bcm63xx_hsspi_mem_supports_op(struct spi_mem *mem,
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if (!spi_mem_default_supports_op(mem, op))
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return false;
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/* Controller doesn't support spi mem dual io mode */
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if ((op->cmd.opcode == SPINOR_OP_READ_1_2_2) ||
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(op->cmd.opcode == SPINOR_OP_READ_1_2_2_4B) ||
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(op->cmd.opcode == SPINOR_OP_READ_1_2_2_DTR) ||
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(op->cmd.opcode == SPINOR_OP_READ_1_2_2_DTR_4B))
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return false;
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return true;
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}
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