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Merge branch 'pci/controller/xgene'
- Teach handle_simple_irq() to resend an in-progress interrupt (Marc Zyngier) - Defer probing if the MSI widget driver hasn't probed yet (Marc Zyngier) - Drop useless conditional compilation, since pci-xgene.c is only compiled when CONFIG_PCI_XGENE is selected (Marc Zyngier) - Drop useless XGENE_PCIE_IP_VER_UNKN IP version (Marc Zyngier) - Simplify and make per-CPU interrupt setup robust (Marc Zyngier) - Drop superfluous struct xgene_msi fields (Marc Zyngier) - Use device-managed memory allocations (Marc Zyngier) - Drop intermediate xgene_msi_group tracking structure (Marc Zyngier) - Rewrite pci-xgene-msi.c to fix MSI CPU affinity and clean things up (Marc Zyngier) - Resend an MSI racing with itself on a different CPU (Marc Zyngier) - Probe xgene-msi as a standard platform driver rather than a subsys_initcall (Marc Zyngier) - Simplify MSI handler setup/teardown by dropping useless CPU hotplug bits (Marc Zyngier) - Remove unused cpuhp_state CPUHP_PCI_XGENE_DEAD (Marc Zyngier) * pci/controller/xgene: cpu/hotplug: Remove unused cpuhp_state CPUHP_PCI_XGENE_DEAD PCI: xgene-msi: Restructure handler setup/teardown PCI: xgene-msi: Probe as a standard platform driver PCI: xgene-msi: Resend an MSI racing with itself on a different CPU PCI: xgene-msi: Sanitise MSI allocation and affinity setting PCI: xgene-msi: Get rid of intermediate tracking structure PCI: xgene-msi: Use device-managed memory allocations PCI: xgene-msi: Drop superfluous fields from xgene_msi structure PCI: xgene-msi: Make per-CPU interrupt setup robust PCI: xgene: Drop XGENE_PCIE_IP_VER_UNKN PCI: xgene: Drop useless conditional compilation PCI: xgene: Defer probing if the MSI widget driver hasn't probed yet genirq: Teach handle_simple_irq() to resend an in-progress interrupt
This commit is contained in:
Bjorn Helgaas
commit
0edfffd24c
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@ -6,6 +6,7 @@
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* Author: Tanmay Inamdar <tinamdar@apm.com>
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* Duc Dang <dhdang@apm.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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@ -22,31 +23,49 @@
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#define IDX_PER_GROUP 8
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#define IRQS_PER_IDX 16
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#define NR_HW_IRQS 16
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#define NR_MSI_VEC (IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS)
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#define NR_MSI_BITS (IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS)
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#define NR_MSI_VEC (NR_MSI_BITS / num_possible_cpus())
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struct xgene_msi_group {
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struct xgene_msi *msi;
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int gic_irq;
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u32 msi_grp;
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};
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#define MSI_GROUP_MASK GENMASK(22, 19)
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#define MSI_INDEX_MASK GENMASK(18, 16)
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#define MSI_INTR_MASK GENMASK(19, 16)
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#define MSInRx_HWIRQ_MASK GENMASK(6, 4)
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#define DATA_HWIRQ_MASK GENMASK(3, 0)
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struct xgene_msi {
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struct device_node *node;
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struct irq_domain *inner_domain;
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u64 msi_addr;
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void __iomem *msi_regs;
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unsigned long *bitmap;
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struct mutex bitmap_lock;
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struct xgene_msi_group *msi_groups;
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int num_cpus;
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unsigned int gic_irq[NR_HW_IRQS];
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};
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/* Global data */
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static struct xgene_msi xgene_msi_ctrl;
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static struct xgene_msi *xgene_msi_ctrl;
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/*
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* X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where
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* n is group number (0..F), x is index of registers in each group (0..7)
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* X-Gene v1 has 16 frames of MSI termination registers MSInIRx, where n is
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* frame number (0..15), x is index of registers in each frame (0..7). Each
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* 32b register is at the beginning of a 64kB region, each frame occupying
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* 512kB (and the whole thing 8MB of PA space).
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*
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* Each register supports 16 MSI vectors (0..15) to generate interrupts. A
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* write to the MSInIRx from the PCI side generates an interrupt. A read
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* from the MSInRx on the CPU side returns a bitmap of the pending MSIs in
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* the lower 16 bits. A side effect of this read is that all pending
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* interrupts are acknowledged and cleared).
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*
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* Additionally, each MSI termination frame has 1 MSIINTn register (n is
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* 0..15) to indicate the MSI pending status caused by any of its 8
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* termination registers, reported as a bitmap in the lower 8 bits. Each 32b
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* register is at the beginning of a 64kB region (and overall occupying an
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* extra 1MB).
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*
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* There is one GIC IRQ assigned for each MSI termination frame, 16 in
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* total.
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*
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* The register layout is as follows:
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* MSI0IR0 base_addr
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* MSI0IR1 base_addr + 0x10000
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@ -67,107 +86,74 @@ static struct xgene_msi xgene_msi_ctrl;
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* MSIINT1 base_addr + 0x810000
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* ... ...
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* MSIINTF base_addr + 0x8F0000
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*
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* Each index register supports 16 MSI vectors (0..15) to generate interrupt.
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* There are total 16 GIC IRQs assigned for these 16 groups of MSI termination
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* registers.
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*
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* Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate
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* the MSI pending status caused by 1 of its 8 index registers.
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*/
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/* MSInIRx read helper */
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static u32 xgene_msi_ir_read(struct xgene_msi *msi,
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u32 msi_grp, u32 msir_idx)
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static u32 xgene_msi_ir_read(struct xgene_msi *msi, u32 msi_grp, u32 msir_idx)
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{
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return readl_relaxed(msi->msi_regs + MSI_IR0 +
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(msi_grp << 19) + (msir_idx << 16));
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(FIELD_PREP(MSI_GROUP_MASK, msi_grp) |
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FIELD_PREP(MSI_INDEX_MASK, msir_idx)));
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}
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/* MSIINTn read helper */
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static u32 xgene_msi_int_read(struct xgene_msi *msi, u32 msi_grp)
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{
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return readl_relaxed(msi->msi_regs + MSI_INT0 + (msi_grp << 16));
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return readl_relaxed(msi->msi_regs + MSI_INT0 +
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FIELD_PREP(MSI_INTR_MASK, msi_grp));
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}
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/*
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* With 2048 MSI vectors supported, the MSI message can be constructed using
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* following scheme:
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* - Divide into 8 256-vector groups
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* Group 0: 0-255
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* Group 1: 256-511
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* Group 2: 512-767
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* ...
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* Group 7: 1792-2047
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* - Each 256-vector group is divided into 16 16-vector groups
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* As an example: 16 16-vector groups for 256-vector group 0-255 is
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* Group 0: 0-15
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* Group 1: 16-32
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* ...
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* Group 15: 240-255
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* - The termination address of MSI vector in 256-vector group n and 16-vector
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* group x is the address of MSIxIRn
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* - The data for MSI vector in 16-vector group x is x
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* In order to allow an MSI to be moved from one CPU to another without
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* having to repaint both the address and the data (which cannot be done
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* atomically), we statically partitions the MSI frames between CPUs. Given
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* that XGene-1 has 8 CPUs, each CPU gets two frames assigned to it
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*
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* We adopt the convention that when an MSI is moved, it is configured to
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* target the same register number in the congruent frame assigned to the
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* new target CPU. This reserves a given MSI across all CPUs, and reduces
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* the MSI capacity from 2048 to 256.
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*
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* Effectively, this amounts to:
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* - hwirq[7]::cpu[2:0] is the target frame number (n in MSInIRx)
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* - hwirq[6:4] is the register index in any given frame (x in MSInIRx)
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* - hwirq[3:0] is the MSI data
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*/
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static u32 hwirq_to_reg_set(unsigned long hwirq)
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static irq_hw_number_t compute_hwirq(u8 frame, u8 index, u8 data)
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{
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return (hwirq / (NR_HW_IRQS * IRQS_PER_IDX));
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}
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static u32 hwirq_to_group(unsigned long hwirq)
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{
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return (hwirq % NR_HW_IRQS);
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}
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static u32 hwirq_to_msi_data(unsigned long hwirq)
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{
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return ((hwirq / NR_HW_IRQS) % IRQS_PER_IDX);
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return (FIELD_PREP(BIT(7), FIELD_GET(BIT(3), frame)) |
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FIELD_PREP(MSInRx_HWIRQ_MASK, index) |
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FIELD_PREP(DATA_HWIRQ_MASK, data));
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}
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static void xgene_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct xgene_msi *msi = irq_data_get_irq_chip_data(data);
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u32 reg_set = hwirq_to_reg_set(data->hwirq);
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u32 group = hwirq_to_group(data->hwirq);
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u64 target_addr = msi->msi_addr + (((8 * group) + reg_set) << 16);
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u64 target_addr;
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u32 frame, msir;
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int cpu;
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cpu = cpumask_first(irq_data_get_effective_affinity_mask(data));
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msir = FIELD_GET(MSInRx_HWIRQ_MASK, data->hwirq);
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frame = FIELD_PREP(BIT(3), FIELD_GET(BIT(7), data->hwirq)) | cpu;
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target_addr = msi->msi_addr;
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target_addr += (FIELD_PREP(MSI_GROUP_MASK, frame) |
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FIELD_PREP(MSI_INTR_MASK, msir));
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msg->address_hi = upper_32_bits(target_addr);
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msg->address_lo = lower_32_bits(target_addr);
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msg->data = hwirq_to_msi_data(data->hwirq);
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}
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/*
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* X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors. To maintain
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* the expected behaviour of .set_affinity for each MSI interrupt, the 16
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* MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs
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* for each core). The MSI vector is moved from 1 MSI GIC IRQ to another
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* MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core. As a
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* consequence, the total MSI vectors that X-Gene v1 supports will be
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* reduced to 256 (2048/8) vectors.
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*/
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static int hwirq_to_cpu(unsigned long hwirq)
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{
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return (hwirq % xgene_msi_ctrl.num_cpus);
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}
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static unsigned long hwirq_to_canonical_hwirq(unsigned long hwirq)
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{
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return (hwirq - hwirq_to_cpu(hwirq));
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msg->data = FIELD_GET(DATA_HWIRQ_MASK, data->hwirq);
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}
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static int xgene_msi_set_affinity(struct irq_data *irqdata,
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const struct cpumask *mask, bool force)
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{
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int target_cpu = cpumask_first(mask);
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int curr_cpu;
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curr_cpu = hwirq_to_cpu(irqdata->hwirq);
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if (curr_cpu == target_cpu)
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return IRQ_SET_MASK_OK_DONE;
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/* Update MSI number to target the new CPU */
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irqdata->hwirq = hwirq_to_canonical_hwirq(irqdata->hwirq) + target_cpu;
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irq_data_update_effective_affinity(irqdata, cpumask_of(target_cpu));
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/* Force the core code to regenerate the message */
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return IRQ_SET_MASK_OK;
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}
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@ -181,25 +167,23 @@ static int xgene_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct xgene_msi *msi = domain->host_data;
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int msi_irq;
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irq_hw_number_t hwirq;
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mutex_lock(&msi->bitmap_lock);
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msi_irq = bitmap_find_next_zero_area(msi->bitmap, NR_MSI_VEC, 0,
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msi->num_cpus, 0);
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if (msi_irq < NR_MSI_VEC)
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bitmap_set(msi->bitmap, msi_irq, msi->num_cpus);
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else
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msi_irq = -ENOSPC;
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hwirq = find_first_zero_bit(msi->bitmap, NR_MSI_VEC);
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if (hwirq < NR_MSI_VEC)
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set_bit(hwirq, msi->bitmap);
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mutex_unlock(&msi->bitmap_lock);
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if (msi_irq < 0)
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return msi_irq;
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if (hwirq >= NR_MSI_VEC)
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return -ENOSPC;
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irq_domain_set_info(domain, virq, msi_irq,
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irq_domain_set_info(domain, virq, hwirq,
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&xgene_msi_bottom_irq_chip, domain->host_data,
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handle_simple_irq, NULL, NULL);
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irqd_set_resend_when_in_progress(irq_get_irq_data(virq));
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return 0;
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}
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@ -209,12 +193,10 @@ static void xgene_irq_domain_free(struct irq_domain *domain,
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct xgene_msi *msi = irq_data_get_irq_chip_data(d);
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u32 hwirq;
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mutex_lock(&msi->bitmap_lock);
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hwirq = hwirq_to_canonical_hwirq(d->hwirq);
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bitmap_clear(msi->bitmap, hwirq, msi->num_cpus);
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clear_bit(d->hwirq, msi->bitmap);
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mutex_unlock(&msi->bitmap_lock);
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@ -235,10 +217,11 @@ static const struct msi_parent_ops xgene_msi_parent_ops = {
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.init_dev_msi_info = msi_lib_init_dev_msi_info,
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};
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static int xgene_allocate_domains(struct xgene_msi *msi)
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static int xgene_allocate_domains(struct device_node *node,
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struct xgene_msi *msi)
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{
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struct irq_domain_info info = {
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.fwnode = of_fwnode_handle(msi->node),
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.fwnode = of_fwnode_handle(node),
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.ops = &xgene_msi_domain_ops,
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.size = NR_MSI_VEC,
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.host_data = msi,
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@ -248,169 +231,114 @@ static int xgene_allocate_domains(struct xgene_msi *msi)
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return msi->inner_domain ? 0 : -ENOMEM;
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}
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static void xgene_free_domains(struct xgene_msi *msi)
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static int xgene_msi_init_allocator(struct device *dev)
|
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{
|
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if (msi->inner_domain)
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irq_domain_remove(msi->inner_domain);
|
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}
|
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|
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static int xgene_msi_init_allocator(struct xgene_msi *xgene_msi)
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{
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xgene_msi->bitmap = bitmap_zalloc(NR_MSI_VEC, GFP_KERNEL);
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if (!xgene_msi->bitmap)
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xgene_msi_ctrl->bitmap = devm_bitmap_zalloc(dev, NR_MSI_VEC, GFP_KERNEL);
|
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if (!xgene_msi_ctrl->bitmap)
|
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return -ENOMEM;
|
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|
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mutex_init(&xgene_msi->bitmap_lock);
|
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|
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xgene_msi->msi_groups = kcalloc(NR_HW_IRQS,
|
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sizeof(struct xgene_msi_group),
|
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GFP_KERNEL);
|
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if (!xgene_msi->msi_groups)
|
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return -ENOMEM;
|
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mutex_init(&xgene_msi_ctrl->bitmap_lock);
|
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|
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return 0;
|
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}
|
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|
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static void xgene_msi_isr(struct irq_desc *desc)
|
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{
|
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unsigned int *irqp = irq_desc_get_handler_data(desc);
|
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struct irq_chip *chip = irq_desc_get_chip(desc);
|
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struct xgene_msi_group *msi_groups;
|
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struct xgene_msi *xgene_msi;
|
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int msir_index, msir_val, hw_irq, ret;
|
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u32 intr_index, grp_select, msi_grp;
|
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struct xgene_msi *xgene_msi = xgene_msi_ctrl;
|
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unsigned long grp_pending;
|
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int msir_idx;
|
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u32 msi_grp;
|
||||
|
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chained_irq_enter(chip, desc);
|
||||
|
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msi_groups = irq_desc_get_handler_data(desc);
|
||||
xgene_msi = msi_groups->msi;
|
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msi_grp = msi_groups->msi_grp;
|
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msi_grp = irqp - xgene_msi->gic_irq;
|
||||
|
||||
/*
|
||||
* MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt
|
||||
* If bit x of this register is set (x is 0..7), one or more interrupts
|
||||
* corresponding to MSInIRx is set.
|
||||
*/
|
||||
grp_select = xgene_msi_int_read(xgene_msi, msi_grp);
|
||||
while (grp_select) {
|
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msir_index = ffs(grp_select) - 1;
|
||||
/*
|
||||
* Calculate MSInIRx address to read to check for interrupts
|
||||
* (refer to termination address and data assignment
|
||||
* described in xgene_compose_msi_msg() )
|
||||
*/
|
||||
msir_val = xgene_msi_ir_read(xgene_msi, msi_grp, msir_index);
|
||||
while (msir_val) {
|
||||
intr_index = ffs(msir_val) - 1;
|
||||
/*
|
||||
* Calculate MSI vector number (refer to the termination
|
||||
* address and data assignment described in
|
||||
* xgene_compose_msi_msg function)
|
||||
*/
|
||||
hw_irq = (((msir_index * IRQS_PER_IDX) + intr_index) *
|
||||
NR_HW_IRQS) + msi_grp;
|
||||
/*
|
||||
* As we have multiple hw_irq that maps to single MSI,
|
||||
* always look up the virq using the hw_irq as seen from
|
||||
* CPU0
|
||||
*/
|
||||
hw_irq = hwirq_to_canonical_hwirq(hw_irq);
|
||||
ret = generic_handle_domain_irq(xgene_msi->inner_domain, hw_irq);
|
||||
grp_pending = xgene_msi_int_read(xgene_msi, msi_grp);
|
||||
|
||||
for_each_set_bit(msir_idx, &grp_pending, IDX_PER_GROUP) {
|
||||
unsigned long msir;
|
||||
int intr_idx;
|
||||
|
||||
msir = xgene_msi_ir_read(xgene_msi, msi_grp, msir_idx);
|
||||
|
||||
for_each_set_bit(intr_idx, &msir, IRQS_PER_IDX) {
|
||||
irq_hw_number_t hwirq;
|
||||
int ret;
|
||||
|
||||
hwirq = compute_hwirq(msi_grp, msir_idx, intr_idx);
|
||||
ret = generic_handle_domain_irq(xgene_msi->inner_domain,
|
||||
hwirq);
|
||||
WARN_ON_ONCE(ret);
|
||||
msir_val &= ~(1 << intr_index);
|
||||
}
|
||||
grp_select &= ~(1 << msir_index);
|
||||
|
||||
if (!grp_select) {
|
||||
/*
|
||||
* We handled all interrupts happened in this group,
|
||||
* resample this group MSI_INTx register in case
|
||||
* something else has been made pending in the meantime
|
||||
*/
|
||||
grp_select = xgene_msi_int_read(xgene_msi, msi_grp);
|
||||
}
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static enum cpuhp_state pci_xgene_online;
|
||||
|
||||
static void xgene_msi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct xgene_msi *msi = platform_get_drvdata(pdev);
|
||||
for (int i = 0; i < NR_HW_IRQS; i++) {
|
||||
unsigned int irq = xgene_msi_ctrl->gic_irq[i];
|
||||
if (!irq)
|
||||
continue;
|
||||
irq_set_chained_handler_and_data(irq, NULL, NULL);
|
||||
}
|
||||
|
||||
if (pci_xgene_online)
|
||||
cpuhp_remove_state(pci_xgene_online);
|
||||
cpuhp_remove_state(CPUHP_PCI_XGENE_DEAD);
|
||||
|
||||
kfree(msi->msi_groups);
|
||||
|
||||
bitmap_free(msi->bitmap);
|
||||
msi->bitmap = NULL;
|
||||
|
||||
xgene_free_domains(msi);
|
||||
if (xgene_msi_ctrl->inner_domain)
|
||||
irq_domain_remove(xgene_msi_ctrl->inner_domain);
|
||||
}
|
||||
|
||||
static int xgene_msi_hwirq_alloc(unsigned int cpu)
|
||||
static int xgene_msi_handler_setup(struct platform_device *pdev)
|
||||
{
|
||||
struct xgene_msi *msi = &xgene_msi_ctrl;
|
||||
struct xgene_msi_group *msi_group;
|
||||
cpumask_var_t mask;
|
||||
struct xgene_msi *xgene_msi = xgene_msi_ctrl;
|
||||
int i;
|
||||
int err;
|
||||
|
||||
for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) {
|
||||
msi_group = &msi->msi_groups[i];
|
||||
if (!msi_group->gic_irq)
|
||||
continue;
|
||||
for (i = 0; i < NR_HW_IRQS; i++) {
|
||||
u32 msi_val;
|
||||
int irq, err;
|
||||
|
||||
irq_set_chained_handler_and_data(msi_group->gic_irq,
|
||||
xgene_msi_isr, msi_group);
|
||||
/*
|
||||
* MSInIRx registers are read-to-clear; before registering
|
||||
* interrupt handlers, read all of them to clear spurious
|
||||
* interrupts that may occur before the driver is probed.
|
||||
*/
|
||||
for (int msi_idx = 0; msi_idx < IDX_PER_GROUP; msi_idx++)
|
||||
xgene_msi_ir_read(xgene_msi, i, msi_idx);
|
||||
|
||||
/* Read MSIINTn to confirm */
|
||||
msi_val = xgene_msi_int_read(xgene_msi, i);
|
||||
if (msi_val) {
|
||||
dev_err(&pdev->dev, "Failed to clear spurious IRQ\n");
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, i);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
xgene_msi->gic_irq[i] = irq;
|
||||
|
||||
/*
|
||||
* Statically allocate MSI GIC IRQs to each CPU core.
|
||||
* With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated
|
||||
* to each core.
|
||||
*/
|
||||
if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
|
||||
cpumask_clear(mask);
|
||||
cpumask_set_cpu(cpu, mask);
|
||||
err = irq_set_affinity(msi_group->gic_irq, mask);
|
||||
if (err)
|
||||
pr_err("failed to set affinity for GIC IRQ");
|
||||
free_cpumask_var(mask);
|
||||
} else {
|
||||
pr_err("failed to alloc CPU mask for affinity\n");
|
||||
err = -EINVAL;
|
||||
}
|
||||
|
||||
irq_set_status_flags(irq, IRQ_NO_BALANCING);
|
||||
err = irq_set_affinity(irq, cpumask_of(i % num_possible_cpus()));
|
||||
if (err) {
|
||||
irq_set_chained_handler_and_data(msi_group->gic_irq,
|
||||
NULL, NULL);
|
||||
pr_err("failed to set affinity for GIC IRQ");
|
||||
return err;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(irq, xgene_msi_isr,
|
||||
&xgene_msi_ctrl->gic_irq[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xgene_msi_hwirq_free(unsigned int cpu)
|
||||
{
|
||||
struct xgene_msi *msi = &xgene_msi_ctrl;
|
||||
struct xgene_msi_group *msi_group;
|
||||
int i;
|
||||
|
||||
for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) {
|
||||
msi_group = &msi->msi_groups[i];
|
||||
if (!msi_group->gic_irq)
|
||||
continue;
|
||||
|
||||
irq_set_chained_handler_and_data(msi_group->gic_irq, NULL,
|
||||
NULL);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id xgene_msi_match_table[] = {
|
||||
{.compatible = "apm,xgene1-msi"},
|
||||
{},
|
||||
|
|
@ -419,14 +347,15 @@ static const struct of_device_id xgene_msi_match_table[] = {
|
|||
static int xgene_msi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
int rc, irq_index;
|
||||
struct xgene_msi *xgene_msi;
|
||||
int virt_msir;
|
||||
u32 msi_val, msi_idx;
|
||||
int rc;
|
||||
|
||||
xgene_msi = &xgene_msi_ctrl;
|
||||
xgene_msi_ctrl = devm_kzalloc(&pdev->dev, sizeof(*xgene_msi_ctrl),
|
||||
GFP_KERNEL);
|
||||
if (!xgene_msi_ctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, xgene_msi);
|
||||
xgene_msi = xgene_msi_ctrl;
|
||||
|
||||
xgene_msi->msi_regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
||||
if (IS_ERR(xgene_msi->msi_regs)) {
|
||||
|
|
@ -434,66 +363,26 @@ static int xgene_msi_probe(struct platform_device *pdev)
|
|||
goto error;
|
||||
}
|
||||
xgene_msi->msi_addr = res->start;
|
||||
xgene_msi->node = pdev->dev.of_node;
|
||||
xgene_msi->num_cpus = num_possible_cpus();
|
||||
|
||||
rc = xgene_msi_init_allocator(xgene_msi);
|
||||
rc = xgene_msi_init_allocator(&pdev->dev);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev, "Error allocating MSI bitmap\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
rc = xgene_allocate_domains(xgene_msi);
|
||||
rc = xgene_allocate_domains(dev_of_node(&pdev->dev), xgene_msi);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev, "Failed to allocate MSI domain\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) {
|
||||
virt_msir = platform_get_irq(pdev, irq_index);
|
||||
if (virt_msir < 0) {
|
||||
rc = virt_msir;
|
||||
goto error;
|
||||
}
|
||||
xgene_msi->msi_groups[irq_index].gic_irq = virt_msir;
|
||||
xgene_msi->msi_groups[irq_index].msi_grp = irq_index;
|
||||
xgene_msi->msi_groups[irq_index].msi = xgene_msi;
|
||||
}
|
||||
|
||||
/*
|
||||
* MSInIRx registers are read-to-clear; before registering
|
||||
* interrupt handlers, read all of them to clear spurious
|
||||
* interrupts that may occur before the driver is probed.
|
||||
*/
|
||||
for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) {
|
||||
for (msi_idx = 0; msi_idx < IDX_PER_GROUP; msi_idx++)
|
||||
xgene_msi_ir_read(xgene_msi, irq_index, msi_idx);
|
||||
|
||||
/* Read MSIINTn to confirm */
|
||||
msi_val = xgene_msi_int_read(xgene_msi, irq_index);
|
||||
if (msi_val) {
|
||||
dev_err(&pdev->dev, "Failed to clear spurious IRQ\n");
|
||||
rc = -EINVAL;
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "pci/xgene:online",
|
||||
xgene_msi_hwirq_alloc, NULL);
|
||||
if (rc < 0)
|
||||
goto err_cpuhp;
|
||||
pci_xgene_online = rc;
|
||||
rc = cpuhp_setup_state(CPUHP_PCI_XGENE_DEAD, "pci/xgene:dead", NULL,
|
||||
xgene_msi_hwirq_free);
|
||||
rc = xgene_msi_handler_setup(pdev);
|
||||
if (rc)
|
||||
goto err_cpuhp;
|
||||
goto error;
|
||||
|
||||
dev_info(&pdev->dev, "APM X-Gene PCIe MSI driver loaded\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_cpuhp:
|
||||
dev_err(&pdev->dev, "failed to add CPU MSI notifier\n");
|
||||
error:
|
||||
xgene_msi_remove(pdev);
|
||||
return rc;
|
||||
|
|
@ -507,9 +396,4 @@ static struct platform_driver xgene_msi_driver = {
|
|||
.probe = xgene_msi_probe,
|
||||
.remove = xgene_msi_remove,
|
||||
};
|
||||
|
||||
static int __init xgene_pcie_msi_init(void)
|
||||
{
|
||||
return platform_driver_register(&xgene_msi_driver);
|
||||
}
|
||||
subsys_initcall(xgene_pcie_msi_init);
|
||||
builtin_platform_driver(xgene_msi_driver);
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/jiffies.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_pci.h>
|
||||
|
|
@ -53,11 +54,9 @@
|
|||
#define XGENE_V1_PCI_EXP_CAP 0x40
|
||||
|
||||
/* PCIe IP version */
|
||||
#define XGENE_PCIE_IP_VER_UNKN 0
|
||||
#define XGENE_PCIE_IP_VER_1 1
|
||||
#define XGENE_PCIE_IP_VER_2 2
|
||||
|
||||
#if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
|
||||
struct xgene_pcie {
|
||||
struct device_node *node;
|
||||
struct device *dev;
|
||||
|
|
@ -188,7 +187,6 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
|
|||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
|
||||
static int xgene_get_csr_resource(struct acpi_device *adev,
|
||||
|
|
@ -279,7 +277,6 @@ const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI_XGENE)
|
||||
static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr,
|
||||
u32 flags, u64 size)
|
||||
{
|
||||
|
|
@ -594,6 +591,24 @@ static struct pci_ops xgene_pcie_ops = {
|
|||
.write = pci_generic_config_write32,
|
||||
};
|
||||
|
||||
static bool xgene_check_pcie_msi_ready(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct irq_domain *d;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_PCI_XGENE_MSI))
|
||||
return true;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "apm,xgene1-msi");
|
||||
if (!np)
|
||||
return true;
|
||||
|
||||
d = irq_find_matching_host(np, DOMAIN_BUS_PCI_MSI);
|
||||
of_node_put(np);
|
||||
|
||||
return d && irq_domain_is_msi_parent(d);
|
||||
}
|
||||
|
||||
static int xgene_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -602,6 +617,10 @@ static int xgene_pcie_probe(struct platform_device *pdev)
|
|||
struct pci_host_bridge *bridge;
|
||||
int ret;
|
||||
|
||||
if (!xgene_check_pcie_msi_ready())
|
||||
return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
|
||||
"MSI driver not ready\n");
|
||||
|
||||
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
|
||||
if (!bridge)
|
||||
return -ENOMEM;
|
||||
|
|
@ -610,10 +629,7 @@ static int xgene_pcie_probe(struct platform_device *pdev)
|
|||
|
||||
port->node = of_node_get(dn);
|
||||
port->dev = dev;
|
||||
|
||||
port->version = XGENE_PCIE_IP_VER_UNKN;
|
||||
if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
|
||||
port->version = XGENE_PCIE_IP_VER_1;
|
||||
port->version = XGENE_PCIE_IP_VER_1;
|
||||
|
||||
ret = xgene_pcie_map_reg(port, pdev);
|
||||
if (ret)
|
||||
|
|
@ -647,4 +663,3 @@ static struct platform_driver xgene_pcie_driver = {
|
|||
.probe = xgene_pcie_probe,
|
||||
};
|
||||
builtin_platform_driver(xgene_pcie_driver);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -90,7 +90,6 @@ enum cpuhp_state {
|
|||
CPUHP_RADIX_DEAD,
|
||||
CPUHP_PAGE_ALLOC,
|
||||
CPUHP_NET_DEV_DEAD,
|
||||
CPUHP_PCI_XGENE_DEAD,
|
||||
CPUHP_IOMMU_IOVA_DEAD,
|
||||
CPUHP_AP_ARM_CACHE_B15_RAC_DEAD,
|
||||
CPUHP_PADATA_DEAD,
|
||||
|
|
|
|||
|
|
@ -551,7 +551,13 @@ void handle_simple_irq(struct irq_desc *desc)
|
|||
{
|
||||
guard(raw_spinlock)(&desc->lock);
|
||||
|
||||
if (!irq_can_handle(desc))
|
||||
if (!irq_can_handle_pm(desc)) {
|
||||
if (irqd_needs_resend_when_in_progress(&desc->irq_data))
|
||||
desc->istate |= IRQS_PENDING;
|
||||
return;
|
||||
}
|
||||
|
||||
if (!irq_can_handle_actions(desc))
|
||||
return;
|
||||
|
||||
kstat_incr_irqs_this_cpu(desc);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user