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i2c: spacemit: configure ILCR/IWCR for accurate SCL frequency
The SpacemiT I2C controller's SCL (Serial Clock Line) frequency for master mode operations is determined by the ILCR (I2C Load Count Register). Previously, the driver relied on the hardware's reset default values for this register. The hardware's default ILCR values (SLV=0x156, FLV=0x5d) yield SCL frequencies lower than intended. For example, with the default 31.5 MHz input clock, these default settings result in an SCL frequency of approximately 93 kHz (standard mode) when targeting 100 kHz, and approximately 338 kHz (fast mode) when targeting 400 kHz. These frequencies are below the 100 kHz/400 kHz nominal speeds. This patch integrates the SCL frequency management into the Common Clock Framework (CCF). Specifically, the ILCR register, which acts as a frequency divider for the SCL clock, is now registered as a managed clock (scl_clk) within the CCF. The actual hardware timing formulas are: - standard mode: SCL = FCLK / (2 * SLV + 8) - fast mode: SCL = FCLK / (2 * FLV + 10) These formulas are only valid when the IWCR (Wait Count Register) is programmed to 0x142A, a value specified by the I2C IP designer. The driver now initializes IWCR to this value during controller init. Reviewed-by: Yixun Lan <dlan@gentoo.org> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Reviewed-by: Alex Elder <elder@riscstar.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-1-8c2dde5c3ed5@linux.spacemit.com
This commit is contained in:
Troy Mitchell
Andi Shyti
parent
dc59e4fea9
commit
0ed3fa2370
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@ -793,7 +793,7 @@ config I2C_JZ4780
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config I2C_K1
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tristate "SpacemiT K1 I2C adapter"
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depends on ARCH_SPACEMIT || COMPILE_TEST
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depends on OF
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depends on OF && COMMON_CLK
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default ARCH_SPACEMIT
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help
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This option enables support for the I2C interface on the SpacemiT K1
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@ -4,7 +4,9 @@
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/i2c.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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@ -17,6 +19,8 @@
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#define SPACEMIT_ISR 0x4 /* Status register */
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#define SPACEMIT_IDBR 0xc /* Data buffer register */
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#define SPACEMIT_IRCR 0x18 /* Reset cycle counter */
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#define SPACEMIT_ILCR 0x10 /* Load Count Register */
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#define SPACEMIT_IWCR 0x14 /* Wait Count Register */
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#define SPACEMIT_IBMR 0x1c /* Bus monitor register */
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/* SPACEMIT_ICR register fields */
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@ -88,6 +92,19 @@
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#define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */
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#define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */
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#define SPACEMIT_LCR_LV_STANDARD_MASK GENMASK(8, 0)
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#define SPACEMIT_LCR_LV_FAST_MASK GENMASK(17, 9)
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/* SPACEMIT_IWCR register fields */
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#define SPACEMIT_WCR_COUNT GENMASK(4, 0)
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#define SPACEMIT_WCR_HS_COUNT1 GENMASK(9, 5)
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#define SPACEMIT_WCR_HS_COUNT2 GENMASK(14, 10)
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/* Required by I2C IP for correct SCL timing */
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#define SPACEMIT_IWCR_INIT_VALUE (FIELD_PREP(SPACEMIT_WCR_COUNT, 10) | \
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FIELD_PREP(SPACEMIT_WCR_HS_COUNT1, 1) | \
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FIELD_PREP(SPACEMIT_WCR_HS_COUNT2, 5))
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/* i2c bus recover timeout: us */
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#define SPACEMIT_I2C_BUS_BUSY_TIMEOUT 100000
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@ -109,11 +126,20 @@ enum spacemit_i2c_state {
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SPACEMIT_STATE_WRITE,
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};
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enum spacemit_i2c_mode {
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SPACEMIT_MODE_STANDARD,
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SPACEMIT_MODE_FAST
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};
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/* i2c-spacemit driver's main struct */
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struct spacemit_i2c_dev {
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struct device *dev;
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struct i2c_adapter adapt;
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struct clk_hw scl_clk_hw;
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struct clk *scl_clk;
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enum spacemit_i2c_mode mode;
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/* hardware resources */
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void __iomem *base;
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int irq;
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@ -135,6 +161,85 @@ struct spacemit_i2c_dev {
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u32 status;
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};
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static void spacemit_i2c_scl_clk_disable_unprepare(void *data)
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{
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clk_disable_unprepare(data);
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}
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/*
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* Calculate the ILCR divider value (lv) from the target SCL rate.
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*
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* Hardware timing formulas:
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* - standard mode: SCL = FCLK / (2 * SLV + 8)
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* - fast mode: SCL = FCLK / (2 * FLV + 10)
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*/
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static u32 spacemit_i2c_calc_lv(struct spacemit_i2c_dev *i2c,
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unsigned long parent_rate,
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unsigned long target_rate)
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{
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u32 offset, denom;
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offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10;
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denom = DIV_ROUND_CLOSEST(parent_rate, target_rate);
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return (denom <= offset) ? 0 : DIV_ROUND_CLOSEST(denom - offset, 2);
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}
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static int spacemit_i2c_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw);
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u32 lv, lcr, mask;
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lv = spacemit_i2c_calc_lv(i2c, parent_rate, rate);
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mask = (i2c->mode == SPACEMIT_MODE_STANDARD) ?
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SPACEMIT_LCR_LV_STANDARD_MASK : SPACEMIT_LCR_LV_FAST_MASK;
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lcr = readl(i2c->base + SPACEMIT_ILCR);
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lcr &= ~mask;
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lcr |= field_prep(mask, lv);
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writel(lcr, i2c->base + SPACEMIT_ILCR);
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return 0;
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}
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static int spacemit_i2c_clk_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw);
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u32 lv, offset;
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lv = spacemit_i2c_calc_lv(i2c, req->best_parent_rate, req->rate);
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offset = (i2c->mode == SPACEMIT_MODE_STANDARD) ? 8 : 10;
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req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, lv * 2 + offset);
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return 0;
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}
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static unsigned long spacemit_i2c_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct spacemit_i2c_dev *i2c = container_of(hw, struct spacemit_i2c_dev, scl_clk_hw);
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u32 lcr, lv = 0;
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lcr = readl(i2c->base + SPACEMIT_ILCR);
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if (i2c->mode == SPACEMIT_MODE_STANDARD) {
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lv = FIELD_GET(SPACEMIT_LCR_LV_STANDARD_MASK, lcr);
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return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 8);
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}
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lv = FIELD_GET(SPACEMIT_LCR_LV_FAST_MASK, lcr);
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return DIV_ROUND_CLOSEST(parent_rate, lv * 2 + 10);
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}
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static const struct clk_ops spacemit_i2c_clk_ops = {
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.set_rate = spacemit_i2c_clk_set_rate,
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.determine_rate = spacemit_i2c_clk_determine_rate,
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.recalc_rate = spacemit_i2c_clk_recalc_rate,
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};
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static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c)
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{
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u32 val;
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@ -153,6 +258,28 @@ static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c)
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writel(val, i2c->base + SPACEMIT_ICR);
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}
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static int spacemit_i2c_register_scl_clk(struct spacemit_i2c_dev *i2c)
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{
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struct clk_init_data init = {};
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char name[64];
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int ret;
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ret = snprintf(name, sizeof(name), "%s_scl_clk", dev_name(i2c->dev));
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if (ret >= ARRAY_SIZE(name))
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dev_warn(i2c->dev, "scl clock name truncated");
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init.name = name;
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init.ops = &spacemit_i2c_clk_ops;
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init.parent_data = (struct clk_parent_data[]) {
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{ .fw_name = "func" },
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};
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init.num_parents = 1;
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i2c->scl_clk_hw.init = &init;
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return devm_clk_hw_register(i2c->dev, &i2c->scl_clk_hw);
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}
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static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c)
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{
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writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR);
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@ -286,7 +413,7 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c)
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val |= SPACEMIT_CR_MSDIE;
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}
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if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ)
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if (i2c->mode == SPACEMIT_MODE_FAST)
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val |= SPACEMIT_CR_MODE_FAST;
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/* disable response to general call */
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@ -309,6 +436,14 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c)
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writel(val, i2c->base + SPACEMIT_IRCR);
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spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK);
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/*
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* Initialize IWCR to the value specified by the I2C IP designer.
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* The SCL frequency formulas (SCL = FCLK / (2*SLV+8) for standard
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* mode, SCL = FCLK / (2*FLV+10) for fast mode) are only valid when
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* IWCR contains this specific value.
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*/
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writel(SPACEMIT_IWCR_INIT_VALUE, i2c->base + SPACEMIT_IWCR);
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}
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static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c)
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@ -703,14 +838,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev)
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dev_warn(dev, "failed to read clock-frequency property: %d\n", ret);
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/* For now, this driver doesn't support high-speed. */
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if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) {
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dev_warn(dev, "unsupported clock frequency %u; using %u\n",
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i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ);
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if (i2c->clock_freq > SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ &&
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i2c->clock_freq <= SPACEMIT_I2C_MAX_FAST_MODE_FREQ) {
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i2c->mode = SPACEMIT_MODE_FAST;
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} else if (i2c->clock_freq && i2c->clock_freq <= SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) {
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i2c->mode = SPACEMIT_MODE_STANDARD;
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} else {
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dev_warn(i2c->dev, "invalid clock-frequency, fallback to fast mode");
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i2c->mode = SPACEMIT_MODE_FAST;
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i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ;
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} else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) {
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dev_warn(dev, "unsupported clock frequency %u; using %u\n",
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i2c->clock_freq, SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ);
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i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ;
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}
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i2c->dev = &pdev->dev;
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@ -732,6 +868,15 @@ static int spacemit_i2c_probe(struct platform_device *pdev)
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if (IS_ERR(clk))
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return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock");
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ret = spacemit_i2c_register_scl_clk(i2c);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register scl clock\n");
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i2c->scl_clk = devm_clk_hw_get_clk(dev, &i2c->scl_clk_hw, "scl");
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if (IS_ERR(i2c->scl_clk))
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return dev_err_probe(dev, PTR_ERR(i2c->scl_clk),
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"failed to get scl clock\n");
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clk = devm_clk_get_enabled(dev, "bus");
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if (IS_ERR(clk))
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return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock");
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@ -741,6 +886,19 @@ static int spacemit_i2c_probe(struct platform_device *pdev)
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return dev_err_probe(dev, PTR_ERR(rst),
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"failed to acquire deasserted reset\n");
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ret = clk_set_rate(i2c->scl_clk, i2c->clock_freq);
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if (ret)
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return dev_err_probe(dev, ret, "failed to set rate for SCL clock");
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ret = clk_prepare_enable(i2c->scl_clk);
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if (ret)
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return dev_err_probe(dev, ret, "failed to prepare and enable clock");
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ret = devm_add_action_or_reset(dev, spacemit_i2c_scl_clk_disable_unprepare,
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i2c->scl_clk);
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if (ret)
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return ret;
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spacemit_i2c_reset(i2c);
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i2c_set_adapdata(&i2c->adapt, i2c);
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